Commit Graph

70 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes f170f8bff6 Add asm parsing support w/ testcases for strex/ldrex family of instructions
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
Bill Wendling 00f0cddfd4 We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.

llvm-svn: 127986
2011-03-21 04:13:46 +00:00
Jim Grosbach c5efcbad71 Remove some dead patterns.
llvm-svn: 127601
2011-03-14 18:34:35 +00:00
Anton Korobeynikov e7410dd0d5 Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101
2011-03-05 18:43:32 +00:00
Bruno Cardoso Lopes 90d1dfe4c6 Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
2011-02-14 13:09:44 +00:00
Owen Anderson c3c7f5dd56 Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.

With this, we can properly pretty-print and encode assembly like:
	mrc p15, #0, r3, c13, c0, #3

Fixes <rdar://problem/8857858>.

llvm-svn: 123404
2011-01-13 21:46:02 +00:00
Bill Wendling 092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Jim Grosbach 7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
2010-11-29 22:37:40 +00:00
Jim Grosbach 58bc36a3a9 ARM Pseudo-ize tBR_JTr.
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
Chris Lattner a76eab433a stub out a powerpc MCInstPrinter implementation.
llvm-svn: 119059
2010-11-14 19:40:38 +00:00
Evan Cheng 9c40af415f For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
llvm-svn: 118945
2010-11-12 23:46:13 +00:00
Jim Grosbach fd96701456 Remove unused function.
llvm-svn: 118141
2010-11-03 01:35:15 +00:00
Jim Grosbach e7f7de95e0 Remove the no longer used 'Modifier' optional operand to the ARM
printOperand() asm printer helper functions. rdar://8425198

llvm-svn: 118140
2010-11-03 01:11:15 +00:00
Jim Grosbach 50ba3c09bf Remove unused function.
llvm-svn: 118139
2010-11-03 01:07:48 +00:00
Jim Grosbach c6af2b4066 Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Chris Lattner f20f79808e hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.

llvm-svn: 117609
2010-10-28 21:37:33 +00:00
Jim Grosbach e6fe1a03c7 imm12 operands aren't Thumb2 only, so rename the printer helper function.
llvm-svn: 117291
2010-10-25 20:00:01 +00:00
Jim Grosbach 7e72ec6626 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
2010-10-13 21:00:04 +00:00
Jim Grosbach ff1751c0a6 PrintSpecial() can go away now.
llvm-svn: 115376
2010-10-01 23:27:48 +00:00
Jim Grosbach 0e854f3d43 Rename the AsmPrinter directory to InstPrinter for those targets that have
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.

llvm-svn: 115360
2010-10-01 22:39:28 +00:00