3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
...
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
...
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
182b6a077e
Tidy up a bit.
...
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
ae672f8118
Add comment.
...
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
e1154eef0b
ARM parsing aliases for data-size suffices on VST1.
...
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
...
llvm-svn: 145442
2011-11-29 22:38:04 +00:00
312b97c267
comment.
...
llvm-svn: 145422
2011-11-29 19:33:49 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
...
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
ae9132207f
Better fix for ARM MOVT relocation encoding of thumb bit.
...
Replaces r145318 with a more targetted fix for the relocation handling.
llvm-svn: 145346
2011-11-29 01:15:25 +00:00
12330650f8
Silence wrong warnings from GCC about variables possibly being used
...
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
llvm-svn: 145239
2011-11-28 10:31:27 +00:00
7ba71be392
Move code into anonymous namespaces.
...
llvm-svn: 145154
2011-11-26 23:01:57 +00:00
989eaf6e3f
ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
...
llvm-svn: 145129
2011-11-25 09:19:57 +00:00
ee93ff736a
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
...
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
0eff3e5c21
Add TODO comment.
...
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
15b2498e88
Dead code.
...
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
ce619ddfc5
Don't unconditionally set the kill flag.
...
rdar://10456186
llvm-svn: 144872
2011-11-17 01:16:53 +00:00
d3f02cbce9
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
7ccdb7c0ae
Fix encoding of NOP used for padding in ARM mode .align.
...
llvm-svn: 144842
2011-11-16 22:40:25 +00:00
bfe5c5c968
ARM assembly parsing for shifted register operands for MOV instruction.
...
llvm-svn: 144837
2011-11-16 21:50:05 +00:00
01e0439240
Clean up debug printing of ARM shifted operands.
...
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
3127ab6d8f
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
...
llvm-svn: 144814
2011-11-16 19:12:24 +00:00
1a2f9ee3c8
ARM assembly parsing for RRX mnemonic.
...
rdar://9704684
llvm-svn: 144812
2011-11-16 19:05:59 +00:00
80979b6ea6
Check to make sure we can select the instruction before trying to put the
...
operands into a register. Otherwise, we may materialize dead code.
llvm-svn: 144805
2011-11-16 18:39:44 +00:00
abcac56869
ARM mode aliases for bitwise instructions w/ register operands.
...
rdar://9704684
llvm-svn: 144803
2011-11-16 18:31:45 +00:00
0ca7ce389c
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
...
llvm-svn: 144798
2011-11-16 17:09:59 +00:00
b345060a85
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
...
llvm-svn: 144794
2011-11-16 09:18:28 +00:00
ecb2908bf9
Sink codegen optimization level into MCCodeGenInfo along side relocation model
...
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
2011-11-16 08:38:26 +00:00
f6d1728d8f
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
...
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
llvm-svn: 144781
2011-11-16 07:11:57 +00:00
af13d767a2
Add FIXME comment.
...
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
653183fd5c
Enable -widen-vmovs by default.
...
This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
llvm-svn: 144734
2011-11-15 23:53:18 +00:00
e891fe8d6c
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
003cea6011
ARM assembly parsing for data type suffices on NEON VMOV aliases.
...
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
75fb4abcdc
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
a01033709f
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
...
llvm-svn: 144710
2011-11-15 22:15:10 +00:00
8279c1828f
ARM accept an immediate offset in memory operands w/o the '#'.
...
llvm-svn: 144709
2011-11-15 22:14:41 +00:00
8d579230c6
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
...
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
llvm-svn: 144701
2011-11-15 21:45:55 +00:00
84f0ba5747
ARM size suffix on VFP single-precision 'vmov' is optional.
...
rdar://10435114
llvm-svn: 144698
2011-11-15 21:18:35 +00:00
a92a5d8548
Fix typo.
...
llvm-svn: 144695
2011-11-15 21:01:30 +00:00
131b45e632
ARM alternate size suffices for VTRN instructions.
...
rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
05060f0748
Fix a misplaced paren bug.
...
llvm-svn: 144692
2011-11-15 20:30:41 +00:00
5803f6d5a2
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
c5b1bc561e
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
72dfd20aba
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
efa7e95d06
Thumb2 two-operand 'mul' instruction wide encoding parsing.
...
rdar://10449724
llvm-svn: 144684
2011-11-15 19:55:16 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
...
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
6efa7b9852
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
2aabaa704a
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144650
2011-11-15 17:49:59 +00:00
e5cbd3c3fb
Fix typo in comment.
...
llvm-svn: 144633
2011-11-15 07:50:05 +00:00
465101bb0e
Make use of MachinePointerInfo::getFixedStack. This removes all mention
...
of PseudoSourceValue from lib/Target/.
llvm-svn: 144632
2011-11-15 07:34:52 +00:00
0745e645e0
Remove some unnecessary includes of PseudoSourceValue.h.
...
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
7ca4b6eb5c
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
...
integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
29cdcda80d
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144606
2011-11-15 01:46:57 +00:00
a498af2b1d
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
72838a0345
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
750de7a399
Add explanatory comment.
...
llvm-svn: 144589
2011-11-14 23:21:09 +00:00
9c2d9d597b
Split out the plain '.{8|16|32|64}' suffix handling.
...
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
llvm-svn: 144588
2011-11-14 23:20:14 +00:00
3d6c0e0bb2
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
...
rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
057b6d3476
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
...
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
llvm-svn: 144585
2011-11-14 23:04:09 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
ab7223e99a
Add support for inlining small memcpys.
...
rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
45110fdf8d
Fix a performance regression from r144565. Positive offsets were being lowered
...
into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
7996b15724
ARM assembly parsing type suffix options for VLDR/VSTR.
...
rdar://10435076
llvm-svn: 144575
2011-11-14 22:28:39 +00:00
adfd200bcb
Add support for Thumb load/stores with negative offsets.
...
rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
ee201faeac
Tidy up. 80 column.
...
llvm-svn: 144538
2011-11-14 17:52:47 +00:00
2a1df883d0
Add support for ARM halfword load/stores and signed byte loads with negative
...
offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
1198d894d0
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
...
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
a476e391f1
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
...
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
5196efdf36
Fix comments.
...
llvm-svn: 144490
2011-11-13 04:25:02 +00:00
c8cfd3a8fb
Add support for emitting both signed- and zero-extend loads. Fix
...
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
52823cc91c
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
...
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
3a3d8e82bc
ARM refactor simple immediate asm operand render methods.
...
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
llvm-svn: 144439
2011-11-12 00:58:43 +00:00
8ca13deecf
Re-apply 144430, this time with the associated isel and disassmbler bits.
...
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
155763b630
Oops. Missed the isel half of this. revert while I sort that out.
...
llvm-svn: 144431
2011-11-11 23:51:31 +00:00
28f721a2b4
ARM assembly parsing for VST1 two-register encoding.
...
llvm-svn: 144430
2011-11-11 23:45:47 +00:00
609d113874
ARM optional size suffix for VLDR/VSTR syntax.
...
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
a7ebc5617d
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
...
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
12952fef71
ARM vldm and vstm VFP instructions can take a data type suffix.
...
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
llvm-svn: 144422
2011-11-11 23:08:10 +00:00
b68eeb3852
Nuke no longer accurate comment.
...
llvm-svn: 144411
2011-11-11 22:30:06 +00:00
28c1d18434
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
...
Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
85a2343b01
ARM allow Q registers in vldm/vstm register lists.
...
rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
48b5bbffed
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
...
llvm-svn: 144384
2011-11-11 12:39:41 +00:00
e19b0a9eb8
Rename variables to avoid confusion. No functionallity change intended.
...
llvm-svn: 144377
2011-11-11 06:27:41 +00:00
7ddd63ce4e
Add support for using immediates with select instructions.
...
rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
c4a001478c
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
...
llvm-svn: 144361
2011-11-11 03:16:38 +00:00
023ede5649
When loading a value, treat an i1 as an i8.
...
llvm-svn: 144356
2011-11-11 02:38:59 +00:00
2a3503e061
Add support for using MVN to materialize negative constants.
...
rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
6d617b48c7
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
...
llvm-svn: 144344
2011-11-11 00:23:56 +00:00
d9a9be269c
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
...
rdar://10429490
llvm-svn: 144338
2011-11-10 23:58:34 +00:00
afad053141
ARM let processInstruction() tranforms chain.
...
llvm-svn: 144337
2011-11-10 23:42:14 +00:00
9bded9dc24
Thumb2 parsing for push/pop w/ hi registers in the reglist.
...
rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
a113eb0205
Thumb1 diagnostics for reglist on PUSH/POP fix.
...
Was not checking the first register in the register list.
llvm-svn: 144329
2011-11-10 23:01:27 +00:00
5a5ce63742
Thumb MUL assembly parsing for 3-operand form.
...
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
d1762e00e2
When in ARM mode, LDRH/STRH require special handling of negative offsets.
...
For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
42ba6286b6
ARM .thumb_func directive for quoted symbol names.
...
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
llvm-svn: 144315
2011-11-10 20:48:53 +00:00
c14871cc67
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
61db5a59f7
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
3fbd094ad9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
233c9304a8
llvm-build: Add --native-target and --enable-targets options, and add logic to
...
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
82219ad4dc
llvm-build: Add an explicit component type to represent targets.
...
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
a48485a37f
Tidy up.
...
llvm-svn: 144244
2011-11-10 00:02:33 +00:00
25bc090170
Thumb2 assembly parsing STMDB w/ optional .w suffix.
...
rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
2d4055b683
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
...
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
2f27fab6ed
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
...
rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
595d419427
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
94307f6ba6
Hide cpu name checking in ARMSubtarget.
...
llvm-svn: 144154
2011-11-09 01:57:03 +00:00
c3770ac687
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
...
llvm-svn: 144123
2011-11-08 21:21:09 +00:00
0439cfc41f
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
...
No functional change intended.
llvm-svn: 144122
2011-11-08 21:12:00 +00:00
b85fcd07df
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
...
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
llvm-svn: 144102
2011-11-08 18:56:23 +00:00
82cd9e81fc
Added invariant field to the DAG.getLoad method and changed all calls.
...
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
6f84fed675
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
...
llvm-svn: 144057
2011-11-08 01:43:53 +00:00
5de1bea5c9
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
...
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
fa75530ff0
Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well.
...
llvm-svn: 144021
2011-11-07 21:43:40 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
...
As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
20baffb257
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
...
llvm-svn: 143891
2011-11-06 20:37:06 +00:00
d0191a53c9
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
...
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
f0055f61fb
Allow i1 to be promoted to i32 for ARM APCS calling convention.
...
llvm-svn: 143755
2011-11-05 00:02:56 +00:00
5b8fdd7b62
Cannot create a result register for non-legal types.
...
llvm-svn: 143749
2011-11-04 23:45:39 +00:00
e8b8b77307
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
...
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
llvm-svn: 143743
2011-11-04 23:09:49 +00:00
67f96887aa
Enable support for materializing i1, i8, and i16 integers via move immediate.
...
llvm-svn: 143739
2011-11-04 22:29:00 +00:00
4a9c6426ff
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
...
added a layer of indirection with no value (not even conciseness).
llvm-svn: 143727
2011-11-04 19:04:23 +00:00
1ddeb167e8
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen.
...
llvm-svn: 143675
2011-11-04 01:48:58 +00:00
8a98ec4d4b
Indentation.
...
llvm-svn: 143670
2011-11-04 00:58:10 +00:00
f3e73ad5da
Add fast-isel support for returning i1, i8, and i16.
...
llvm-svn: 143669
2011-11-04 00:50:21 +00:00
198b7ffc11
Reapply r143206, with fixes. Disallow physical register lifetimes
...
across calls, and only check for nested dependences on the special
call-sequence-resource register.
llvm-svn: 143660
2011-11-03 21:49:52 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
...
llvm-svn: 143634
2011-11-03 18:53:17 +00:00
bf5f4bec1a
Add support for sign-extending non-legal types in SelectSIToFP().
...
llvm-svn: 143603
2011-11-03 02:04:59 +00:00
1f4603d498
Fixed parameter name.
...
llvm-svn: 143594
2011-11-02 23:37:04 +00:00
9929c423a1
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
...
llvm-svn: 143582
2011-11-02 22:52:45 +00:00
9cf803c4bf
Add support for comparing integer non-legal types.
...
llvm-svn: 143559
2011-11-02 18:08:25 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
...
llvm-svn: 143557
2011-11-02 18:03:14 +00:00
ec5c5f7008
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
...
llvm-svn: 143553
2011-11-02 17:46:18 +00:00
fad59dab62
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
...
llvm-svn: 143552
2011-11-02 17:41:23 +00:00
4489f948a7
Factor out an EmitIntExt function. No functionality change intended.
...
llvm-svn: 143547
2011-11-02 17:20:24 +00:00
ee7e452571
Factor out a SelectTrunc function. No functionality change intended.
...
llvm-svn: 143523
2011-11-02 00:18:48 +00:00
5c6b6346bc
ARM label operands can be quoted.
...
For example, labels from Objective-C sources.
llvm-svn: 143511
2011-11-01 22:38:31 +00:00
7f1f3bd868
ARM label operands can have an optional '#' before them.
...
llvm-svn: 143510
2011-11-01 22:37:37 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
...
llvm-svn: 143507
2011-11-01 22:18:13 +00:00
fb2f1d61f4
ARM VLD/VST assembly parsing for symbolic address operands.
...
llvm-svn: 143413
2011-11-01 01:24:45 +00:00
05df460269
ARM VST1 w/ writeback assembly parsing and encoding.
...
llvm-svn: 143369
2011-10-31 21:50:31 +00:00
e4c8e692f2
ARM writeback vs. stride operands for VST/VLD.
...
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.
llvm-svn: 143356
2011-10-31 19:11:23 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
...
llvm-svn: 143351
2011-10-31 17:17:32 +00:00
9b9c970148
Revert r143206, as there are still some failing tests.
...
llvm-svn: 143262
2011-10-29 00:41:52 +00:00
3d785edee2
ARM mode 'mov' to 'mvn' assembler alias.
...
llvm-svn: 143237
2011-10-28 22:50:54 +00:00
b009a872d7
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
...
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
llvm-svn: 143235
2011-10-28 22:36:30 +00:00
409b694c6c
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
...
llvm-svn: 143220
2011-10-28 20:43:24 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
...
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
73057ad24f
Reapply r143177 and r143179 (reverting r143188), with scheduler
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fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
llvm-svn: 143206
2011-10-28 17:55:38 +00:00
effd094438
Revert r143202.
...
llvm-svn: 143203
2011-10-28 17:38:30 +00:00
df53d4fd61
Specify fixed bits on CPS instructions to enable roundtripping.
...
llvm-svn: 143202
2011-10-28 17:29:39 +00:00
7a49575d7f
Thumb2 ADD/SUB instructions encoding selection outside IT block.
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Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
llvm-svn: 143201
2011-10-28 16:57:07 +00:00
225a7037d6
Speculatively disable Dan's commits 143177 and 143179 to see if
...
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
llvm-svn: 143188
2011-10-28 09:55:57 +00:00
4db3f7dd83
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
...
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
llvm-svn: 143177
2011-10-28 01:29:32 +00:00
080a499ee0
ARM Allow 'q' registers in VLD/VST vector lists.
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Just treat it as if the constituent D registers where specified.
rdar://10348896
llvm-svn: 143167
2011-10-28 00:06:50 +00:00
8a6ebd085a
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
...
llvm-svn: 143162
2011-10-27 22:53:10 +00:00
e5a6adceac
Also set addrmode6 alignment when align==size.
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Previously, we were only setting the alignment bits on over-aligned
loads and stores.
llvm-svn: 143160
2011-10-27 22:39:16 +00:00
12a39540bb
ARM isel for vld1, opcode selection for register stride post-index pseudos.
...
llvm-svn: 143158
2011-10-27 22:25:42 +00:00
f4807a19e8
Avoid partial CPSR dependency from loop backedges. rdar://10357570
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llvm-svn: 143145
2011-10-27 21:21:05 +00:00
6ed3845530
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
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rdar://10348844
llvm-svn: 143110
2011-10-27 17:33:59 +00:00
ba7f90c7df
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
...
rdar://10348584
llvm-svn: 143108
2011-10-27 17:16:55 +00:00
d24e7e1d9b
A branch predicated on a constant can just FastEmit an unconditional branch.
...
llvm-svn: 143086
2011-10-27 00:21:16 +00:00
a486f44733
Add a TODO comment. FastISel works by parsing each basic block from the bottom
...
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
llvm-svn: 143079
2011-10-26 23:34:37 +00:00
78127d31f3
Factor a little more code into EmitCmp, which should have been done in the first
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place. No functional change intended.
llvm-svn: 143078
2011-10-26 23:25:44 +00:00
eafbf3faa9
Use EmitCmp in SelectBranch. No functional change intended.
...
llvm-svn: 143076
2011-10-26 23:17:28 +00:00
59a201950b
Factor out an EmitCmp function that can be used by both SelectCmp and
...
SelectBranch. No functional change intended.
llvm-svn: 143072
2011-10-26 22:47:55 +00:00
61fdba048f
Thumb2 ldr pc-relative encoding fixes.
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We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
llvm-svn: 143068
2011-10-26 22:22:01 +00:00
4e380354a9
ARM parse parenthesized expressions for label references.
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Partial fix for rdar://10348687.
llvm-svn: 143063
2011-10-26 21:14:08 +00:00
c47e283430
Make sure short memsets on ARM lower to stores, even when optimizing for size.
...
llvm-svn: 143055
2011-10-26 20:56:52 +00:00
25d4707c4d
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
...
llvm-svn: 143034
2011-10-26 17:28:15 +00:00
dd9137aa56
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
...
llvm-svn: 143023
2011-10-26 08:53:19 +00:00
1414bc5a14
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
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llvm-svn: 143018
2011-10-26 07:16:18 +00:00
043c9d3f7a
Revert part of r142530. The patch potentially hurts performance especially
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on Darwin platforms where -Os means optimize for size without hurting
performance.
llvm-svn: 143002
2011-10-26 01:17:44 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
30c39c8bf2
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
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llvm-svn: 142877
2011-10-24 23:40:46 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
a5e244c08d
Don't crash on variable insertelement on ARM. PR10258.
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llvm-svn: 142871
2011-10-24 23:08:52 +00:00
f33bfbbace
ARMConstantPoolMBB::print should print BB number.
...
llvm-svn: 142867
2011-10-24 23:01:03 +00:00
3ea0657d54
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
2098cb1e6f
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
...
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
4ed1afa51d
Change this overloaded use of Sched::Latency to be an overloaded
...
use of Sched::ILP instead, as Sched::Latency is going away.
llvm-svn: 142813
2011-10-24 17:55:11 +00:00
1b5e49a35a
Thumb2 LDM instructions can target PC. Make sure to encode it.
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PR11220
llvm-svn: 142801
2011-10-24 17:16:24 +00:00
0d6d098841
Move various generated tables into read-only memory, fixing up const correctness along the way.
...
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
94e6643fce
The different flavors of ARM have different valid subsets of registers. Check
...
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
llvm-svn: 142706
2011-10-22 00:29:28 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
...
llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
...
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
...
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
...
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
...
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
03a173eb71
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
...
llvm-svn: 142669
2011-10-21 18:43:28 +00:00
e6d88c9a51
Nuke an #if0 that got accidentally left in.
...
llvm-svn: 142658
2011-10-21 16:59:08 +00:00
20cb505e2f
whitespace.
...
llvm-svn: 142657
2011-10-21 16:56:40 +00:00
e3013dd62d
Remove some outdated comments.
...
llvm-svn: 142653
2011-10-21 16:14:12 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
...
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
3acac94b60
Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
...
llvm-svn: 142618
2011-10-20 21:24:38 +00:00
cf7bdf4438
Add missing operand. <rdar://problem/10313323>
...
llvm-svn: 142615
2011-10-20 20:37:11 +00:00
79ebc51c45
Tidy up. Trailing whitespace.
...
llvm-svn: 142591
2011-10-20 17:28:20 +00:00
9036c5cf2b
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
...
llvm-svn: 142583
2011-10-20 15:04:25 +00:00
8db25984a9
ARM VTBX (one register) assembly parsing and encoding.
...
llvm-svn: 142581
2011-10-20 14:48:50 +00:00
add38c12b8
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
...
llvm-svn: 142557
2011-10-20 00:07:12 +00:00
2d768fd379
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
...
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
llvm-svn: 142530
2011-10-19 14:11:07 +00:00
2977a15ab1
Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.
...
llvm-svn: 142485
2011-10-19 09:24:02 +00:00
7c1634556d
Remove some dead code.
...
llvm-svn: 142484
2011-10-19 09:04:11 +00:00
94f60018e0
Emit the MOVT instruction only if the # LPads is > 64K.
...
llvm-svn: 142460
2011-10-18 23:19:55 +00:00
64e6bfc16c
For Thumb mode, we need to use a constant pool if the value is too large to be
...
used with the CMP instruction.
llvm-svn: 142458
2011-10-18 23:11:05 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
...
llvm-svn: 142441
2011-10-18 23:02:30 +00:00
4969dcdef9
Use the integer compare when the value is small enough. Use the "move into a
...
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
llvm-svn: 142440
2011-10-18 22:52:20 +00:00
85833f71c6
Use the integer compare when the value is small enough. Use the "move into a
...
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
llvm-svn: 142437
2011-10-18 22:49:07 +00:00
973c817cde
The value we're comparing against may be too large for the ARM CMP
...
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>
llvm-svn: 142431
2011-10-18 22:11:18 +00:00
b2a703d352
The immediate may be too large for the CMP instruction. Move it into a register
...
and use that in the CMP.
<rdar://problem/10305266>
llvm-svn: 142429
2011-10-18 21:55:58 +00:00
6918617e32
Yet more ARM NEON assembly parsing for the lane index operand.
...
llvm-svn: 142416
2011-10-18 20:21:17 +00:00
e9f204c197
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142413
2011-10-18 20:14:56 +00:00
712f3670fd
ARM vmov assembly parsing for the lane index operand.
...
llvm-svn: 142412
2011-10-18 20:10:47 +00:00
88b2450adc
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
...
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
llvm-svn: 142397
2011-10-18 19:18:52 +00:00
93b0f7b319
Use isIntN and isUIntN to check for valid signed/unsigned numbers.
...
llvm-svn: 142395
2011-10-18 18:46:49 +00:00
3f07c429b5
whitespace
...
llvm-svn: 142394
2011-10-18 18:40:53 +00:00
617075fcf6
A landing pad could have more than one predecessor. In that case, we want that
...
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>
llvm-svn: 142390
2011-10-18 18:30:49 +00:00
611450071c
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142389
2011-10-18 18:27:07 +00:00
c8eff0327a
ARM vqdmulh assembly parsing for the lane index operand.
...
llvm-svn: 142386
2011-10-18 18:12:09 +00:00
e6fbca3a61
ARM vmul assembly parsing for the lane index operand.
...
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
9258b76d8d
Fix incorrect check for sign-extended constant BUILD_VECTOR.
...
<rdar://problem/10298332>
llvm-svn: 142371
2011-10-18 17:34:51 +00:00
af26d7e280
ARM vqdmlal assembly parsing for the lane index operand.
...
llvm-svn: 142365
2011-10-18 17:16:30 +00:00
dfa7fb8fe6
Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
...
llvm-svn: 142363
2011-10-18 17:09:35 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
...
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
d278d35b13
Fix a bunch of unused variable warnings when doing a release
...
build with gcc-4.6.
llvm-svn: 142350
2011-10-18 12:44:00 +00:00
49045ddb4c
Remove NaClMode
...
llvm-svn: 142338
2011-10-18 05:29:23 +00:00
0ffe593a16
Add support for dynamic stack realignment when in thumb1 mode.
...
rdar://10288916
llvm-svn: 142337
2011-10-18 05:28:00 +00:00
1c192774b6
Commit test, capitalizing store... keep it simple.
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llvm-svn: 142336
2011-10-18 04:44:36 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
...
llvm-svn: 142332
2011-10-18 03:17:34 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
...
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
...
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
b522550ce5
Add a few FIXME comments.
...
llvm-svn: 142299
2011-10-17 22:54:23 +00:00
f18eec158c
Tidy up.
...
llvm-svn: 142297
2011-10-17 22:41:42 +00:00
aa9047d3f5
Now Igor, throw the switch...give my creation life!
...
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.
It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.
Neat, huh?
<rdar://problem/10116753>
llvm-svn: 142294
2011-10-17 22:26:23 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
...
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
510fbcd440
Don't renumber the blocks here. This could cause problems later on if another
...
pass renumbers the blocks again.
llvm-svn: 142258
2011-10-17 21:32:56 +00:00
4373c21205
Pseudoinstructions should not be less constrained than the instruction they are
...
lowered to. This fixes a lot of verifier failures on the test suite.
llvm-svn: 142254
2011-10-17 21:20:13 +00:00
2ad0dee309
Tidy up organization.
...
llvm-svn: 142248
2011-10-17 21:00:11 +00:00
f7f223f69e
Add a call to EmitSjLjDispatchBlock.
...
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.
llvm-svn: 142245
2011-10-17 20:37:20 +00:00
34957911e7
Removed set, but unused variables.
...
Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142223
2011-10-17 18:48:30 +00:00
0050f59665
Fix CMake build.
...
llvm-svn: 142204
2011-10-17 17:50:39 +00:00
76c8563239
svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp
...
There is no reason to have simple IR level pass in lib/Target.
llvm-svn: 142200
2011-10-17 17:17:43 +00:00
26d2780d07
Add comment explaining that the order of processing doesn't matter here.
...
llvm-svn: 142176
2011-10-17 05:25:09 +00:00
434b3bff44
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
...
These missing flags show up as errors when running -verify-coalescing on
test-suite.
llvm-svn: 142111
2011-10-16 06:38:10 +00:00
08ca5d35bd
Fix an obvious typo found when looking at nearby code.
...
llvm-svn: 142110
2011-10-16 06:38:06 +00:00
097106b77a
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
...
llvm-svn: 142080
2011-10-15 20:03:12 +00:00
dd2b39d989
Mark tADDrSPi as having side effects again.
...
It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations. I am guessing that it got
moved across a stack pointer update.
Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.
llvm-svn: 142030
2011-10-15 00:57:13 +00:00
1809d6c0d5
Thumb1 does not support dynamic stack realignment.
...
rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
llvm-svn: 142028
2011-10-15 00:28:24 +00:00
9c1019c6c7
Mark registers as DEAD because they're really just clobbers.
...
llvm-svn: 142027
2011-10-15 00:27:44 +00:00
74d1da5a05
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
...
llvm-svn: 142022
2011-10-14 23:58:49 +00:00
9e0cd1ee17
Make sure that the register is in the register class before adding it as a machine op.
...
llvm-svn: 142021
2011-10-14 23:55:44 +00:00
6f3f9a391e
Mark the invoke call instruction as implicitly defining the callee-saved registers.
...
The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
llvm-svn: 142018
2011-10-14 23:34:37 +00:00
8b478360ef
Fix a non-firing assert. Change:
...
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
llvm-svn: 142000
2011-10-14 20:50:26 +00:00
d9444d455e
Ban rematerializable instructions with side effects.
...
TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
llvm-svn: 141929
2011-10-14 01:00:49 +00:00
a7ad9f3932
Fix undefined shift. Patch by Ahmed Charles.
...
llvm-svn: 141914
2011-10-13 23:36:06 +00:00
aa6ec39056
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
...
llvm-svn: 141903
2011-10-13 22:40:23 +00:00
44f76eafae
SETEND is not allowed in an IT block.
...
llvm-svn: 141874
2011-10-13 17:58:39 +00:00
a098a891ab
ARM addrmode5 represents the 'U' bit of the encoding backwards.
...
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
llvm-svn: 141819
2011-10-12 21:59:02 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
...
llvm-svn: 141811
2011-10-12 20:54:17 +00:00
8007320902
addrmode2 is gone from these, so no need for the reg0 operand.
...
llvm-svn: 141794
2011-10-12 18:11:24 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
d74c0e7c14
80 columns.
...
llvm-svn: 141781
2011-10-12 16:36:01 +00:00
6966411f45
Tidy up. Formatting.
...
llvm-svn: 141780
2011-10-12 16:34:37 +00:00
39c31a77b8
Fix -widen-vmovs liveness issues.
...
When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
llvm-svn: 141746
2011-10-12 00:06:23 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
265328baf6
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
12b2889989
ARM addressing mode cleanup for LDC/STC.
...
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
llvm-svn: 141704
2011-10-11 20:17:35 +00:00
a95ec99a96
ARM parse alignment specifier for NEON load/store instructions.
...
llvm-svn: 141682
2011-10-11 17:29:55 +00:00
871dff76df
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
...
llvm-svn: 141671
2011-10-11 15:59:20 +00:00
da7c0f8f7d
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
...
The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
llvm-svn: 141619
2011-10-11 00:59:06 +00:00
98703350d0
Simplify check that optional def is there and is CPSR.
...
llvm-svn: 141602
2011-10-11 00:10:41 +00:00
de7ab801cc
Add a natural stack alignment field to TargetData, and prevent InstCombine from
...
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
llvm-svn: 141599
2011-10-10 23:42:08 +00:00
c11b7c3805
Simplify operand Kind checks a bit.
...
llvm-svn: 141592
2011-10-10 23:06:42 +00:00
a7d697e4a6
Reapply r141365 now that PR11107 is fixed.
...
llvm-svn: 141591
2011-10-10 22:59:55 +00:00
2957c88c0a
Add a name to sub-operand for clarity.
...
llvm-svn: 141590
2011-10-10 22:55:05 +00:00
0a10cdc704
If the CPSR is defined by a copy, then we don't want to merge it into an IT
...
block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
llvm-svn: 141589
2011-10-10 22:52:53 +00:00
47aac51043
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
...
hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
ea662bb32f
When getting the number of bits necessary for addressing mode
...
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
llvm-svn: 141529
2011-10-10 07:24:23 +00:00
b60187ae74
Fix a regression from r138445. If we're loading from the frame/base pointer
...
the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
llvm-svn: 141523
2011-10-10 01:03:35 +00:00
e45373520d
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
...
llvm-svn: 141481
2011-10-08 08:38:45 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
6e5778f7b1
ARM prefix asmparser operand kind enums for readability.
...
llvm-svn: 141438
2011-10-07 23:24:09 +00:00
883ec97115
Take all of the invoke basic blocks and make the dispatch basic block their new
...
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
llvm-svn: 141436
2011-10-07 23:18:02 +00:00
f9f5e455d4
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
...
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
llvm-svn: 141419
2011-10-07 22:08:37 +00:00
7ecfbd90ef
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
...
do. This will be useful later on with the new SJLJ stuff.
llvm-svn: 141416
2011-10-07 21:25:38 +00:00
b8d9f51e4c
Improve ARM assembly parser diagnostic for unexpected tokens.
...
Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
llvm-svn: 141380
2011-10-07 18:27:04 +00:00
8decdc472f
Reenable tail calls for iOS 5.0 and later.
...
llvm-svn: 141370
2011-10-07 17:17:49 +00:00
bc1589945d
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
...
llvm-svn: 141368
2011-10-07 16:59:21 +00:00
318d6bae80
Peephole optimization for ABS on ARM.
...
Patch by Ana Pazos!
llvm-svn: 141365
2011-10-07 16:15:08 +00:00
8d50ea0f82
Use the correct vreg here.
...
llvm-svn: 141342
2011-10-06 23:41:14 +00:00
b3d4678877
Generate the dispatch code for a 'thumb' function. This is very similar to the
...
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
llvm-svn: 141341
2011-10-06 23:37:36 +00:00
6a5c150e9c
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
...
llvm-svn: 141339
2011-10-06 23:33:11 +00:00
5626c66a89
Generate the dispatch table for ARM mode.
...
llvm-svn: 141327
2011-10-06 22:53:00 +00:00
030b58e5c9
Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
...
llvm-svn: 141323
2011-10-06 22:18:16 +00:00
31d973cde6
Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
...
Place the immediate to OR into a register so that it works.
llvm-svn: 141319
2011-10-06 21:51:21 +00:00
362c1b01cc
* Set the low bit of the return address when we are in thumb mode.
...
* Some code cleanup.
llvm-svn: 141317
2011-10-06 21:29:56 +00:00
fb3d935649
Build system infrastructure for multiple tblgens.
...
llvm-svn: 141266
2011-10-06 01:51:51 +00:00
6134655f08
Add the MBBs before inserting the instructions. Doing it afterwards could lead
...
to an infinite loop because of the def-use chains.
Also use a frame load instead of store for the LD instruction.
llvm-svn: 141263
2011-10-06 00:53:33 +00:00
842f99a6ee
Always merge profitable shifts on A9, not just when they have a single use.
...
llvm-svn: 141248
2011-10-05 23:39:02 +00:00
87aa18378e
Remove a check from ARM shifted operand isel helper methods, which were blocking
...
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
llvm-svn: 141247
2011-10-05 23:38:50 +00:00
f793e7ed5c
Get the proper call site numbers for the landing pads. Also remove a magic
...
number (18) for the proper addressing mode.
llvm-svn: 141245
2011-10-05 23:28:57 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
2226b4be09
Add braces around something that throws me for a loop.
...
llvm-svn: 141173
2011-10-05 08:59:10 +00:00
6a7aa237cc
There is no point in setting out-parameters for a ComplexPattern function when
...
it returns false, at least as far as I could tell by reading the code.
llvm-svn: 141172
2011-10-05 08:59:05 +00:00
324be98a3c
Look at the number of entries in the jump table and jump to a 'trap' block if
...
the value exceeds that number.
llvm-svn: 141143
2011-10-05 00:39:32 +00:00
202803e39c
Checkpoint for SJLJ EH code.
...
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
llvm-svn: 141140
2011-10-05 00:02:33 +00:00
0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
...
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
69e6f90eb2
Tidy up. 80 columns.
...
llvm-svn: 141043
2011-10-03 23:03:26 +00:00
1eab54f8ba
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
...
llvm-svn: 141042
2011-10-03 22:44:15 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
374ee194f2
Check-pointing the new SjLj EH lowering.
...
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
llvm-svn: 141031
2011-10-03 21:25:38 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
5dd3425b77
Thumb2 ADD/SUB can take SP as a destination register.
...
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
a88cb23da7
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
...
to appease nightly testers. Not quite there yet.
llvm-svn: 140953
2011-10-01 19:30:36 +00:00
d072b73d78
No one should be using the method directly. Assert if they do.
...
llvm-svn: 140947
2011-10-01 12:47:34 +00:00
f977ff5fb5
Add a convenience method to tell if two things are equal.
...
llvm-svn: 140946
2011-10-01 12:44:28 +00:00
4a4772fae2
Use the ARMConstantPoolMBB class to handle the MBB values.
...
llvm-svn: 140943
2011-10-01 09:30:42 +00:00
6dbc9fe82b
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
...
llvm-svn: 140942
2011-10-01 09:19:10 +00:00
c5a86069ca
Remove dead code.
...
llvm-svn: 140941
2011-10-01 09:05:12 +00:00
9ff05f740f
Remove now dead methods and ivar.
...
llvm-svn: 140940
2011-10-01 09:04:18 +00:00
c214cb055d
Use the new ARMConstantPoolSymbol class to handle external symbols.
...
llvm-svn: 140939
2011-10-01 08:58:29 +00:00
d7fa016720
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
...
llvm-svn: 140938
2011-10-01 08:36:59 +00:00
d115c4d300
Remove now dead methods and ivar from ARMConstantPoolValue.
...
llvm-svn: 140937
2011-10-01 08:02:05 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
f117a35de0
Some more refactoring.
...
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
llvm-svn: 140935
2011-10-01 07:52:37 +00:00
6722556380
Add a Create method that accepts 'kind' and 'pcadj' arguments.
...
llvm-svn: 140934
2011-10-01 06:44:24 +00:00
396c211ae1
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
...
pool value.
It's not used right now, but will be soon.
llvm-svn: 140933
2011-10-01 06:40:33 +00:00
21360a4949
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
...
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
llvm-svn: 140924
2011-10-01 02:03:18 +00:00
237dceff90
Store sub-class lists as a bit vector.
...
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
d76f43e18c
Correct for my over-eager delete finger.
...
llvm-svn: 140892
2011-09-30 22:02:45 +00:00
e8e4dbf468
Constify 'isLSDA' and move a method out-of-line.
...
llvm-svn: 140868
2011-09-30 18:42:06 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
d2222c386c
ARM Fixup valus for movt/movw are for the whole value.
...
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
...
llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
...
llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
a0d5f268a9
Move to ISelLowering.
...
llvm-svn: 140754
2011-09-29 01:13:55 +00:00
8156376aa9
Tighten a ARM dag combine condition to avoid an identity transformation, which
...
ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
315b9573c6
Perform the lowering only if there are invokes.
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llvm-svn: 140719
2011-09-28 20:29:45 +00:00
dfe5acd34e
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
...
llvm-svn: 140718
2011-09-28 20:29:28 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
e3e36f80f5
Unbreak CMake build.
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llvm-svn: 140655
2011-09-27 23:29:59 +00:00
f9b71a2e01
Implement TII::get/setExecutionDomain() for ARM.
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llvm-svn: 140653
2011-09-27 22:57:21 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
354ff9e348
This is the start of the new SjLj EH preparation pass, which will replace the
...
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
af136f71ec
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
...
Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
1c7597693c
Use existing function.
...
llvm-svn: 140615
2011-09-27 17:55:08 +00:00
b1a9f65487
Remove extraneous commit garbage.
...
llvm-svn: 140581
2011-09-26 23:14:02 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
...
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
b1fbf9ff26
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
...
llvm-svn: 140516
2011-09-26 06:13:20 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
2056d15bd9
Also match negative offsets for addrmode3 and addrmode5.
...
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
b0b865d658
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
...
llvm-svn: 140422
2011-09-23 21:57:50 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
...
llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
...
llvm-svn: 140412
2011-09-23 21:00:32 +00:00
fbe52c0192
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
...
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
bcc3fadad9
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
...
llvm-svn: 140267
2011-09-21 17:58:45 +00:00
924123acb3
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
...
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
3f1fdf1b31
whitespace
...
llvm-svn: 140227
2011-09-21 02:17:37 +00:00
69fa8ffeef
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
...
llvm-svn: 140217
2011-09-21 00:25:23 +00:00
61a003315e
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
...
llvm-svn: 140181
2011-09-20 21:38:18 +00:00
52363bdbeb
Restore hasPostISelHook tblgen flag.
...
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
llvm-svn: 140160
2011-09-20 18:22:31 +00:00
8586e62d91
ARM isel bug fix for adds/subs operands.
...
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
53df4b6dfa
whitespace
...
llvm-svn: 140133
2011-09-20 03:06:13 +00:00
b35198021a
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
...
llvm-svn: 140125
2011-09-20 00:46:54 +00:00
716f17399e
Thumb2 assembly parsing and encoding for USAX.
...
llvm-svn: 140119
2011-09-20 00:30:45 +00:00
691389c93f
Remove incorrect comments. These are not disassmebly only patterns.
...
llvm-svn: 140116
2011-09-20 00:26:34 +00:00
62f8eee0eb
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
...
llvm-svn: 140111
2011-09-20 00:18:52 +00:00
08a478063c
Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
...
llvm-svn: 140108
2011-09-20 00:10:37 +00:00
4da03f007f
Thumb CPS definition is not disassembler only.
...
llvm-svn: 140106
2011-09-20 00:00:06 +00:00
d9846bbce2
Thumb2 range check on CPS mode immediate.
...
llvm-svn: 140105
2011-09-19 23:58:31 +00:00
163be01d69
tMOVSr is not allowed in an IT block either.
...
llvm-svn: 140104
2011-09-19 23:57:20 +00:00
61e4604dd8
CPS instructions are UNPREDICTABLE inside IT blocks.
...
llvm-svn: 140102
2011-09-19 23:47:10 +00:00
fbb4481097
Tidy up comments.
...
llvm-svn: 140099
2011-09-19 23:38:34 +00:00
fc5451832a
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
...
llvm-svn: 140095
2011-09-19 23:31:02 +00:00
15d97fd89b
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
...
llvm-svn: 140088
2011-09-19 23:13:25 +00:00
a6e6504e2a
Thumb2 assembly parsing and encoding for UASX.
...
llvm-svn: 140085
2011-09-19 23:05:22 +00:00
f902d92fc9
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
...
llvm-svn: 140079
2011-09-19 22:34:23 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
...
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
1a23fbb9fd
Tidy up a bit.
...
llvm-svn: 140050
2011-09-19 20:31:59 +00:00
8221319707
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
...
llvm-svn: 140047
2011-09-19 20:29:33 +00:00
8c021d85a6
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
...
llvm-svn: 140041
2011-09-19 20:00:02 +00:00
40700e0992
ARM asm parsing should handle pre-indexed writeback w/o immediate.
...
For example, 'ldrb r9, [sp]!' is odd, but valid.
llvm-svn: 140035
2011-09-19 18:42:21 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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llvm-svn: 140032
2011-09-19 18:07:10 +00:00
264abdecf0
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
...
llvm-svn: 140029
2011-09-19 17:56:37 +00:00
502cd9d87a
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
...
llvm-svn: 139972
2011-09-16 23:30:01 +00:00
b925e935d7
Fix bitfield decoding based on Eli's feedback.
...
llvm-svn: 139969
2011-09-16 23:04:48 +00:00
d0c435c23c
Thumb2 assembly parsing and encoding for SUB(immediate).
...
llvm-svn: 139966
2011-09-16 22:58:42 +00:00
bcfa9a6f89
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
...
llvm-svn: 139965
2011-09-16 22:42:36 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
...
llvm-svn: 139964
2011-09-16 22:29:48 +00:00
9764bced10
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
...
llvm-svn: 139958
2011-09-16 22:17:02 +00:00
9c0b86a76d
Thumb2 assembly parsing and encoding for STR.
...
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
llvm-svn: 139949
2011-09-16 21:55:56 +00:00
5c3657a0e5
Tidy up. 80 columns.
...
llvm-svn: 139944
2011-09-16 21:09:00 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
...
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
92606beeae
Thumb2 assembly parsing and encoding for STR(immediate).
...
Add aliases for STRB/STRH while there. Tests forthcoming for those.
llvm-svn: 139942
2011-09-16 21:06:12 +00:00
099c9767c3
Thumb2 assembly parsing and encoding for STMIA.
...
llvm-svn: 139938
2011-09-16 20:50:13 +00:00
8aee874bf1
Thumb2 assembly parsing and encoding for SSAX.
...
llvm-svn: 139929
2011-09-16 18:37:10 +00:00
9d9c99ff07
Thumb2 assembly parsing and encoding for SSAT.
...
llvm-svn: 139926
2011-09-16 18:32:30 +00:00
e6e7cd146a
Thumb2 assembly parsing and encoding for SRS.
...
llvm-svn: 139925
2011-09-16 18:25:22 +00:00
d73c6458de
Thumb2 assembly parsing and encoding for SMMULL.
...
llvm-svn: 139921
2011-09-16 18:05:48 +00:00
c1826a9de0
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
...
llvm-svn: 139909
2011-09-16 17:10:44 +00:00
7a0b90b187
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
...
llvm-svn: 139906
2011-09-16 16:58:03 +00:00
5e6d5cd7da
Kill some dead code.
...
llvm-svn: 139904
2011-09-16 16:45:40 +00:00
6c45b75154
Tidy up a bit.
...
llvm-svn: 139903
2011-09-16 16:39:25 +00:00
f9799d2c2d
Thumb2 assembly parsing and encoding for SMLAL.
...
llvm-svn: 139902
2011-09-16 16:38:00 +00:00
10a93ff8e0
Remove incorrect comments.
...
llvm-svn: 139877
2011-09-15 23:45:50 +00:00
a0c3b97221
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
...
llvm-svn: 139876
2011-09-15 23:38:46 +00:00
b08ce9b4c4
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
...
llvm-svn: 139870
2011-09-15 22:34:29 +00:00
10f9ce2b7d
Minor cleanup.
...
llvm-svn: 139869
2011-09-15 22:26:18 +00:00
ba912e06c2
Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
...
llvm-svn: 139865
2011-09-15 22:18:49 +00:00
10725a202b
Thumb2 assembly parsing and encoding for SASX.
...
llvm-svn: 139843
2011-09-15 21:01:23 +00:00
eaa5265285
Thumb2 assembly parsing and encoding for RSB.
...
llvm-svn: 139839
2011-09-15 20:54:14 +00:00
4cbe06e7f8
Thumb2 assembly parsing and encoding for REV16/REVSH.
...
llvm-svn: 139828
2011-09-15 19:46:13 +00:00
d1814791ad
Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
...
llvm-svn: 139820
2011-09-15 18:36:29 +00:00
ab154f0b65
Thumb2 assembly parsing and encoding for REV.
...
llvm-svn: 139813
2011-09-15 18:13:30 +00:00
d93c4ece15
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
...
llvm-svn: 139796
2011-09-15 16:16:50 +00:00
22f76390a6
Thumb2 push/pop mnemonic recognition.
...
llvm-svn: 139794
2011-09-15 15:55:04 +00:00
801e06b768
Thumb2 assembly parsing and encoding for PKH.
...
llvm-svn: 139754
2011-09-14 23:16:41 +00:00
521526845c
ARMv7a has the PKH instructions.
...
llvm-svn: 139753
2011-09-14 23:16:34 +00:00
25ca53b268
ARM tighten up the register classes for the PKH instructions.
...
llvm-svn: 139748
2011-09-14 22:52:14 +00:00
d7791b961c
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
...
llvm-svn: 139747
2011-09-14 22:46:14 +00:00
752d6fd529
Thumb2 assembly parsing and encoding for MVN.
...
llvm-svn: 139739
2011-09-14 21:24:41 +00:00
f1e384421a
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
...
llvm-svn: 139736
2011-09-14 21:06:21 +00:00
9c8b9932d6
Thumb2 assembly parsing and encoding for MUL.
...
llvm-svn: 139735
2011-09-14 21:00:40 +00:00
0ecd395095
Thumb2 assembly parsing and encoding for MSR/MRS.
...
Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
18b8b17579
Thumb2 assembly parsing for MOV in IT block.
...
Select the right 16 vs. 32 bit encoding in an IT block.
llvm-svn: 139714
2011-09-14 19:12:11 +00:00
3ac26b138b
ARM fix assembly parser handling of ranges in register lists.
...
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
llvm-svn: 139707
2011-09-14 18:08:35 +00:00
75461af000
Remove unnecessary scope resolution operator.
...
llvm-svn: 139656
2011-09-13 22:56:44 +00:00
7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
...
llvm-svn: 139639
2011-09-13 20:46:26 +00:00
e3a6a82f16
There's only 16 regs legal in a register list.
...
llvm-svn: 139637
2011-09-13 20:35:57 +00:00
e7e2aca322
Tidy up a few 80 column violations.
...
llvm-svn: 139636
2011-09-13 20:30:37 +00:00
50087ea1ec
Tidy up a bit.
...
llvm-svn: 139635
2011-09-13 20:27:44 +00:00
44ae2da4ec
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
...
llvm-svn: 139610
2011-09-13 17:59:19 +00:00
c3c60a0882
Fix encoding of Thumb2 shifted register operands with RRX shifts.
...
llvm-svn: 139606
2011-09-13 17:34:32 +00:00
12ea1b72a4
Zap some junk from the ARM instruction descriptions.
...
llvm-svn: 139575
2011-09-13 02:29:58 +00:00
3337e396c8
Tidy up a bit.
...
llvm-svn: 139559
2011-09-12 23:36:42 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
...
llvm-svn: 139542
2011-09-12 21:28:46 +00:00
4a9eb5f8dc
Fix encoding of PC-relative LDRSHW with an immediate offset.
...
llvm-svn: 139537
2011-09-12 20:36:51 +00:00
3543398bcf
There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
...
llvm-svn: 139531
2011-09-12 20:07:22 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
...
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
eb3f0fbdce
Fix an ambiguously nested if.
...
llvm-svn: 139431
2011-09-09 23:13:02 +00:00
93cd31869b
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
...
llvm-svn: 139429
2011-09-09 23:05:14 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
...
llvm-svn: 139399
2011-09-09 20:24:45 +00:00
779a2bee7b
Thumb2 assembly parsing and encoding for LDRSB.
...
llvm-svn: 139389
2011-09-09 19:42:40 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
...
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
33d39536e6
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
...
llvm-svn: 139329
2011-09-08 22:48:37 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
...
llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
...
Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
3343da5424
Thumb2 assembly parsing and encoding for LDR post-indexed.
...
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
c086f689f8
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
...
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
f174959286
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
...
llvm-svn: 139268
2011-09-08 00:11:18 +00:00
2392c53e73
Thumb2 assembly parsing and encoding for LDRBT.
...
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
e0ebc1c396
Thumb2 assembly parsing and encoding for LDR(register).
...
llvm-svn: 139264
2011-09-07 23:10:15 +00:00
c8e3656b43
Thumb2 assembly parsing and encoding for LDRB(immediate).
...
llvm-svn: 139258
2011-09-07 21:41:25 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
...
llvm-svn: 139256
2011-09-07 21:10:42 +00:00
5bfa8bab06
Thumb2 parsing and encoding for LDR(immediate).
...
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
llvm-svn: 139254
2011-09-07 20:58:57 +00:00
1c7406767e
Thumb2 parsing and encoding for LDMDB.
...
llvm-svn: 139251
2011-09-07 19:57:53 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
...
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
42b5570850
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
...
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
llvm-svn: 139243
2011-09-07 18:39:47 +00:00
a31f223af8
Thumb2 parsing and encoding for LDMIA.
...
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
llvm-svn: 139242
2011-09-07 18:05:34 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
4c493e8050
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
...
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
4ff93f3bc2
Thumb2 use 'ldm' as default mnemonic.
...
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
llvm-svn: 139234
2011-09-07 16:22:42 +00:00
39c6e1d66d
Better diagnostic location information for mnemonic suffices.
...
llvm-svn: 139232
2011-09-07 16:06:04 +00:00
5b5c953b07
ISB is HasDB, not just HasV7.
...
llvm-svn: 139202
2011-09-06 23:09:19 +00:00
83a6188f18
Thumb2 parsing and encoding for ISB.
...
llvm-svn: 139200
2011-09-06 22:53:27 +00:00
e95f46384e
Thumb2 parsing and encoding for DMB.
...
llvm-svn: 139193
2011-09-06 22:14:58 +00:00
c048b905b4
Thumb2 parsing and encoding for DBG.
...
llvm-svn: 139191
2011-09-06 22:06:40 +00:00
565e2f5752
Thumb2 parsing and encoding for CMN and CMP.
...
llvm-svn: 139188
2011-09-06 21:44:58 +00:00
fc4b343dda
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
...
llvm-svn: 139179
2011-09-06 20:53:37 +00:00
803898f119
Thumb2 parsing and encoding for CLREX.
...
llvm-svn: 139172
2011-09-06 20:27:04 +00:00
f2641e1bc1
Add codegen support for vector select (in the IR this means a select
...
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
0b758ed6ba
Fix fall outs from my recent change on how carry bit is modeled during isel.
...
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
llvm-svn: 139157
2011-09-06 18:52:20 +00:00
f471ac3c72
ARM .code directive should always go to the streamer.
...
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
llvm-svn: 139155
2011-09-06 18:46:23 +00:00
50ef7611aa
Atomic pseudos don't use (as in read) CPSR. They clobber it.
...
llvm-svn: 139148
2011-09-06 17:40:35 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
...
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
f1a5f57d2f
Fix typo in comment.
...
llvm-svn: 139122
2011-09-05 18:35:03 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
05dec8b122
Tidy up. Formatting.
...
llvm-svn: 139024
2011-09-02 18:46:15 +00:00
0a57375a28
Tidy up. 80 columns.
...
llvm-svn: 139022
2011-09-02 18:43:25 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
...
llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
...
llvm-svn: 138980
2011-09-01 23:23:50 +00:00
6397051ece
Don't drop alignment info on local common symbols.
...
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
d7776ed030
Null-initialize to shut up -Wuninitialized warnings.
...
llvm-svn: 138974
2011-09-01 22:27:41 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
...
llvm-svn: 138948
2011-09-01 18:02:14 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
17847ae757
Fixup for functions that return a bool.
...
llvm-svn: 138918
2011-08-31 23:49:05 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
...
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
...
llvm-svn: 138910
2011-08-31 22:00:41 +00:00
99bc84662f
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
...
llvm-svn: 138898
2011-08-31 21:17:31 +00:00
a455a0b1e7
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
939cd21248
When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
...
<rdar://problem/10046188>
llvm-svn: 138885
2011-08-31 20:00:11 +00:00
cfa9421e16
Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.
...
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.
llvm-svn: 138879
2011-08-31 18:39:39 +00:00
5c160fd243
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
c61fc8f301
tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).
...
llvm-svn: 138873
2011-08-31 18:29:05 +00:00
af8c3cc710
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
1ccecbb9d3
64-bit atomic cmpxchg for ARM.
...
llvm-svn: 138868
2011-08-31 17:52:22 +00:00
6d606fbe14
Tweak Thumb1 ADD encoding selection a bit.
...
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
llvm-svn: 138862
2011-08-31 17:07:33 +00:00
cd893390f5
Put VMOVS widening under a command line option, off by default.
...
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
llvm-svn: 138861
2011-08-31 17:00:02 +00:00
2c7bb52f56
Some minor cleanups for r138845.
...
llvm-svn: 138846
2011-08-31 00:41:05 +00:00
c3f9c4a852
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
...
llvm-svn: 138845
2011-08-31 00:31:29 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
fdf3cd7f2b
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
...
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
d16fb43b1f
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
...
llvm-svn: 138835
2011-08-30 22:10:03 +00:00
543c89fb15
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
...
llvm-svn: 138834
2011-08-30 22:03:20 +00:00
1732c2ebf6
Clean up whitespace.
...
llvm-svn: 138833
2011-08-30 21:58:18 +00:00
e6fba77971
Follow up to r138791.
...
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
llvm-svn: 138810
2011-08-30 19:09:48 +00:00
e891654a58
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
...
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
llvm-svn: 138791
2011-08-30 01:34:54 +00:00
6e59d5c916
Revert 138781. It's not playing nicely with the immediate forms for ADC.
...
llvm-svn: 138782
2011-08-29 23:24:15 +00:00
19a75f075d
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
...
llvm-svn: 138781
2011-08-29 23:20:54 +00:00
3e0aa03fe9
Add missing encoding information for some of the GPR<->FP register moves.
...
llvm-svn: 138780
2011-08-29 23:15:25 +00:00
ed16ec4248
Thumb2 parsing and encoding for IT blocks.
...
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
243274c789
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
...
llvm-svn: 138766
2011-08-29 21:14:19 +00:00
32ac76616e
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
...
llvm-svn: 138760
2011-08-29 20:42:00 +00:00
4d5c8f894d
addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.
...
llvm-svn: 138758
2011-08-29 20:16:50 +00:00
967674d26c
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
7dfa791f4f
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
...
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
6314343333
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
...
llvm-svn: 138746
2011-08-29 17:59:41 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
61a1ff543c
Silence GCC warnings and make an array const.
...
llvm-svn: 138706
2011-08-27 17:36:14 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
b9d4e37776
ARM assembly parsing tweak for pldw.
...
llvm-svn: 138669
2011-08-26 22:21:51 +00:00
240d20af79
Spelling fail.
...
llvm-svn: 138667
2011-08-26 21:47:57 +00:00
3d1eac85c3
Thumb2 assembler parsing and encoding of IT instruction.
...
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
llvm-svn: 138665
2011-08-26 21:43:41 +00:00
fd60f60ed1
Fix ARM codegen breakage caused by r138653.
...
llvm-svn: 138657
2011-08-26 21:12:37 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
5658b49f64
Update for feedback from Jim.
...
llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
...
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
...
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
64bfca1b60
Remove stray fullstop.
...
llvm-svn: 138589
2011-08-25 21:46:20 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
...
rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
f7ecc16c96
whitespace
...
llvm-svn: 138566
2011-08-25 17:40:54 +00:00
1c171b121a
Explicitly disallow predication in Thumb1 assembly.
...
llvm-svn: 138562
2011-08-25 17:23:55 +00:00
9dad430486
Hide -global-merge option.
...
llvm-svn: 138540
2011-08-25 01:22:49 +00:00
f066b2fe99
Add a command line option to disable global merge pass.
...
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
3ca20e64ac
Remove a out-of-place comment.
...
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
21a60b6f90
ARM asm backend initialize isThumbMode based on target triple.
...
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
...
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
af2f827a2c
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
...
rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
...
rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
a281f2d07d
Thumb add SP assembly syntax fix.
...
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
...
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
...
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
...
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
...
from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
...
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
...
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
d80d169a04
Thumb parsing and encoding for STM.
...
llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
...
llvm-svn: 138344
2011-08-23 18:13:04 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
...
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
e364ad540a
Clean up Thumb load/store multiple definitions.
...
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
llvm-svn: 138338
2011-08-23 17:41:15 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
...
llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
...
llvm-svn: 138308
2011-08-22 23:47:13 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
...
llvm-svn: 138306
2011-08-22 23:44:04 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
...
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
...
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
bfeb4f78af
Revert r138278 now that r138289 has fixed the root issue.
...
llvm-svn: 138299
2011-08-22 23:25:48 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
...
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
...
llvm-svn: 138295
2011-08-22 23:17:34 +00:00
2844a81079
Match operand names to provide correct decoding for Thumb2 SMULL.
...
llvm-svn: 138294
2011-08-22 23:16:48 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
...
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
...
llvm-svn: 138287
2011-08-22 23:01:07 +00:00
ca2ffad8b1
Temporarilly mark tMUL as not commutable.
...
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
llvm-svn: 138278
2011-08-22 22:00:18 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
...
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
5c932b24be
Tighten up ARM reglist validation a bit.
...
llvm-svn: 138258
2011-08-22 18:50:36 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
6caa557ae6
Clean up predicates on ARM target instruction aliases.
...
llvm-svn: 138249
2011-08-22 18:04:24 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
...
llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
...
llvm-svn: 138174
2011-08-20 00:40:14 +00:00
59015c8b17
Add <imp-def> operands to QQ and QQQQ stack loads.
...
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
llvm-svn: 138164
2011-08-20 00:17:45 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
...
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
...
The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
...
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
8022015a16
Fix NEG alias
...
llvm-svn: 138125
2011-08-19 22:30:58 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
...
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
066e9ec1e4
Update tests.
...
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
...
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
...
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
dbb60f960a
Tidy up. Tab character.
...
llvm-svn: 138072
2011-08-19 20:30:19 +00:00
9c92049069
Tab characters.
...
llvm-svn: 138066
2011-08-19 19:41:46 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
...
llvm-svn: 138063
2011-08-19 19:29:25 +00:00
7c4739da3c
Thumb assembly parsing and encoding for LDRSB and LDRSH.
...
llvm-svn: 138061
2011-08-19 19:17:58 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
...
llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
...
llvm-svn: 138059
2011-08-19 18:49:59 +00:00
181d2f92b5
Thumb assembly parsing and encoding for LDR(literal).
...
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
...
llvm-svn: 138050
2011-08-19 18:13:48 +00:00
7473329725
Use helper function to check for low registers.
...
llvm-svn: 138048
2011-08-19 17:57:22 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
...
llvm-svn: 138047
2011-08-19 17:55:24 +00:00
e93807049b
Add explanatory comment.
...
llvm-svn: 138042
2011-08-19 16:52:32 +00:00
4938edb02c
Make a bunch of symbols private.
...
llvm-svn: 138025
2011-08-19 01:42:18 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
5d2db89ba6
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
...
llvm-svn: 137997
2011-08-18 22:15:25 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
...
Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
...
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
4f240a1fd5
Thumb assembly parsing and encoding for CMP.
...
llvm-svn: 137963
2011-08-18 18:08:29 +00:00
8a6bed863a
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
...
llvm-svn: 137956
2011-08-18 17:51:36 +00:00
f00b9ccd22
ARM Thumb blx instruction fixup has same data range as bl.
...
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
llvm-svn: 137947
2011-08-18 16:57:50 +00:00
8fa3f6a2b4
80 columns.
...
llvm-svn: 137946
2011-08-18 16:50:45 +00:00
6ddb568ab8
Add missing 'break'.
...
llvm-svn: 137941
2011-08-18 16:08:39 +00:00
50aafeaa2c
Remove extraneous newline from operand print method. PR10569.
...
llvm-svn: 137900
2011-08-17 23:23:07 +00:00
23b729eeba
Clean up patterns for Thumb1 system instructions.
...
llvm-svn: 137897
2011-08-17 23:08:57 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
...
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
...
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
d14b70d00b
Tidy up. 80 columns.
...
llvm-svn: 137881
2011-08-17 21:58:18 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
...
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
854fe433d4
Fix predicate for imm1_32
...
llvm-svn: 137865
2011-08-17 21:01:11 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
...
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
3b5a69cc45
80 columns.
...
llvm-svn: 137857
2011-08-17 19:55:51 +00:00
8637523886
Tidy up.
...
llvm-svn: 137856
2011-08-17 19:53:53 +00:00
187e1e46f9
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
...
llvm-svn: 137838
2011-08-17 18:14:48 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
...
Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
...
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
91a8f9be20
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
...
llvm-svn: 137787
2011-08-16 23:45:44 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
...
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
64610e52e7
Add missing exit for 'case'.
...
llvm-svn: 137774
2011-08-16 21:42:31 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
...
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
7283da9bb2
Move some logic into a helper function and expand the commentary.
...
llvm-svn: 137756
2011-08-16 21:12:37 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
...
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
...
Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
...
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
120a96a721
MCTargetAsmParser target match predicate support.
...
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
llvm-svn: 137675
2011-08-15 23:03:29 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
de25f9aa8f
Remove dead classes.
...
llvm-svn: 137643
2011-08-15 20:11:11 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
30694dcdeb
Update comment to reflect MC target machine refactor.
...
llvm-svn: 137615
2011-08-15 16:52:24 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
...
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
2325474368
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
...
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
llvm-svn: 137525
2011-08-12 22:20:41 +00:00
f402f694e2
ARM expansion of pre-indexed store pseudos should maintain memoperands.
...
Partial fix for rdar://9945172.
llvm-svn: 137513
2011-08-12 21:02:34 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
60138eaf93
Fix decoding of ARM-mode STRH.
...
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
1043e173bc
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
...
llvm-svn: 137494
2011-08-12 19:41:29 +00:00
3987a61c16
Fix decoding of pre-indexed stores.
...
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
...
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
a41634e307
Silence a bunch (but not all) "variable written but not read" warnings
...
when building with assertions disabled.
llvm-svn: 137460
2011-08-12 14:54:45 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
...
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
37f7e6b2f4
Remove no-longer-true comments. These are for the assembler, also.
...
llvm-svn: 137375
2011-08-11 22:30:30 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
eca346ee1a
Make the USAT16 operand decoder auto-generate-able.
...
llvm-svn: 137371
2011-08-11 22:10:11 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
...
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
...
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
...
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
12d13efa21
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
...
llvm-svn: 137364
2011-08-11 21:52:38 +00:00
f05e744857
Making SEL decodings auto-generate-able.
...
llvm-svn: 137363
2011-08-11 21:50:56 +00:00
88981ff168
Tidy up comment.
...
llvm-svn: 137359
2011-08-11 21:41:59 +00:00
b685c9f011
Fix decoding support for STREXD and LDREXD.
...
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
2ea19d1438
Tidy up. Remove unused template parameter.
...
llvm-svn: 137345
2011-08-11 20:41:13 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
1b0f79573e
Tidy up.
...
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
2a50260f2f
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
e33c95d39b
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
d5d6359785
ARM LDRT assembly parsing and encoding.
...
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
d3f7bcd43c
Tidy up. 80 columns.
...
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
cd4dd255c0
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
1d9d5e93d1
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
f7164b2cfd
Fix typo. Not quite sure how that slipped in there.
...
llvm-svn: 137245
2011-08-10 20:49:18 +00:00
5b96b80644
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
1531e5cd2b
Tabs --> spaces.
...
llvm-svn: 137225
2011-08-10 17:38:05 +00:00
5d69f63bbb
Cleanups based on Nick Lewycky's feedback.
...
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
732f82c463
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
...
llvm-svn: 137223
2011-08-10 17:21:20 +00:00
36a3abc671
Add support for the R and Q constraints.
...
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
6a14dc01ff
Promote VMOVS to VMOVD when possible.
...
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
...
vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
llvm-svn: 137182
2011-08-09 23:41:44 +00:00
92b942b1b5
Tighten operand checking of register-shifted-register operands.
...
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
e008931bf6
Tighten operand checking on memory barrier instructions.
...
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
3d2e0e9db6
Tighten operand checking on CPS instructions.
...
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
042619f97d
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
...
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
406dc1755f
ARM Disassembler: sign extend branch immediates.
...
Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
d151b09921
Silence an false-positive warning.
...
llvm-svn: 137154
2011-08-09 21:38:14 +00:00
d770f6c110
Don't generate the old-style disassembler in CMake builds either.
...
llvm-svn: 137153
2011-08-09 21:36:11 +00:00
de2c381331
The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
...
llvm-svn: 137151
2011-08-09 21:34:19 +00:00
982aa05017
Don't continue generating the old-style decoder file.
...
llvm-svn: 137150
2011-08-09 21:30:29 +00:00
5e80abbb5d
ARM fix typo in pre-indexed store lowering.
...
rdar://9915869
llvm-svn: 137148
2011-08-09 21:22:41 +00:00
c7afd84322
Attempt to fix CMake build.
...
llvm-svn: 137147
2011-08-09 21:09:59 +00:00
7a2401dbf0
Tighten Thumb1 branch predicate decoding.
...
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
faff512536
Emitting ARM build attributes and values as ULEB, rather than char.
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llvm-svn: 137115
2011-08-09 09:50:10 +00:00
cab35c0836
ARM parsing and encoding for LDRBT instruction.
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Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
03ac20fc66
Thumb1 BL instructions encoding 22 bits of displacement, not 21.
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llvm-svn: 137073
2011-08-08 23:25:22 +00:00
c04a66b48e
Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
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They improve the verbose assembly.
llvm-svn: 137069
2011-08-08 21:45:32 +00:00
95466ce63b
ARM load/store label parsing.
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Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.
llvm-svn: 137064
2011-08-08 20:59:31 +00:00
c40303885b
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
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llvm-svn: 137062
2011-08-08 20:42:17 +00:00
a27da98921
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
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llvm-svn: 137061
2011-08-08 19:49:37 +00:00
c22d50e5c3
Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
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- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
llvm-svn: 137059
2011-08-08 18:56:44 +00:00
3d0b3a3a50
ARM load instruction shifted register index operands.
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Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
c320c85261
ARM indexed load assembly parsing and encoding.
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More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
llvm-svn: 136982
2011-08-05 21:28:30 +00:00
f0c95cadc7
ARM refactor indexed store instructions.
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Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.
llvm-svn: 136978
2011-08-05 20:35:44 +00:00
a70fbfd577
ARM simplify the postidx_reg operand encoding.
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The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
llvm-svn: 136969
2011-08-05 16:11:38 +00:00
bafce840ff
ARM use a dedicated printer for postidx_reg operands.
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llvm-svn: 136968
2011-08-05 15:48:21 +00:00
8de11bab76
Add missing register constraint for some VLD3/VLD4 pseudo instructions.
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<rdar://problem/9878189>
llvm-svn: 136962
2011-08-05 07:24:09 +00:00
08d4bb0f12
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
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llvm-svn: 136942
2011-08-04 23:18:05 +00:00
cd17c12078
ARM assembly parsing and encoding for LDR instructions.
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Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.
llvm-svn: 136940
2011-08-04 23:01:30 +00:00
ce5190321e
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
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llvm-svn: 136896
2011-08-04 18:24:14 +00:00
d359571120
ARM refactoring assembly parsing of memory address operands.
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Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
7bc3b11a56
Fix broken encoding of tCBNZ.
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llvm-svn: 136837
2011-08-03 23:21:48 +00:00
30a49e93e3
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
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I think this completes the basic CodeGen for atomicrmw and cmpxchg.
llvm-svn: 136813
2011-08-03 21:06:02 +00:00
5c863aeefd
ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
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llvm-svn: 136737
2011-08-02 22:44:16 +00:00
713406f88d
Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
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llvm-svn: 136707
2011-08-02 18:30:00 +00:00
c8c63914c5
Tidy up. 80 columns.
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llvm-svn: 136705
2011-08-02 18:16:36 +00:00
9ec152b6bf
ARM: rename addrmode7 to addr_offset_none.
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Use a more descriptive name so the code is more self-documenting.
llvm-svn: 136704
2011-08-02 18:07:32 +00:00
9f620a6883
Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
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llvm-svn: 136656
2011-08-01 22:02:20 +00:00
0f731b3232
Fix comments.
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llvm-svn: 136655
2011-08-01 21:55:12 +00:00
d41f3a161f
Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.
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llvm-svn: 136621
2011-08-01 16:29:27 +00:00
Jim Grosbach