69cc2cbbff
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
...
llvm-svn: 60487
2008-12-03 18:15:48 +00:00
cda011b5ad
Fix bug 3140.
...
Print a single parameter .file directive if we have an ELF target.
llvm-svn: 60480
2008-12-03 11:01:37 +00:00
ae3ba45eb2
Add a sanity-check to tablegen to catch the case where isSimpleLoad
...
is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
llvm-svn: 60459
2008-12-03 02:30:17 +00:00
3d960941b1
There are no longer any places that require a
...
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
llvm-svn: 60349
2008-12-01 11:41:29 +00:00
6ed40141f7
Change the interface to the type legalization method
...
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
llvm-svn: 60348
2008-12-01 11:39:25 +00:00
dc2dac181a
If the type legalizer actually legalized anything
...
(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types. I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.
llvm-svn: 59960
2008-11-24 14:53:14 +00:00
75339657bd
Fix comments.
...
llvm-svn: 59958
2008-11-24 11:44:00 +00:00
977e7be9d4
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
...
llvm-svn: 59953
2008-11-24 07:34:46 +00:00
8d6e2e13d5
Rename SetCCResultContents to BooleanContents. In
...
practice these booleans are mostly produced by SetCC,
however the concept is more general.
llvm-svn: 59911
2008-11-23 15:47:28 +00:00
bff4b37af5
Make a convenient helper for printing offsets.
...
llvm-svn: 59872
2008-11-22 16:15:34 +00:00
60cb69e665
Experimental post-pass scheduling support. Post-pass scheduling
...
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
llvm-svn: 59676
2008-11-19 23:18:57 +00:00
0b2732598c
Add more const qualifiers. This fixes build breakage from r59540.
...
llvm-svn: 59542
2008-11-18 19:49:32 +00:00
aae3a4f864
Move some former testcases (low-probability codegen
...
optimizations) into this wishlist.
llvm-svn: 59455
2008-11-17 18:56:34 +00:00
ba4eb2a9db
Adds extern "C" ints to the .cpp files that use RegisterTarget, as
...
well as 2 files that use "Registrator"s. These are to be used by the
MSVC builds, as the Win32 linker does not include libs that are
otherwise unreferenced, even if global constructors in the lib have
side-effects.
Patch by Scott Graham!
llvm-svn: 59378
2008-11-15 21:36:30 +00:00
9833d8c369
Temporary revert my last commit: it seems it's triggering some subtle bug in backend
...
and breaks llvm-gcc
llvm-svn: 58926
2008-11-08 23:05:05 +00:00
09f51d1fd4
Factor out offset printing code into generic AsmPrinter.
...
FIXME: it seems, that most of targets don't support
offsets wrt CPI/GlobalAddress', was it intentional?
llvm-svn: 58917
2008-11-08 17:21:38 +00:00
b31a717527
Rename startFunctionStub to startGVStub since it's also used for GV non-lazy ptr.
...
llvm-svn: 58897
2008-11-08 08:02:53 +00:00
160be0ffda
Make FP tests requiring two compares work on PPC (PR 642).
...
This is Chris' patch from the PR, modified to realize that
SETUGT/SETULT occur legitimately with integers, plus
two fixes in LegalizeDAG to pass a valid result type into
LegalizeSetCC. The argument of TLI.getSetCCResultType is
ignored on PPC, but I think I'm following usage elsewhere.
llvm-svn: 58871
2008-11-07 22:54:33 +00:00
cb0df597e0
Flush the raw_ostream after emitting the assembly for a function.
...
This is a temporary fix for the -print-emitted-asm option, where
errs() is used as the stream, in the case where other code is
using stderr without using errs()' buffer. Hopefully soon we'll
fix errs() to be non-buffered instead. Patch by Preston Gurd.
llvm-svn: 58859
2008-11-07 19:49:17 +00:00
7a638a8c7e
Reintroduce a comment that was removed with the AddToISelQueue
...
changes.
llvm-svn: 58760
2008-11-05 17:16:24 +00:00
f14b77ebf1
Eliminate the ISel priority queue, which used the topological order for a
...
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
llvm-svn: 58748
2008-11-05 04:14:16 +00:00
1310574b0f
Shift amounts should have type getShiftAmountTy
...
(i32 for PPC, not i8). Correct this, and some
formatting while there.
llvm-svn: 58451
2008-10-30 19:28:32 +00:00
98aa9d3e49
Add a RM pseudoreg for the rounding mode, which
...
allows ppcf128->int conversion to work with
DeadInstructionElimination. This is now turned
off but RM is harmless. It does not do a complete
job of modeling the rounding mode.
Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now. Eventually it should go back in and the
other problems fixed where they're broken.
llvm-svn: 58391
2008-10-29 18:26:45 +00:00
4068a7f31e
Fix darwin ppc llvm-gcc build breakage: intercept
...
ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG. This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes. Probably PPC should
simply custom lower the original conversion.
llvm-svn: 58329
2008-10-28 15:00:32 +00:00
ce2a938186
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
...
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
llvm-svn: 58278
2008-10-27 21:56:29 +00:00
71f361e758
Mark MFCR as reading all condition code registers.
...
Prevents some more overzealous deletions (mostly
in AltiVec code).
llvm-svn: 58121
2008-10-24 22:08:01 +00:00
3863f8e725
Rewrite logic to figure out whether LR needs to
...
be saved/restored in the prolog/epilog. We need
to do this iff something in the function stores
into it.
llvm-svn: 58116
2008-10-24 21:24:23 +00:00
e395d78657
Mark defs and uses of CTR and LR correctly.
...
Prevents DeadMachineInstructionElim from thinking
things like MTCTR are dead (fixes massive
testsuite breakage at -O0).
llvm-svn: 58043
2008-10-23 20:41:28 +00:00
f3c03b02dc
CMake: Turned some libraries into partially linked objects. Corrected
...
names of LLVMCore and ARMCodeGen.
llvm-svn: 57943
2008-10-22 02:51:53 +00:00
c14e5227f0
Disable constant-offset folding for PowerPC, as the PowerPC target
...
isn't yet prepared for it.
llvm-svn: 57886
2008-10-21 03:41:46 +00:00
e33afda4fa
Trim #includes.
...
llvm-svn: 57649
2008-10-16 20:18:31 +00:00
dc84511146
Fix warnings about mb/me being potentially used
...
uninitialized in these functions with gcc-4.3.
llvm-svn: 57635
2008-10-16 13:02:33 +00:00
33332bce17
Const-ify several TargetInstrInfo methods.
...
llvm-svn: 57622
2008-10-16 01:49:15 +00:00
07d53b1d33
Rename LoadX to LoadExt.
...
llvm-svn: 57526
2008-10-14 21:26:46 +00:00
9c4b7d5c4f
Fix command-line option printing to print two spaces where needed,
...
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
llvm-svn: 57521
2008-10-14 20:25:08 +00:00
2753955fc0
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
...
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
26ff6f9c54
Add <cstdio> include where needed by gcc-4.4.
...
Patch by Samuel Tardieu.
llvm-svn: 57291
2008-10-08 07:23:46 +00:00
d2aded08ac
Fix weird think-o and unbreak build on all gcc-3.4.x-based platforms (e.g. mingw)
...
llvm-svn: 57106
2008-10-05 08:53:29 +00:00
2c836cf187
Avoid creating two TargetLowering objects for each target.
...
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
llvm-svn: 57016
2008-10-03 16:55:19 +00:00
0d1e9a8e04
Switch the MachineOperand accessors back to the short names like
...
isReg, etc., from isRegister, etc.
llvm-svn: 57006
2008-10-03 15:45:36 +00:00
1b76f2c40b
Remove OptimizeForSize global. Use function attribute optsize.
...
llvm-svn: 56937
2008-10-01 23:18:38 +00:00
08d91178e9
Rename isWeakForLinker to mayBeOverridden. Use it
...
instead of hasWeakLinkage in a bunch of optimization
passes.
llvm-svn: 56782
2008-09-29 11:25:42 +00:00
c966a737c5
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
...
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
llvm-svn: 56703
2008-09-26 22:10:44 +00:00
6e0548336a
Rename ConstantSDNode's getSignExtended to getSExtValue, for
...
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
llvm-svn: 56700
2008-09-26 21:54:37 +00:00
d77cbe8947
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
...
llvm-svn: 56683
2008-09-26 19:48:35 +00:00
0e32a2c935
Add "inreg" field to CallSDNode (doesn't increase
...
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
llvm-svn: 56677
2008-09-26 19:31:26 +00:00
cdc95498f5
CMake: Builds all targets.
...
llvm-svn: 56641
2008-09-26 04:40:32 +00:00
374d7f2b16
If we have a function with an unreachable statement such that the ending debug
...
information is in an unreachable block, then it's possible that the high/low pc
values won't be set for the dwarf information. E.g., this function:
void abort(void) __attribute__((__noreturn__));
void dead_beef(void) __attribute__ ((noreturn));
int *b;
void dead_beef(void) {
*b=0xdeadbeef;
abort();
}
has a call to "@llvm.dbg.region.end" only in the unreachable block:
define void @dead_beef() noreturn nounwind {
entry:
call void @llvm.dbg.func.start(...)
call void @llvm.dbg.stoppoint(...)
...
call void @abort( ) noreturn nounwind
unreachable
return: ; No predecessors!
call void @llvm.dbg.stoppoint(...)
call void @llvm.dbg.region.end(...)
ret void
}
The dwarf information emitted is something like:
0x00000084: TAG_subprogram [5]
AT_name( "dead_beef" )
AT_external( 0x01 )
AT_prototyped( 0x01 )
AT_decl_file( 0x01 )
AT_decl_line( 0x08 )
Note that this is *not* the best fix for this problem, but a band-aid for an
gaping wound. This code needs to be changed when we revamp our debugging
information.
llvm-svn: 56628
2008-09-26 00:28:12 +00:00
87001fd6fd
Reapply 56585:56589 with proper fix for some gcc versions
...
llvm-svn: 56621
2008-09-25 21:00:33 +00:00
84301390ae
Temporarily backing out 56585:56589 to unbreak the build.
...
llvm-svn: 56607
2008-09-25 07:38:08 +00:00
3097c10347
Minor cleanup
...
llvm-svn: 56588
2008-09-24 22:22:54 +00:00
237f087eb9
Get rid of virtual inheritance for PPC TAI
...
llvm-svn: 56586
2008-09-24 22:22:03 +00:00
8e7b93938d
Get rid of ReadOnlySection duplicate
...
llvm-svn: 56582
2008-09-24 22:20:27 +00:00
5906234c1d
Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
...
llvm-svn: 56580
2008-09-24 22:18:54 +00:00
f8dc8aac3c
Get rid of duplicate char*/Section* TextSection
...
llvm-svn: 56574
2008-09-24 22:15:21 +00:00
076e905b94
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
...
llvm-svn: 56573
2008-09-24 22:14:23 +00:00
69ff51baa0
Drop obsolete hook and change all usage to new interface
...
llvm-svn: 56572
2008-09-24 22:13:07 +00:00
e0add20c1b
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
...
llvm-svn: 56526
2008-09-24 00:05:32 +00:00
ba3fa6c6e1
s/ParameterAttributes/Attributes/g
...
llvm-svn: 56513
2008-09-23 23:03:40 +00:00
ed1cf1a8f1
Fix these enums' starting values to reflect the way that
...
instruction opcodes are now numbered. No functionality change.
llvm-svn: 56497
2008-09-23 18:42:32 +00:00
7a74e71489
Make log, log2, log10, exp, exp2 use Expand by
...
default.
llvm-svn: 56471
2008-09-22 21:57:32 +00:00
95e1af217f
Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
...
function with appropriate parameters. This allows us to support blocks on PPC.
llvm-svn: 56267
2008-09-17 00:30:57 +00:00
24c79f28b1
Reverting r56249. On further investigation, this functionality isn't needed.
...
Apologies for the thrashing.
llvm-svn: 56251
2008-09-16 21:48:12 +00:00
8bc392fb1d
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
...
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
llvm-svn: 56249
2008-09-16 21:12:30 +00:00
38453eebdc
Remove isImm(), isReg(), and friends, in favor of
...
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
llvm-svn: 56189
2008-09-13 17:58:21 +00:00
d3fe174c53
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
...
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
llvm-svn: 56183
2008-09-13 01:54:27 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
e5ca04e70d
Succumb utterly to compatibility and implement
...
__sync_fetch_and_nand as ANDC, even though that's
not what nand means.
llvm-svn: 56087
2008-09-11 02:15:03 +00:00
f080225490
Fix logic for not emitting no-dead-strip for some
...
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
llvm-svn: 55973
2008-09-09 01:21:22 +00:00
d41c7160d0
Fix constant pool loads, and remove broken versions of addConstantPoolReference.
...
llvm-svn: 55868
2008-09-06 01:11:01 +00:00
a79db30d28
Tidy up several unbeseeming casts from pointer to intptr_t.
...
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
634412fe35
Clean up uses of TargetLowering::getTargetMachine.
...
llvm-svn: 55769
2008-09-04 15:39:15 +00:00
da2d80688b
Add intrinsics for log, log2, log10, exp, exp2.
...
No functional change (and no FE change to generate them).
llvm-svn: 55753
2008-09-04 00:47:13 +00:00
bc69829b22
Fix some bugs in the code sequences for atomics.
...
llvm-svn: 55643
2008-09-02 20:30:23 +00:00
34f3a962b0
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
...
llvm-svn: 55623
2008-09-02 06:51:36 +00:00
81d6a38434
fix a bunch of 80-col violations
...
llvm-svn: 55588
2008-08-31 15:37:04 +00:00
62cf24343c
Expand for ROTR with MVT::i64.
...
Dale, Could you please review this?
llvm-svn: 55581
2008-08-31 02:53:19 +00:00
340d264f52
Add ppc partial-word ATOMIC_CMP_SWAP.
...
llvm-svn: 55554
2008-08-30 00:08:53 +00:00
f0a88d6b2a
Add partial word version of ATOMIC_SWAP.
...
llvm-svn: 55546
2008-08-29 18:29:46 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
...
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
1e137300bd
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
...
llvm-svn: 55499
2008-08-28 21:04:05 +00:00
a32affb9ba
Implement partial-word binary atomics on ppc.
...
llvm-svn: 55478
2008-08-28 17:53:09 +00:00
abfdf928d8
disallow direct access to SDValue::ResNo, provide a getter instead
...
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
27fb3dcbc7
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
...
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
d4eb0521e4
Implement 32 & 64 bit versions of PPC atomic
...
binary primitives.
llvm-svn: 55343
2008-08-25 22:34:37 +00:00
765065c982
Remove PPC-specific lowering for atomics; the
...
generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
llvm-svn: 55336
2008-08-25 21:09:52 +00:00
166d6cb1fa
It's important for the cmp-and-swap to balance
...
loads and stores but it's even more important for
it to store the right value.:(
llvm-svn: 55319
2008-08-25 18:53:26 +00:00
eb0cee91f6
Move the point at which FastISel taps into the SelectionDAGISel
...
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
llvm-svn: 55219
2008-08-23 02:25:05 +00:00
ed86f689cb
Implement __sync_synchronize on ppc32. Patch by Gary Benson.
...
llvm-svn: 55186
2008-08-22 17:20:54 +00:00
dec51704ed
Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap
...
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
llvm-svn: 55163
2008-08-22 03:49:10 +00:00
d3582c9bda
Simplify SelectRoot's interface, and factor out some common code
...
from all targets.
llvm-svn: 55124
2008-08-21 16:36:34 +00:00
9371964f47
Use raw_ostream throughout the AsmPrinter.
...
llvm-svn: 55092
2008-08-21 00:14:44 +00:00
19fed1eb3d
Use correct name for PPC codegen library
...
llvm-svn: 54888
2008-08-17 13:54:44 +00:00
28dc9d0ad9
Factor out asmprinter out of ppc
...
llvm-svn: 54887
2008-08-17 13:54:28 +00:00
16d5d3fba7
PPC/Linux normally uses named section for bss
...
llvm-svn: 54847
2008-08-16 12:59:02 +00:00
c3f3aea666
Use proper strings section name for PPC
...
llvm-svn: 54846
2008-08-16 12:58:46 +00:00
4f6bf04616
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
...
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
f69d13b60a
Implement ISD::TRAP support on PPC
...
llvm-svn: 54644
2008-08-11 17:36:31 +00:00
ed47329174
Handle visibility printing with all generality. Remove bunch of duplicate code.
...
llvm-svn: 54540
2008-08-08 18:25:07 +00:00
f1f8aa3e50
Use chars, where possible
...
llvm-svn: 54539
2008-08-08 18:24:10 +00:00
c9ad17c3da
Convert PPC/Linux to new section printing stuff
...
llvm-svn: 54538
2008-08-08 18:23:49 +00:00
5b5d8bcd88
Switch PPC/Darwin to new section handling stuff
...
llvm-svn: 54537
2008-08-08 18:23:25 +00:00
7c20ede085
Cleanup
...
llvm-svn: 54536
2008-08-08 18:22:59 +00:00
c31eb205c1
Add a flag to disable jump table generation (all
...
switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
llvm-svn: 54248
2008-07-31 18:13:12 +00:00
2ce6f2ad5e
Rename SDOperand to SDValue.
...
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
91e5dcb680
Tidy SDNode::use_iterator, and complete the transition to have it
...
parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.
llvm-svn: 54127
2008-07-27 20:43:25 +00:00
0f0aee213f
Fix a catastrophic PPC64 ABI bug: i32 operands which are passed in memory (all of the parameter registers are used) are loaded from sp offsets that were off by 4.
...
llvm-svn: 53979
2008-07-24 08:17:07 +00:00
b0e3938651
Add VerifyNode, a place to put sanity checks on
...
generic SDNode's (nodes with their own constructors
should do sanity checking in the constructor). Add
sanity checks for BUILD_VECTOR and fix all the places
that were producing bogus BUILD_VECTORs, as found by
"make check". My favorite is the BUILD_VECTOR with
only two operands that was being used to build a
vector with four elements!
llvm-svn: 53850
2008-07-21 10:20:31 +00:00
bc780e3441
Unbreak build: 'DarwinTargetAsmInfo' was already taken as PPC TAI flavour.
...
llvm-svn: 53801
2008-07-19 21:44:57 +00:00
2a28791789
Make sure custom lowering for LegalizeTypes
...
returns a node with the right number of
return values. This fixes codegen of
Generic/cast-fp.ll, Generic/fp_to_int.ll
and PowerPC/multiple-return-values.ll
when using -march=ppc32 -mattr=+64bit.
llvm-svn: 53794
2008-07-19 16:26:02 +00:00
1705968102
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
...
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
llvm-svn: 53728
2008-07-17 19:10:17 +00:00
32e376f354
Implement llvm.atomic.cmp.swap.i32 on PPC. Patch by Gary Benson!
...
llvm-svn: 53505
2008-07-12 02:23:19 +00:00
02c7c6cb33
Include a frame index in the "fixed stack" pseudo source value
...
instead of using the frame index for the SVOffset, which was
inconsistent.
llvm-svn: 53486
2008-07-11 22:44:52 +00:00
0597e5b697
Trim unnecessary #includes.
...
llvm-svn: 53471
2008-07-11 20:38:31 +00:00
60de1ae3d9
Remove extraneous vertical whitespace before Eric gets the wrong idea ;-)
...
llvm-svn: 53411
2008-07-10 16:49:53 +00:00
5e718e7431
Fix an altivec constant miscompilation that Duncan found through
...
his work on legalizetypes.
llvm-svn: 53410
2008-07-10 16:33:38 +00:00
ca43dce1e8
Remove extra call to DW.SetModuleInfo on Linux.
...
llvm-svn: 53365
2008-07-09 21:33:15 +00:00
dbd04c0783
Emit debug into for data-only files for Linux PPC.
...
I cannot test this target, let me know if it breaks!
llvm-svn: 53362
2008-07-09 21:24:07 +00:00
b9aaddc110
Emit debug info for data-only files. This version
...
applies to ppc Darwin only.
llvm-svn: 53353
2008-07-09 20:43:39 +00:00
49c8e68e4c
Back out 53254. It broke ppc debug info codegen.
...
llvm-svn: 53280
2008-07-09 06:36:53 +00:00
b9097a71d4
Make debug info come out in data-only files.
...
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason. I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.
llvm-svn: 53254
2008-07-08 21:56:22 +00:00
3b46030375
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
...
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
2008-07-07 23:14:23 +00:00
0189604b0a
Clean up PPC register specification.
...
llvm-svn: 53209
2008-07-07 22:22:07 +00:00
230263c63e
Simplify this use of BuildMI. This is also in preparation for
...
pool-allocating MachineInstrs.
llvm-svn: 53198
2008-07-07 20:09:12 +00:00
56e3f63ec5
Add explicit keywords.
...
llvm-svn: 53179
2008-07-07 18:00:37 +00:00
93e180342a
Rather than having a different custom legalization
...
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
llvm-svn: 53137
2008-07-04 11:47:58 +00:00
04fb6bf468
Linux also does not require exception handling
...
moves in order to get correct debug info. Since
I can't imagine how any target could possibly
be any different, I've just stripped out the
option: now all the world's like Darwin!
llvm-svn: 53134
2008-07-04 09:55:48 +00:00
7d98a48f15
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
...
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
llvm-svn: 53097
2008-07-03 09:09:37 +00:00
739a0548c4
Add a new getMergeValues method that does not need
...
to be passed the list of value types, and use this
where appropriate. Inappropriate places are where
the value type list is already known and may be
long, in which case the existing method is more
efficient.
llvm-svn: 53035
2008-07-02 17:40:58 +00:00
b7bd02be57
Darwin doesn't need exception handling information for the "move" info when
...
debug information is being output, because it's leet!
llvm-svn: 52994
2008-07-01 23:34:48 +00:00
fb19f9402b
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
...
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
llvm-svn: 52943
2008-07-01 00:05:16 +00:00
5c73a886b4
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
...
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
llvm-svn: 52924
2008-06-30 20:59:49 +00:00
0711d68fa7
Split scheduling from instruction selection.
...
llvm-svn: 52923
2008-06-30 20:45:06 +00:00
1ae6ef83ee
Revert the SelectionDAG optimization that makes
...
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
llvm-svn: 52893
2008-06-30 10:19:09 +00:00
c1e80a759f
Provide correct encoding for PPC LWARX instructions.
...
Patch by Gary Benson!
llvm-svn: 52828
2008-06-27 16:10:20 +00:00
d3406fc2a7
Switch the PPC backend and target-independent JIT to use the libsystem
...
InvalidateInstructionCache method instead of calling through
a hook on the JIT. This is a host feature, not a target feature.
llvm-svn: 52734
2008-06-25 17:18:44 +00:00
6a490371c9
Added MemOperands to Atomic operations since Atomics touches memory.
...
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub
llvm-svn: 52706
2008-06-25 08:15:39 +00:00
1f2b2a4abe
Remove unnecessary #includes.
...
llvm-svn: 52613
2008-06-22 19:21:26 +00:00
55083d5dd3
Use MachineBasicBlock::transferSuccessors.
...
llvm-svn: 52594
2008-06-21 20:21:19 +00:00
f51ed6a161
Add one more 'magic' define :)
...
llvm-svn: 52420
2008-06-17 17:57:43 +00:00
8e5d9214ba
Unbreak non-PPC builds
...
llvm-svn: 52419
2008-06-17 17:38:31 +00:00
7d7dcd52db
Provide generic hooks for icache invalidation. Add PPC implementation.
...
Patch by Gary Benson!
llvm-svn: 52418
2008-06-17 17:30:05 +00:00
8b69e8a647
Add support for icache invalidation on non-darwin ppc systems.
...
Patch by Gary Benson!
llvm-svn: 52332
2008-06-16 17:04:06 +00:00
03553bb59a
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
...
llvm-svn: 52308
2008-06-16 07:33:11 +00:00
11dd424539
Remove comparison methods for MVT. The main cause
...
of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits. Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.
llvm-svn: 52098
2008-06-08 20:54:56 +00:00
b7272db9f6
Temporarily reverting r52056. It's causing PPC to fail to bootstrap.
...
llvm-svn: 52085
2008-06-08 01:36:24 +00:00
0b8f2c53a2
Typo.
...
llvm-svn: 52062
2008-06-06 21:00:10 +00:00
9bf9110d93
PPC preferred loop alignment is 16.
...
llvm-svn: 52056
2008-06-06 19:50:46 +00:00
13237ac3b9
Wrap MVT::ValueType in a struct to get type safety
...
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
llvm-svn: 52044
2008-06-06 12:08:01 +00:00
355b74acc2
Add StringConstantPrefix to control what the
...
assembler names of string constants look like.
llvm-svn: 51909
2008-06-03 18:09:06 +00:00
305fcd493f
Add FreeBSD/PPC support, patch by Marcel Moolenaar!
...
llvm-svn: 51538
2008-05-24 04:58:48 +00:00
18cc4d3ea4
Put initialized const weak objects into correct
...
sections on ppc32 darwin. g++.dg/abi/key2.C
llvm-svn: 51527
2008-05-24 00:10:20 +00:00
002e554ce9
Add a missed CommonLinkage check.
...
llvm-svn: 51503
2008-05-23 21:33:27 +00:00
5bf742f2aa
Handle quoted names when constructing $stub's,
...
$non_lazy_ptr's and $lazy_ptr's.
llvm-svn: 51277
2008-05-19 21:38:18 +00:00
2e1d5e487b
Record weak external linkage in a case where we were
...
missing it. gcc.dg/darwin-weakimport-2.c.
Handle common and weak differently for darwin ppc32.
llvm-svn: 51201
2008-05-16 20:09:25 +00:00
ce4396bc92
Add CommonLinkage; currently tentative definitions
...
are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both. The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.
llvm-svn: 51118
2008-05-14 20:12:51 +00:00
eabd647cd5
Change target-specific classes to use more precise static types.
...
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
llvm-svn: 51091
2008-05-14 01:58:56 +00:00
d78c400b5b
Clean up the use of static and anonymous namespaces. This turned up
...
several things that were neither in an anonymous namespace nor static
but not intended to be global.
llvm-svn: 51017
2008-05-13 00:00:25 +00:00
be0de34ede
Tail call optimization improvements:
...
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
llvm-svn: 50477
2008-04-30 09:16:33 +00:00
724539c001
A few inline asm cleanups:
...
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
llvm-svn: 50312
2008-04-26 23:02:14 +00:00
33bd24bd92
add a note
...
llvm-svn: 50267
2008-04-25 17:25:00 +00:00
5102bd9359
64-bit atomic operations.
...
llvm-svn: 49949
2008-04-19 02:30:38 +00:00
51096affb5
PPC32 atomic operations.
...
llvm-svn: 49947
2008-04-19 01:30:48 +00:00
a7557dfe71
Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
...
the stub will resolve.
llvm-svn: 49814
2008-04-16 20:46:05 +00:00
ae84bbdbed
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
...
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
7000c8f1aa
Change Divided flag to Split, as suggested by Evan
...
llvm-svn: 49715
2008-04-15 08:08:50 +00:00
876224b1e8
Reverse sense of unwind-tables option. This means
...
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.
llvm-svn: 49663
2008-04-14 17:54:17 +00:00
dcc2eda5fc
Add a divided flag for the first piece of an argument divided into mulitple parts. Fixes PR1643
...
llvm-svn: 49611
2008-04-13 13:40:22 +00:00
544ab2c50b
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
...
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 04:36:06 +00:00
344aec2952
Implement new llc flag -disable-required-unwind-tables.
...
Corresponds to -fno-unwind-tables (usually default in gcc).
llvm-svn: 49361
2008-04-08 00:10:24 +00:00
3bc3ddd638
Rename MemOperand to MachineMemOperand. This was suggested by
...
review feedback from Chris quite a while ago. No functionality
change.
llvm-svn: 49348
2008-04-07 19:35:22 +00:00
51f532f92d
Re-commit of the r48822, where the infinite looping problem discovered
...
by Dan Gohman is fixed.
llvm-svn: 49330
2008-04-07 10:06:32 +00:00
025cea1126
Backing out 48222 temporarily.
...
llvm-svn: 49124
2008-04-03 03:13:16 +00:00
8780ecbbac
Cosmetic changes per EH patch review feedback.
...
llvm-svn: 49096
2008-04-02 17:04:45 +00:00
fd967cf3fa
Recommitting EH patch; this should answer most of the
...
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.
llvm-svn: 49064
2008-04-02 00:25:04 +00:00
5e4e051c2a
Revert 49006 for the moment.
...
llvm-svn: 49046
2008-04-01 20:00:57 +00:00
7d02cf3c9c
Emit exception handling info for functions which are
...
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.
llvm-gcc generates nounwind in the right places; other FEs
will need to do so also. Given such a FE, -enable-eh should
no longer be needed.
llvm-svn: 49006
2008-03-31 23:40:23 +00:00
ed6e34fe41
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
...
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
0f760dfe09
Fix "Control reaches the end of non-void function" warnings,
...
patch by David Chisnall.
llvm-svn: 48963
2008-03-30 18:22:13 +00:00
358e04a185
Use a linked data structure for the uses lists of an SDNode, just like
...
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
llvm-svn: 48822
2008-03-26 12:39:26 +00:00
ddc58ff92a
Smaller function alignment when optimizing for size.
...
llvm-svn: 48805
2008-03-25 22:29:46 +00:00
c60c67fc37
Add explicit keywords.
...
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
bdc24adaaf
A quick nm audit turned up several fixed tables and objects that were
...
marked read-write. Use const so that they can be allocated in a
read-only segment.
llvm-svn: 48800
2008-03-25 21:45:14 +00:00
6306183df3
Use the bit size of the operand instead of the hard-coded 32 to generate the
...
mask.
llvm-svn: 48750
2008-03-24 23:16:37 +00:00
d97eea372a
Introduce a new node for holding call argument
...
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
llvm-svn: 48640
2008-03-21 09:14:45 +00:00
a7cca362af
detabify llvm, patch by Mike Stump!
...
llvm-svn: 48577
2008-03-20 01:22:40 +00:00
b9056838d2
Add support for multiple return values for the PPC target by
...
converting call result lowering to use the CallingConvLowering
infastructure.
llvm-svn: 48552
2008-03-19 21:39:28 +00:00
cf87e71053
Make Complex long long/double/long double work
...
in ppc64 mode.
llvm-svn: 48459
2008-03-17 17:11:08 +00:00
24bc123e80
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48447
2008-03-17 06:56:52 +00:00
92dcf1e0c2
Next round of PPC32 ABI changes. Allow for gcc
...
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
llvm-svn: 48439
2008-03-17 02:13:43 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
0dfd3f33f7
Implement the real calling convention for ppc32 Altivec:
...
vectors go at the end of the memory area, after all
non-vector parameters.
llvm-svn: 48364
2008-03-14 17:41:26 +00:00
6424bd0b11
Do not promote float params to double in varargs
...
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
llvm-svn: 48310
2008-03-12 23:40:01 +00:00
0d98256c05
One more bit of Altivec parameter passing.
...
llvm-svn: 48269
2008-03-12 00:49:20 +00:00
b28456ef18
Implement Altivec passing to varargs functions on ppc.
...
llvm-svn: 48264
2008-03-12 00:22:17 +00:00
24570836b2
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
d6819da453
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
0fb187f81b
Disable prolog code that aligns the stack when a
...
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
c6c48fca74
Change the "enable/disable" mechanism so that we can enable PPC register
...
scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
ae2c56d93e
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
514b3ed536
fix 80 col violations.
...
llvm-svn: 48166
2008-03-10 18:55:53 +00:00
708784ea4f
Stylistic modifications. No functionality changes.
...
llvm-svn: 48158
2008-03-10 17:46:45 +00:00
a6729e8666
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
b1de7a35f9
Add description of individual bits in CR. This fix PR1765.
...
llvm-svn: 48143
2008-03-10 14:12:10 +00:00
4e622ec86d
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
...
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
aed9406bb7
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
...
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
llvm-svn: 48120
2008-03-09 20:49:33 +00:00
21a8f144a6
More ppc32 byval handling (bug fixes). Things
...
are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
95cf661534
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
...
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
d2ab5fd713
Add support for calls with i128 return values on ppc64.
...
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
968f32ce3d
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
...
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
8d2ead2e34
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
bfa252d402
Next bits of PPC byval handling. Basically functional
...
but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
20b5a2b037
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
...
llvm-svn: 48027
2008-03-07 20:18:24 +00:00
25ff7e217d
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
...
with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
0d235052d1
Next bit of PPC ByVal handling; call-site code seems
...
correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
3fcd946c26
Removed spurious EnablePPCRS check.
...
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
85d41a1c44
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
1af20ad336
Use a command-line option to turn register scavenging on/off for PPC.
...
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
632ea65072
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
6b0a189225
add a note
...
llvm-svn: 47830
2008-03-02 19:27:34 +00:00
bd0bb3f07f
Evan implemented this.
...
llvm-svn: 47827
2008-03-02 17:56:29 +00:00
0e8b146152
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
cbde4c2206
Interface of getByValTypeAlignment differed between
...
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
llvm-svn: 47734
2008-02-28 22:31:51 +00:00
c799065cc3
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
...
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
d73396bef9
EHPreferredDataFormat hook for PPC targets. Looks like Darwin
...
uses the same encoding everywhere. Linux FIXME'ed.
llvm-svn: 47701
2008-02-27 23:49:15 +00:00
26854f242e
Don't hard-code the mask size to be 32, which is incorrect on ppc64
...
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
llvm-svn: 47692
2008-02-27 21:12:32 +00:00
97925ec704
Final de-tabification.
...
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
f19609abe8
Convert the last remaining users of the non-APInt form of
...
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
llvm-svn: 47654
2008-02-27 01:23:58 +00:00
d7a258d325
Rename PrintableName to Name.
...
llvm-svn: 47629
2008-02-26 21:47:57 +00:00
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
...
would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
a7d1ed4c98
Some platforms use the same name for 32-bit and 64-bit registers (like
...
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
llvm-svn: 47534
2008-02-24 00:56:13 +00:00
40d67c59d5
Remove bunch of gcc 4.3-related warnings from Target
...
llvm-svn: 47369
2008-02-20 11:22:39 +00:00
fedcf477b5
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
...
llvm-svn: 47213
2008-02-16 14:46:26 +00:00
7b1431785b
Handle \n's in value names for more targets. The asm printers
...
really really really need refactoring :(
llvm-svn: 47171
2008-02-15 19:04:54 +00:00
2e01912f1a
Cosmetics.
...
llvm-svn: 47168
2008-02-15 18:40:53 +00:00
67b818f503
Remove warning about 64-bit code on processor
...
that doesn't support it. Per Chris.
llvm-svn: 47162
2008-02-15 18:09:51 +00:00
6ca3ccf519
Rewrite tblgen handling of subtarget features so
...
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to. Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.
llvm-svn: 47143
2008-02-14 23:35:16 +00:00
53e1b3f9d5
Change how FP immediates are handled.
...
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
llvm-svn: 47121
2008-02-14 08:57:00 +00:00
e1d9ee66ed
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
...
to pass the mask APInt by value, not by reference.
llvm-svn: 47096
2008-02-13 22:28:48 +00:00
21ad494f67
Enable exception handling int JIT
...
llvm-svn: 47079
2008-02-13 18:39:37 +00:00
d973e836f1
Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.
...
llvm-svn: 47067
2008-02-13 17:24:14 +00:00
f6518cf4ab
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
...
DAGCombine is now quite good at zapifying them.
llvm-svn: 47053
2008-02-13 07:35:30 +00:00
eea32990a9
readme updates
...
llvm-svn: 47051
2008-02-13 07:06:12 +00:00
87abe955fc
Make register scavenging happy by not using a reg (CR0) that isn't defined
...
llvm-svn: 47045
2008-02-13 02:58:33 +00:00
244183ef0d
commuteInstr() can now commute non-ssa machine instrs.
...
llvm-svn: 47043
2008-02-13 02:46:49 +00:00
f990faf23b
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
...
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
llvm-svn: 47039
2008-02-13 00:35:47 +00:00
83af1197ca
Revert r46916 PPCTargetAsmInfo.cpp.
...
llvm-svn: 47020
2008-02-12 19:25:12 +00:00
3090b0fbd1
additional missing feature
...
llvm-svn: 46948
2008-02-11 04:16:09 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
...
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
52ea27db17
Match GCC's behaviour for these sections.
...
llvm-svn: 46916
2008-02-10 00:03:54 +00:00
3b3286d4bc
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
...
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
16d4bc3dc0
Follow Chris' suggestion; change the PseudoSourceValue accessors
...
to return pointers instead of references, since this is always what
is needed.
llvm-svn: 46857
2008-02-07 18:41:25 +00:00
2d489b5081
Re-apply the memory operand changes, with a fix for the static
...
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
llvm-svn: 46827
2008-02-06 22:27:42 +00:00
f3c89be368
Ident mnemonics appropriately
...
llvm-svn: 46746
2008-02-05 08:49:09 +00:00
2cb9068c78
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
...
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
32e5347eb8
Get rid of the annoying blank lines before labels.
...
llvm-svn: 46667
2008-02-02 08:39:46 +00:00
2aa360adf8
Unbreak ppc debug support.
...
llvm-svn: 46665
2008-02-02 05:06:29 +00:00
efd142a920
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
...
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
llvm-svn: 46659
2008-02-02 04:07:54 +00:00
d6e44ab5ec
Remove the nasty LABEL hack with a much less evil one. Now llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before.
...
llvm-svn: 46635
2008-02-01 09:10:45 +00:00
27b32b87ed
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
...
llvm-svn: 46623
2008-01-31 21:00:00 +00:00
1c6c16ea11
Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution.
...
llvm-svn: 46609
2008-01-31 09:59:15 +00:00
3c0486fb38
Makes the same change in ppc backend: avoid inserting prologue before debug labels.
...
llvm-svn: 46596
2008-01-31 03:33:38 +00:00
9ba4d76816
Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
...
with the real FLT_ROUNDS (defined in <float.h>).
llvm-svn: 46587
2008-01-31 00:41:03 +00:00
3646fdda67
Create a new class, MemOperand, for describing memory references
...
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
llvm-svn: 46585
2008-01-31 00:25:39 +00:00
29cfb67e28
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
...
instruction at the end.
llvm-svn: 46562
2008-01-30 18:18:23 +00:00
47a7d6fafe
Factor the addressing mode and the load/store VT out of LoadSDNode
...
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
llvm-svn: 46538
2008-01-30 00:15:11 +00:00
1a17ef02c8
If there's no instructions being emitted on X86 for a function, emit a
...
nop. Emit the nop directly for PPC.
llvm-svn: 46398
2008-01-26 09:03:52 +00:00
5079483957
If there are no machine instructions emitted for a function, then insert
...
a "nop" instruction so that we don't have the function's label associated
with something that it's not supposed to be associated with.
llvm-svn: 46394
2008-01-26 06:51:24 +00:00
919ad97c01
JITEmitter.cpp was trying to sync the icache for function stubs, but
...
was actually passing a completely incorrect size to sys_icache_invalidate.
Instead of having the JITEmitter do this (which doesn't have the correct
size), just make the target sync its own stubs.
llvm-svn: 46354
2008-01-25 16:41:09 +00:00
95d46ef887
The last pieces needed for loading arbitrary
...
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
llvm-svn: 46280
2008-01-23 20:39:46 +00:00
7f1ff5fedd
Honor explicit section information on Darwin.
...
llvm-svn: 46267
2008-01-23 00:58:14 +00:00
5c94cb3596
Implement flt_rounds for PowerPC.
...
llvm-svn: 46174
2008-01-18 19:55:37 +00:00
87757d38b3
get symbolic information for ppc ldbl nodes.
...
llvm-svn: 46165
2008-01-18 18:51:16 +00:00
f5b46f7dad
Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to:
...
_test:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of:
_test:
fctiwz f0, f1
stfd f0, -8(r1)
nop
nop
lwz r2, -4(r1)
stb r2, 0(r4)
blr
The former is not correct (stores 4 bytes, not 1).
llvm-svn: 46161
2008-01-18 16:54:56 +00:00
60a9855799
Revert the part of 45848 that treated weak globals
...
as weak globals rather than commons. While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.
llvm-svn: 46144
2008-01-17 23:04:07 +00:00
1ea55cf816
This commit changes:
...
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
72733e573b
* Introduce a new SelectionDAG::getIntPtrConstant method
...
and switch various codegen pieces and the X86 backend over
to using it.
* Add some comments to SelectionDAGNodes.h
* Introduce a second argument to FP_ROUND, which indicates
whether the FP_ROUND changes the value of its input. If
not it is safe to xform things like fp_extend(fp_round(x)) -> x.
llvm-svn: 46125
2008-01-17 07:00:52 +00:00
59a2250b0d
Fix and enable EH for x86-64 Darwin. Adds
...
ShortenEHDataFor64Bits as a not-very-accurate
abstraction to cover all the changes in DwarfWriter.
Some cosmetic changes to Darwin assembly code for
gcc testsuite compatibility.
llvm-svn: 46029
2008-01-15 23:24:56 +00:00
8e07533f20
If someone wants to implement ppc TRAP, they can go for it :)
...
llvm-svn: 46019
2008-01-15 22:15:02 +00:00
9a249b0ce5
rename SDTRet -> SDTNone.
...
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
llvm-svn: 46017
2008-01-15 22:02:54 +00:00
596875118c
rename MachineInstr::setInstrDescriptor -> setDesc
...
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
2ff66f08f2
Weak things initialized to 0 don't go in bss on Darwin.
...
Cosmetic changes to spacing to match gcc (some dejagnu
tests actually care).
llvm-svn: 45848
2008-01-11 00:54:37 +00:00
53c954fa86
Output sinl for a long double FSIN node, not sin.
...
Likewise fix up a bunch of other libcalls. While
there I remove NEG_F32 and NEG_F64 since they are
not used anywhere. This fixes 9 Ada ACATS failures.
llvm-svn: 45833
2008-01-10 10:28:30 +00:00
aca7ca3730
remove explicit sets of 'neverHasSideEffects' that can now be
...
inferred from the instr patterns.
llvm-svn: 45824
2008-01-10 05:45:39 +00:00
94de7bc3aa
get def use info more correct.
...
llvm-svn: 45821
2008-01-10 05:12:37 +00:00
7ecb3b79c7
Emit unused EH frames for weak definitions on Darwin,
...
because assembler/linker can't cope with weak absolutes.
PR 1880.
llvm-svn: 45811
2008-01-10 02:03:30 +00:00
bb956ca730
Use size_t to store Pos, avoid truncating value
...
on 64-bit builds. Analysis and original patch
by Török Edwin. Code audit found another place
with the same problem, also fixed here.
llvm-svn: 45746
2008-01-08 10:06:15 +00:00
89f36e6b21
Finally implement correct ordered comparisons for PPC, even though
...
the code generated is not wonderful. This turns a miscompilation into
a code quality bug (noted in the ppc readme). This fixes PR642, which
is over 2 years old (!). Nate, please review this.
llvm-svn: 45742
2008-01-08 06:46:30 +00:00
03ad885039
rename TargetInstrDescriptor -> TargetInstrDesc.
...
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
2008-01-07 07:27:27 +00:00
d004f54155
use predicate.
...
llvm-svn: 45691
2008-01-07 06:37:29 +00:00
6077962101
no need to explicitly clear these fields.
...
llvm-svn: 45683
2008-01-07 04:55:09 +00:00
b0d06b4381
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
...
llvm-svn: 45680
2008-01-07 03:13:06 +00:00
f0f438a517
remove MachineOpCode typedef.
...
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
a98c679de0
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
...
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
llvm-svn: 45674
2008-01-07 01:56:04 +00:00
2a3be7bb6c
Move even more functionality from MRegisterInfo into TargetInstrInfo.
...
Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
a4ce4f6987
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
...
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
10324d0175
rename isStore -> mayStore to more accurately reflect what it captures.
...
llvm-svn: 45656
2008-01-06 08:36:04 +00:00
a348f55ec6
Change the 'isStore' inferrer to look for 'SDNPMayStore'
...
instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
llvm-svn: 45654
2008-01-06 06:44:58 +00:00
e20f380fbf
remove some isStore flags that are now inferred automatically.
...
llvm-svn: 45652
2008-01-06 05:53:26 +00:00
2e1ba07f16
Correct order of parameters.
...
llvm-svn: 45562
2008-01-04 02:22:21 +00:00
563fcc3428
Change MachineRelocation::DoesntNeedFnStub to NeedStub. This fields will be used
...
for non-function GV relocations that require function address stubs (e.g. Mac OS X in non-static mode).
llvm-svn: 45527
2008-01-03 02:56:28 +00:00
dcbc0f3029
leopard and above support alignment for common symbols.
...
llvm-svn: 45493
2008-01-02 19:35:16 +00:00
eee14601b1
Move some more instruction creation methods from RegisterInfo into InstrInfo.
...
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
b0fb17fd34
Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...
...
llvm-svn: 45476
2008-01-01 01:05:34 +00:00
25568e4cef
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
...
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
llvm-svn: 45475
2008-01-01 01:03:04 +00:00
7a73ae9a86
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
...
Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
a10fff51d9
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
...
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
llvm-svn: 45467
2007-12-31 04:13:23 +00:00
a5bb370aa4
Add new shorter predicates for testing machine operands for various types:
...
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
6005589faf
More cleanups for MachineOperand:
...
- Eliminate the static "print" method for operands, moving it
into MachineOperand::print.
- Change various set* methods for register flags to take a bool
for the value to set it to. Remove unset* methods.
- Group methods more logically by operand flavor in MachineOperand.h
llvm-svn: 45461
2007-12-30 21:56:09 +00:00
5c4637816e
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
...
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
a087a8d2ce
remove attribution from lib Makefiles.
...
llvm-svn: 45415
2007-12-29 20:09:26 +00:00
31a2c3948e
Fix unintented change from last commit
...
llvm-svn: 45282
2007-12-21 12:22:29 +00:00
80c741e160
Enable EH for linux/ppc32 targets
...
llvm-svn: 45281
2007-12-21 12:19:44 +00:00
eadbf4b91c
Enable EH on PPC Darwin. This basically works; there
...
are a couple of issues that show up with the optimizer,
but I don't think they're really EH problems.
(llvm-gcc testsuite users note: By default the testsuite
uses the unwinding code that's built as part of your local
llvm-gcc, which does not work. You need to trick it into
using the installed system unwinding code to get useful
results.)
llvm-svn: 45221
2007-12-19 21:54:36 +00:00
ca77ecb40a
Mark the "isRemat" instruction as never having side effects.
...
llvm-svn: 45190
2007-12-19 06:07:48 +00:00
6e68381e02
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
...
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
f47015bc74
Fix a significant code quality regression I introduced on PPC64 quite
...
a while ago. We now produce:
_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
instead of:
_foo:
mflr r0
std r0, 16(r1)
lis r0, 0
ori r0, r0, 16
ldx r2, r1, r0
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
for:
void foo(void **X) {
*X = __builtin_return_address(0);
}
on ppc64.
llvm-svn: 44701
2007-12-08 07:04:58 +00:00
f6a8156e4f
implement __builtin_return_addr(0) on ppc.
...
llvm-svn: 44700
2007-12-08 06:59:59 +00:00
a6c8297e84
refactor some code to avoid overloading the name 'usesLR' in
...
different places to mean different things. Document what the
one in PPCFunctionInfo means and when it is valid.
llvm-svn: 44699
2007-12-08 06:39:11 +00:00
ab87e735cd
Fix a compilation warning.
...
llvm-svn: 44691
2007-12-08 01:00:21 +00:00
fb706bc52b
Initial commit of the machine code LICM pass. It successfully hoists this:
...
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-07 21:42:31 +00:00
3b8a674469
Added canFoldMemoryOperand for PPC.
...
llvm-svn: 44623
2007-12-05 18:41:29 +00:00
bb26301864
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
...
the stored register is killed.
llvm-svn: 44600
2007-12-05 03:14:33 +00:00
f45a1d623c
Remove redundant foldMemoryOperand variants and other code clean up.
...
llvm-svn: 44517
2007-12-02 08:30:39 +00:00
69fda0a716
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
...
llvm-svn: 44479
2007-12-01 02:07:52 +00:00
57ee7c6630
Implement ExpandOperationResult for ppc i64 fp->int, which fixes
...
CodeGen/Generic/fp_to_int.ll among others. Its unclear why this
just started failing...
llvm-svn: 44407
2007-11-28 18:44:47 +00:00
79ae9895f6
Fix a crash on invalid code due to memcpy lowering.
...
llvm-svn: 44378
2007-11-27 22:14:42 +00:00
763e110a9f
Fix .eh table linkage issues on Darwin. Some EH support
...
for Darwin PPC, but it's not fully working yet.
llvm-svn: 44258
2007-11-20 23:24:42 +00:00
aad83c8ee5
Remove meaningless qualifiers from return types, avoiding compiler warnings.
...
llvm-svn: 44240
2007-11-19 20:46:23 +00:00
7904708369
Revert previous; these files aren't ready to go in yet.
...
llvm-svn: 44057
2007-11-13 19:16:02 +00:00
7a7085f6d3
Add parameter to getDwarfRegNum to permit targets
...
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
llvm-svn: 44056
2007-11-13 19:13:01 +00:00
77b13af9a6
Unifacalize the CALLSEQ{START,END} stuff.
...
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
f359fed9f9
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
...
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
bfb139ec93
Completely forgot, that we have some debug information emission on PPC. This should fix
...
some regressions on ppc nightly tests.
llvm-svn: 44029
2007-11-12 23:36:13 +00:00
933b5b7e62
Add a flag for indirect branch instructions.
...
Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
4edfea438a
Use TableGen to emit information for dwarf register numbers.
...
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
llvm-svn: 43997
2007-11-11 19:50:10 +00:00
283207a71c
Eliminate the remaining uses of getTypeSize. This
...
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
llvm-svn: 43688
2007-11-05 00:04:43 +00:00
d954dcd138
Fix crash before main on ppc/linux with static constructors. PR1771
...
llvm-svn: 43676
2007-11-04 17:32:10 +00:00
10f4152471
Disable a couple more things for ppcf128.
...
llvm-svn: 43267
2007-10-23 23:20:14 +00:00
ec271b104c
Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with right callee-saved defs set for ppc64.
...
llvm-svn: 43248
2007-10-23 06:42:42 +00:00
bdbed66333
Use ptr type in the immediate field of a BxA instruction so we don't end up selecting 32-bit call instruction for ppc64.
...
llvm-svn: 43228
2007-10-22 19:46:19 +00:00
b193576bc6
comment fixes
...
llvm-svn: 43168
2007-10-19 04:08:28 +00:00
10432e5a67
More ppcf128 issues (maybe the last)?
...
llvm-svn: 43160
2007-10-19 00:59:18 +00:00
463e2ab0ac
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
...
- Fix some copy+paste bugs.
llvm-svn: 43153
2007-10-18 22:40:57 +00:00
aa9a225699
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
...
llvm-svn: 43150
2007-10-18 21:29:24 +00:00
1366653e2f
Fix a bug handling frame references in ppc inline asm when the frame offset
...
doesn't fit into 16 bits.
llvm-svn: 43032
2007-10-16 18:00:18 +00:00
06a4954e6e
Change LowerFP_TO_SINT to create the specific code it needs instead of
...
unconditionally creating an i64 bitcast. With the future legalizer
design, operation legalization can't introduce new nodes with illegal
types.
This fixes the rest of olden on ppc32.
llvm-svn: 43005
2007-10-15 20:14:52 +00:00
cdf3609130
Revert 42908 for now.
...
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
2f6b6d6fb0
Fix type mismatch error in PPC Altivec (only causes
...
a problem when asserts are on). From vecLib.
llvm-svn: 42959
2007-10-14 01:58:32 +00:00
dc35bd79ca
Change the names used for internal labels to use the current
...
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
llvm-svn: 42908
2007-10-12 14:53:36 +00:00
9013eaff9a
Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC.
...
llvm-svn: 42904
2007-10-12 14:08:57 +00:00
482732af9d
Set ISD::FPOW to Expand.
...
llvm-svn: 42881
2007-10-11 23:21:31 +00:00
666323eacd
Next PPC long double bits: ppcf128->i32 conversion.
...
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).
llvm-svn: 42822
2007-10-10 01:01:31 +00:00
71f0d7d76e
When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM in
...
target-indepenent lowering, don't use them on PowerPC.
llvm-svn: 42755
2007-10-08 17:28:24 +00:00
f864ac96d8
Next powerpc long double bits. Comparisons work,
...
although not well, and shortening FP converts.
llvm-svn: 42672
2007-10-06 01:24:11 +00:00
c0154c06d6
First round of ppc long double. call/return and
...
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.
llvm-svn: 42644
2007-10-05 20:04:43 +00:00
f4cf5dcdd2
- Added a few target hooks to generate load / store instructions from / to any
...
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
llvm-svn: 42621
2007-10-05 01:32:41 +00:00
c731c97fac
Use empty() member functions when that's what's being tested for instead
...
of comparing begin() and end().
llvm-svn: 42585
2007-10-03 19:26:29 +00:00
a1d46c7d0a
TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
...
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.
llvm-svn: 42419
2007-09-27 23:12:31 +00:00
c1e4e3743b
Allow copyRegToReg to emit cross register classes copies.
...
Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
57211c5550
More explicit keywords.
...
llvm-svn: 42316
2007-09-25 20:27:06 +00:00
1ff71872c2
Honor user-defined section specification of a global, ignores whether its initializer is null.
...
llvm-svn: 42182
2007-09-21 00:41:19 +00:00
d29f938335
Do not override user specified section.
...
llvm-svn: 42179
2007-09-20 23:07:37 +00:00
9da02f5ee2
Remove isReg, isImm, and isMBB, and change all their users to use
...
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
2007-09-14 20:33:02 +00:00
5196f617a1
Fix comments.
...
llvm-svn: 41947
2007-09-14 01:57:02 +00:00
66c22e8fd6
Enable indirect encoding for the personality function
...
llvm-svn: 41873
2007-09-11 23:55:40 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
...
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
...
init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
6777b72659
Add some notes about better flag handling.
...
llvm-svn: 41808
2007-09-10 21:43:18 +00:00
9929bc403d
Add missing index versions of instructions to the map.
...
llvm-svn: 41776
2007-09-07 22:01:02 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
...
Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
b65ef38590
LVXL and STVXL are also a load and store resp.
...
llvm-svn: 41733
2007-09-05 23:47:12 +00:00
b9bf812ba5
Add the 64-bit versions of the DS* Altivec instructions.
...
llvm-svn: 41717
2007-09-05 04:05:20 +00:00
4dbd9f254a
Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.
...
llvm-svn: 41711
2007-09-04 20:20:29 +00:00
3cf889f75e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
...
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
llvm-svn: 41632
2007-08-31 04:03:46 +00:00
9a25d98c86
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
...
llvm-svn: 41597
2007-08-30 05:52:20 +00:00
10e18dea2a
Use i64 on a PPC64 machine
...
llvm-svn: 41590
2007-08-30 00:59:19 +00:00
d8c9cb9182
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
...
changing the interface to allow for future changes.
llvm-svn: 41384
2007-08-25 00:47:38 +00:00
a124f69c52
Disable EH generation until PPC works 100%.
...
llvm-svn: 41360
2007-08-24 16:00:15 +00:00
92c6a65d4e
new example
...
llvm-svn: 41318
2007-08-23 15:16:03 +00:00
f5124b36e4
Fix arguments for some Altivec instructions. From SWB.
...
llvm-svn: 40957
2007-08-09 00:49:19 +00:00
4e7ff3593c
Fix spelling of mtvscr and mfvscr.
...
llvm-svn: 40908
2007-08-07 23:08:00 +00:00
c5283ecd6f
long double patch 2 of N. Handle it in TargetData.
...
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)
llvm-svn: 40792
2007-08-03 20:20:50 +00:00
5f6a9da530
More explicit keywords.
...
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
58c3c30921
Some out operands were incorrectly specified as input operands.
...
llvm-svn: 40697
2007-08-01 23:07:38 +00:00
581d2795dc
Vector fneg must be expanded into fsub -0.0, X.
...
llvm-svn: 40586
2007-07-30 07:51:22 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
...
still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
cf0a5349de
Don't ignore the return value of AsmPrinter::doInitialization and
...
AsmPrinter::doFinalization.
llvm-svn: 40487
2007-07-25 19:33:14 +00:00
5805c46e8f
Fix debug info and globals filled with zeros.
...
llvm-svn: 40483
2007-07-25 03:48:45 +00:00
ac1591be42
No more noResults.
...
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
...
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
9081ab8127
Oops. These stores actually produce results.
...
llvm-svn: 40074
2007-07-20 00:20:46 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
383a324735
Long live the exception handling!
...
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
...
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
09d73c0305
Assert when TLS is not implemented.
...
llvm-svn: 39737
2007-07-11 17:19:51 +00:00
f8f531bf69
Change getCopyToParts and getCopyFromParts to always use target-endian
...
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
2007-07-09 20:59:04 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
...
zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
...
llvm-svn: 37961
2007-07-06 23:22:46 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
...
Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
ea4a82bcfb
PPC conditional branch predicate does not change after isel.
...
llvm-svn: 37893
2007-07-05 07:09:50 +00:00
2660cef6d7
Convert .cvsignore files
...
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
58d1eacd80
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
...
llvm-svn: 37790
2007-06-29 01:25:06 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
7936d91f70
describe an argument, hide it.
...
llvm-svn: 37650
2007-06-19 05:46:06 +00:00
944200be45
If a function is vararg, never pass inreg arguments in registers. Thanks to
...
Anton for half of this patch.
llvm-svn: 37641
2007-06-19 00:13:10 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
...
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
cff3e122b0
Implementation of compilation callback in PPC ELF32
...
llvm-svn: 37340
2007-05-29 16:33:18 +00:00
f9cbdc676c
name change requested by review of previous patch
...
llvm-svn: 37289
2007-05-22 18:31:04 +00:00
82810c8a13
Make tail merging the default, except on powerPC. There was no prior art
...
for a target-dependent default with a command-line override; this way
should be generally usable.
llvm-svn: 37285
2007-05-22 17:14:46 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
...
llvm-svn: 37266
2007-05-21 18:44:17 +00:00
c12dd5207d
Apply this patch:
...
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
llvm-svn: 37240
2007-05-18 23:21:46 +00:00
99be49dd9b
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37192
2007-05-18 00:05:48 +00:00
3e549e9d5f
add support for 128-bit add/sub on ppc64
...
llvm-svn: 37158
2007-05-17 06:52:46 +00:00
0b7472da6f
fix some subtle inline asm selection issues
...
llvm-svn: 37067
2007-05-15 01:31:05 +00:00
d194a8603d
PredicateOperand can be used as a normal operand for isel.
...
llvm-svn: 36947
2007-05-08 21:06:08 +00:00
f50ba31ec6
R0 is a sub-register of X0, etc.
...
llvm-svn: 36939
2007-05-08 17:03:51 +00:00
90bb4fc96b
revert accidental commit
...
llvm-svn: 36668
2007-05-03 16:40:25 +00:00
c1a2a3b344
add support for printing offset of global
...
llvm-svn: 36667
2007-05-03 16:39:48 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
5662b21db1
eliminateFrameIndex() change.
...
llvm-svn: 36626
2007-05-01 09:13:03 +00:00
27a625a74b
llvm bug #1350 , parts 1, 2, and 3.
...
llvm-svn: 36618
2007-05-01 05:57:02 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
cb35c61a4b
Fix PR1351 and CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
...
llvm-svn: 36410
2007-04-24 22:51:03 +00:00
19ccd6226c
Fix a bug in PPCTargetLowering::isLegalAddressingMode, scales other than 0/1/2
...
are always unsupported.
llvm-svn: 35835
2007-04-09 22:10:05 +00:00
e9f516384d
Squelch a warning about mismatch between sign of constant and sign of return
...
type.
llvm-svn: 35674
2007-04-04 22:07:24 +00:00
23710a7da3
Starting implementation of the ELF32 ABI specification of varargs handling.
...
LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
llvm-svn: 35625
2007-04-03 13:59:52 +00:00
b3e99a18ee
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
...
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/ ).
Change all ELF tests to ELF32.
llvm-svn: 35624
2007-04-03 12:35:28 +00:00
ab559f6e3c
Addition to the previous commit for getCalleeSavedRegClasses:
...
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."
llvm-svn: 35623
2007-04-03 10:57:49 +00:00
fbfc451ba9
The ELF ABI specifies F1-F8 registers as argument registers for double, not
...
F1-F10. This affects only ELF, not MachO.
llvm-svn: 35622
2007-04-03 10:27:07 +00:00
3e21eb7fd7
Fix a bug which caused us to never be able to use signed comparisons for
...
equality comparisons of a constant. This allows us to codegen the 'sintzero'
loop in PR1288 as:
LBB1_1: ;cond_next
li r4, 0
addi r2, r2, 1
stw r4, 0(r3)
addi r3, r3, 4
cmpwi cr0, r2, -1
bne cr0, LBB1_1 ;cond_next
instead of:
LBB1_1: ;cond_next
addi r2, r2, 1
li r4, 0
xoris r5, r2, 65535
stw r4, 0(r3)
addi r3, r3, 4
cmplwi cr0, r5, 65535
bne cr0, LBB1_1 ;cond_next
This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.
llvm-svn: 35590
2007-04-02 05:59:42 +00:00
075b4db621
add a note
...
llvm-svn: 35530
2007-03-31 07:06:25 +00:00
1eb94d973a
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
682baf2dda
"The C standards do say that "char" may either be a "signed char" or "unsigned
...
char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php
llvm-svn: 35382
2007-03-27 16:33:08 +00:00
26ad3e7191
add a note
...
llvm-svn: 35334
2007-03-25 05:10:46 +00:00
9c9e2f1af2
add a note
...
llvm-svn: 35330
2007-03-25 04:46:28 +00:00
8810241ebc
Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll
...
llvm-svn: 35329
2007-03-25 04:44:03 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
4ea5217880
Protect R31's frame offset from being used by callee-saved registers, when R31
...
is the frame pointer.
llvm-svn: 35233
2007-03-21 16:44:14 +00:00
61f39d186c
Added MRegisterInfo hook to re-materialize an instruction.
...
llvm-svn: 35205
2007-03-20 08:09:38 +00:00
7aad92868c
Stack and register alignment of call arguments in the ELF ABI
...
llvm-svn: 35083
2007-03-13 15:02:46 +00:00
b9dce9db85
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35074
2007-03-12 23:29:01 +00:00
ddf082082c
Putting more constants which do not contain relocations into .literal{4|8|16}
...
llvm-svn: 35026
2007-03-08 08:31:54 +00:00
d918477ac3
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
...
sections.
llvm-svn: 35017
2007-03-08 01:25:25 +00:00
8b8cac289b
Minor interface change.
...
llvm-svn: 34967
2007-03-06 10:05:14 +00:00
4f2e4e0f92
Switch PPC return lower to use an autogenerated CC description.
...
llvm-svn: 34940
2007-03-06 00:59:59 +00:00
e6049c2f08
Emit low/high immediate loads properly for Linux/PPC.
...
llvm-svn: 34871
2007-03-03 05:29:51 +00:00
75ab9799df
Implemented the frameaddress intrinsic for PPC.
...
llvm-svn: 34787
2007-03-01 13:11:38 +00:00
e0232ec706
More Mach-O writer improvements.
...
llvm-svn: 34740
2007-02-28 07:40:50 +00:00
95ae95a6a6
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
...
llvm-svn: 34707
2007-02-28 00:21:17 +00:00
b524dfd557
Fix parenthesis for BCTRL_{ELF|Macho} test.
...
llvm-svn: 34668
2007-02-27 13:10:41 +00:00
89d81878d2
Differentiate between the MachO and the ELF ABI the CALL instruction.
...
llvm-svn: 34667
2007-02-27 13:01:19 +00:00
b6e200bd68
Duplicate use of LR, take 2.
...
llvm-svn: 34666
2007-02-27 11:55:45 +00:00
5d7ce57c13
Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
...
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29
llvm-svn: 34652
2007-02-27 02:55:29 +00:00
535bd6d3ba
always lower to RETFLAG, never leave it as just ret.
...
llvm-svn: 34639
2007-02-26 19:44:02 +00:00
1ee61ab414
no really, this is the right patch
...
llvm-svn: 34605
2007-02-25 20:01:40 +00:00
4d2f5f8740
always promote float varargs to double.
...
llvm-svn: 34604
2007-02-25 19:59:18 +00:00
84ab9a556c
one important bugfix: PPC32 didn't have both elf and macho support for
...
external symbols and global addresses. Add the missing ones.
one important workaround: PPCISD::CALL is matched by both PPCcall_ELF
and PPCcall_Macho, disable the _ELF patterns for now.
llvm-svn: 34601
2007-02-25 19:20:53 +00:00
43df5b335c
implement support for the linux/ppc function call ABI. Patch by
...
Nicolas Geoffray!
llvm-svn: 34574
2007-02-25 05:34:32 +00:00
b9bd34f54a
Add XLForm_1_ext template, patch by Nicolas Geoffray.
...
llvm-svn: 34573
2007-02-25 05:07:49 +00:00
249edb8b67
Improve JIT support for linux/ppc: Patch by Nicolas Geoffray!
...
llvm-svn: 34572
2007-02-25 05:04:13 +00:00
2f28a3cf08
Don't spill LR as a callee saved register.
...
llvm-svn: 34533
2007-02-23 20:34:16 +00:00
df5899258c
By default, spills kills the register being stored.
...
llvm-svn: 34515
2007-02-23 01:10:04 +00:00
0416b204c9
remove obsolete file
...
llvm-svn: 34506
2007-02-22 23:48:43 +00:00
e0008e23cf
Simplify lowering and selection of exception ops.
...
llvm-svn: 34488
2007-02-22 14:56:36 +00:00
3796abea0f
Support to provide exception and selector registers.
...
llvm-svn: 34482
2007-02-21 22:54:50 +00:00
18fc09723c
Add support for changes in DwarfWriter.
...
llvm-svn: 34478
2007-02-21 22:47:38 +00:00
af76e0e58f
Add TAI field for exception table section.
...
llvm-svn: 34477
2007-02-21 22:43:40 +00:00
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
...
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
da81bf4d3e
For PR1207:
...
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
9865be6d40
Added getReservedRegs().
...
llvm-svn: 34376
2007-02-17 11:06:00 +00:00
1f7d60262e
Fix ixaddrs as well, allowing ppc64 to compile to:
...
_test2:
li r2, 0
lis r3, 1
std r2, 9024(r3)
blr
instead of:
_test2:
lis r2, 1
li r3, 0
ori r2, r2, 9024
std r3, 0(r2)
blr
This implements CodeGen/PowerPC/LargeAbsoluteAddr.ll:test2
llvm-svn: 34373
2007-02-17 06:57:26 +00:00
4a9c0bb147
Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:
...
_test:
lis r2, 743
li r3, 0
stw r3, 32751(r2)
blr
instead of:
_test:
li r2, 0
stw r2, 32751(48693248)
blr
Implement support for ppc64 as well, allowing it to produce better code.
llvm-svn: 34371
2007-02-17 06:44:03 +00:00
8091f28d1a
fix incorrect encoding of vminsw.
...
llvm-svn: 34351
2007-02-16 21:20:09 +00:00
945e437c65
Generalize TargetData strings, to support more interesting forms of data.
...
Patch by Scott Michel.
llvm-svn: 34266
2007-02-14 05:52:17 +00:00
c9088b4c8e
add a note
...
llvm-svn: 34101
2007-02-09 17:38:01 +00:00
ba52b94fa2
Remove fixed item
...
llvm-svn: 34081
2007-02-09 04:19:54 +00:00
e796b6de45
Fixed comments.
...
llvm-svn: 34040
2007-02-08 06:05:08 +00:00
2aa9a42f24
Moved the MachOWriter and ELFWriter out of the Target/* files. Placed the
...
definition of it into the CodeGen library. This is so that a backend doesn't
necessarily add in these writers if it doesn't use them (like in the lli
program).
llvm-svn: 34034
2007-02-08 01:39:44 +00:00
4e8ad36338
Dead files. Functionality has been taken over by the Add*Writer functions.
...
llvm-svn: 34029
2007-02-08 01:32:51 +00:00
a883f55eca
Moved the GetTargetRelocation method from PPCMachOWriter to here. It uses
...
non-Mach-O-specific information.
llvm-svn: 33819
2007-02-03 02:41:58 +00:00
2c350921e2
Moved the GetTargetRelocation method to the PPCMachOWriterInfo object. The
...
PPCMachOWriter is now trivial.
llvm-svn: 33818
2007-02-03 02:40:57 +00:00
c3de9b4b14
Support for non-landing pad exception handling.
...
llvm-svn: 33755
2007-02-01 16:31:34 +00:00
f7937005a3
Fix CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
...
llvm-svn: 33732
2007-02-01 00:39:08 +00:00
37ebf9317b
A relatively simple PPC optimization.
...
llvm-svn: 33709
2007-01-31 19:49:20 +00:00
5301e7c605
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
...
confusion with external linkage types.
llvm-svn: 33663
2007-01-30 20:08:39 +00:00
0e083d0161
Darwin -static should codegen static ctors / dtors to .constructor / .destructor sections.
...
llvm-svn: 33657
2007-01-30 08:04:53 +00:00
3f9f250928
Only gather frame info if debug or eh.
...
llvm-svn: 33639
2007-01-29 23:20:22 +00:00
eda5997cc8
Finish off bug 680, allowing targets to custom lower frame and return
...
address nodes.
llvm-svn: 33636
2007-01-29 22:58:52 +00:00
e3b09fbbb0
We'd still like to register allocate r2 on darwin before the callee-save
...
regs.
llvm-svn: 33635
2007-01-29 22:57:48 +00:00
17f250005a
Update some of the llvm in the readme
...
llvm-svn: 33630
2007-01-29 21:21:22 +00:00
b4a2f05d1c
Landing pad-less eh for PPC.
...
llvm-svn: 33622
2007-01-29 18:51:14 +00:00
037c867b54
Propagate changes from my local tree. This patch includes:
...
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
debcb5530c
Fix a spelling error
...
llvm-svn: 33556
2007-01-26 22:40:50 +00:00
f209495e93
Handle multiple functions, properly mangle symbols, and fix support for
...
scattered relocations.
llvm-svn: 33555
2007-01-26 22:39:48 +00:00
c56315c2b5
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
...
for debugging and exception handling.
llvm-svn: 33550
2007-01-26 21:22:28 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
313c2937f0
Fix comment.
...
llvm-svn: 33508
2007-01-25 22:48:25 +00:00
5acf2fbb43
- Tell PEI that PPC will handle stack frame rounding itself.
...
- Do not round up to max. alignment of stack object if it is > stack alignment.
It will have to be handled with dynamic aligning code.
llvm-svn: 33505
2007-01-25 22:25:04 +00:00
48518548bd
Fix test/CFrontend/2007-01-24-InlineAsmCModifier.c on PPC
...
llvm-svn: 33494
2007-01-25 02:52:50 +00:00
f6c63fec92
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
...
by value so that clean up is less confusing (these vectors tend to be small.)
llvm-svn: 33488
2007-01-24 18:45:13 +00:00
06a03210af
Make ivars private and use getters. Have the MachOWriter return "Mach-O
...
Writer" for the pass name.
llvm-svn: 33483
2007-01-24 07:13:56 +00:00
40cb811cf8
Add a field for and construction of the PPCMachOWriterInfo object.
...
llvm-svn: 33480
2007-01-24 03:41:36 +00:00
56f1058309
Move the getJTRelocation method out of here.
...
llvm-svn: 33479
2007-01-24 03:40:33 +00:00
a1b7b8a485
New "TargetMachOWriterInfo" class. It holds target-specific information
...
that the MachOWriter needs in order to do its writing stuff 'n things.
llvm-svn: 33475
2007-01-24 03:36:05 +00:00
16e58be1bc
hasFP() is now a virtual method of MRegisterInfo.
...
llvm-svn: 33455
2007-01-23 00:57:47 +00:00
9f3a7eb9b2
Double and long preferred alignment set to 8 bytes.
...
llvm-svn: 33447
2007-01-22 23:11:06 +00:00
28c5b8618a
Needed to build on PPC Linux.
...
llvm-svn: 33352
2007-01-19 04:36:02 +00:00
889d934d00
move contents of PR587 to here.
...
llvm-svn: 33333
2007-01-18 07:34:57 +00:00
e750f61ac5
Have the OutputBuffer take the is64Bit and isLittleEndian booleans.
...
llvm-svn: 33316
2007-01-18 01:23:11 +00:00
c1ea85b4c4
Modify emission of jump tables on darwin to emit an extra "l" label that
...
delimits the boundaries of jump tables. This lets the linker's dead code
stripping optimization do a better job.
llvm-svn: 33315
2007-01-18 01:15:58 +00:00
cd9c1f035a
Changed to use the OutputBuffer instead of the methods in MachO and ELF
...
writers.
llvm-svn: 33311
2007-01-17 22:22:31 +00:00
38ee6519b7
Revert patch.
...
llvm-svn: 33298
2007-01-17 09:06:13 +00:00
05e5a5ee6c
Create the specified TargetObjInfo and use it.
...
llvm-svn: 33291
2007-01-17 03:51:37 +00:00
f758157385
New "TargetObjInfo" class. This holds information that the object writers will
...
use to write things to the file. It's abstract so each target should implement
its own version for each writer type.
llvm-svn: 33286
2007-01-17 03:46:30 +00:00
c7b2ab9bdf
Instead of yet another enum indicating the "assembly language flavor",
...
just use the one that's in the subtarget.
llvm-svn: 33255
2007-01-16 09:29:17 +00:00
e21237e59a
Fix for PR1095:
...
LLVM would miscompile ASM dialects when compiling for PPC. Added dialects for
the X86 and PPC backends. It defaults to "0", the first variant of a compound
inline asm expression.
llvm-svn: 33246
2007-01-16 03:42:04 +00:00
3c84b551db
add support for hidden visibility to darwin/ppc and linux/ppc targets
...
llvm-svn: 33200
2007-01-14 06:37:54 +00:00
72a56fc44c
Disable the macho writer until it is 100% functional. Enabling it when
...
broken invites bug reports.
llvm-svn: 32961
2007-01-06 22:27:58 +00:00
8bc7ddb84d
setSetCCIsExpensive is gone.
...
llvm-svn: 32941
2007-01-05 23:42:53 +00:00
74b46e8c05
Fix naming inconsistency.
...
llvm-svn: 32823
2007-01-02 21:33:40 +00:00
28663c73ef
Changes from Nick Lewycky with a simplified PPCTargetAsmInfo.
...
llvm-svn: 32735
2006-12-21 20:26:09 +00:00
4c90a6df16
Oops.
...
llvm-svn: 32724
2006-12-20 21:35:00 +00:00
c2c861d00e
Original patch was overly complicated.
...
llvm-svn: 32723
2006-12-20 21:33:34 +00:00
41621a72f5
Changes to target powerpc for non-Darwin assemblers.
...
1. Patches from Nick Lewycky.
2. Code to filter register names and print them as numeric values on
non-Darwin systems.
llvm-svn: 32721
2006-12-20 20:56:46 +00:00
1ef9cd400d
eliminate static ctors for Statistic objects.
...
llvm-svn: 32703
2006-12-19 22:59:26 +00:00
d7998d0e6d
move ExtWeakSymbols to AsmPrinter
...
llvm-svn: 32648
2006-12-18 03:37:18 +00:00
360a14be02
Apply B. Scott Michel's patch for PR1054, thanks!
...
llvm-svn: 32630
2006-12-16 20:23:42 +00:00
a0850e98ee
Patterns no longer needed due to fix in the DAG combiner.
...
llvm-svn: 32612
2006-12-15 21:39:31 +00:00
73d307d12d
Not all test cases are created equal. This fix is needed.
...
llvm-svn: 32605
2006-12-15 18:51:01 +00:00
38b1d53afe
Not needed. Misinterpreted error message from other bug (Missing load/store
...
relocations.)
llvm-svn: 32604
2006-12-15 18:45:32 +00:00
b0367c987e
Missing load/store relocations.
...
llvm-svn: 32601
2006-12-15 16:44:10 +00:00
36d826dca2
Provide 64-bit support for i64 sextload<i8>.
...
llvm-svn: 32600
2006-12-15 14:34:11 +00:00
f07cc990dd
Provide support for FP_TO_UINT.
...
llvm-svn: 32599
2006-12-15 14:32:57 +00:00
59e7a777da
Honor cpu directive, take two.
...
llvm-svn: 32492
2006-12-12 20:57:08 +00:00
8171e58bd9
Rollback changes to take a different tack.
...
llvm-svn: 32488
2006-12-12 19:26:50 +00:00
7c3cab9ddc
Honor the command line specification for machine type.
...
llvm-svn: 32483
2006-12-12 16:07:33 +00:00
095e6f3044
Reduce number of instructions to load 64-bit constants.
...
llvm-svn: 32481
2006-12-12 13:23:43 +00:00
f4646a7e54
Another step forward in PPC64 JIT support: we now no-longer need stubs
...
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
llvm-svn: 32451
2006-12-11 23:22:45 +00:00
b1f3157638
getInstrItineraryData shouldn't copy the itineraries
...
llvm-svn: 32448
2006-12-11 21:42:55 +00:00
2b136a73bd
Missing opcode.
...
llvm-svn: 32439
2006-12-11 18:45:56 +00:00
e95909a4ef
Layout proper frame for ppc64.
...
llvm-svn: 32436
2006-12-11 18:10:54 +00:00
e8da58b3f9
Properly mangles symbol table names
...
Supports constant pools
Supports relocations to jump tables
Supports relocations within the data segment (global = address of global)
Allocates memory in a non-hacky for all non-code objects.
llvm-svn: 32430
2006-12-11 02:20:45 +00:00
3b7c257cae
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
6af2220815
Reverting until finding the cause of secondary bugs.
...
llvm-svn: 32413
2006-12-10 13:09:42 +00:00
04c832d4ab
__PPC64CompilationCallback code was allowing registers to be clobbered by stub.
...
llvm-svn: 32412
2006-12-10 12:13:31 +00:00
09fecf9a47
this is an initial patch to switch the ppc64 jit over to working in PIC mode,
...
which allows the code to be above the 2G marker. We still need to JIT emit
dyld stubs to support external, weak, common, etc globals, but that will
happen tomorrow.
llvm-svn: 32348
2006-12-08 04:54:03 +00:00
13535c2d93
fix incorrect encoding of rldicr, used by ppc64 function stubs, etc.
...
llvm-svn: 32341
2006-12-07 23:44:07 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
a9a817dc7d
fix CodeGen/PowerPC/2006-12-07-LargeAlloca.ll on ppc64
...
llvm-svn: 32331
2006-12-07 22:15:58 +00:00
d8e7451dc3
Fix i64 uint_to_fp on ppc64
...
llvm-svn: 32297
2006-12-07 01:24:16 +00:00
43c0eb839c
implement sextinreg i8->i64 and i16->i64
...
llvm-svn: 32293
2006-12-06 21:46:13 +00:00
9472eb83c3
fix another sradi encoding bug. This fixes Olden/health with the ppc64 jit.
...
llvm-svn: 32291
2006-12-06 21:35:10 +00:00
aeadac88ea
fix the jit encoding of sradi, simplify the MDForm1 description.
...
llvm-svn: 32285
2006-12-06 20:02:54 +00:00
1fa392dbfa
add relocation support for ppc64 branches.
...
llvm-svn: 32284
2006-12-06 19:40:04 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
527c12f8e6
Make it easier for gdb to find the return address.
...
llvm-svn: 32277
2006-12-06 17:42:06 +00:00
e4f4d048dd
Restoration of the stack pointer after a deallocation of a alloca was not
...
updating the SP link.
llvm-svn: 32202
2006-12-04 22:04:42 +00:00
022030a425
Add weak reference directive.
...
llvm-svn: 32091
2006-12-01 20:47:11 +00:00
b689d32b20
Copy and paste error. An initialized global cannot be a weak reference.
...
llvm-svn: 32075
2006-12-01 17:39:22 +00:00
1b0bc794e6
1. In ppc64 mode we need only use one GPR.
...
2. Float values need to be promoted to double when they are vararg.
llvm-svn: 32074
2006-12-01 16:30:47 +00:00
311622f912
ExternalWeak case in wrong location.
...
llvm-svn: 32073
2006-12-01 14:37:39 +00:00
5fb2c76d59
A initialized global variable cannot be extern weak. However, if a global value's initializer is itself a external weak symbol, emit the weak reference.
...
llvm-svn: 32069
2006-12-01 09:13:26 +00:00
fa54c0b6fb
Darwin PPC external weak linkage support.
...
llvm-svn: 32068
2006-12-01 07:56:37 +00:00
09ed0ff2ac
Fix the CodeGen/PowerPC/vec_constants.ll regression.
...
llvm-svn: 32057
2006-12-01 01:45:39 +00:00
aafeaef8c8
MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor
...
llvm-svn: 32034
2006-11-30 07:12:03 +00:00
2f648fc55d
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
...
created intrinsics have the right integer types. This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll
llvm-svn: 32024
2006-11-29 19:58:49 +00:00
152671f0bf
Offset for load of 32-bit arg in 64-bit world was incorrect.
...
llvm-svn: 32019
2006-11-29 13:37:09 +00:00
40182179b6
Remove debug code.
...
llvm-svn: 31970
2006-11-28 18:27:02 +00:00
ec05b046c7
Prime text sections to improve branch locality in large object files.
...
llvm-svn: 31969
2006-11-28 18:21:52 +00:00
f4e2e009d9
32-bit int space was not accounted for properly in lowerCall.
...
llvm-svn: 31966
2006-11-28 14:53:52 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
6968c497de
Add newline at end of file.
...
llvm-svn: 31902
2006-11-25 05:41:02 +00:00
ec5dbccdcf
in ppc64-mode, don't allocate the 32-bit version of r13 either.
...
llvm-svn: 31884
2006-11-20 20:48:05 +00:00
ac36360348
r13 is the thread pointer on darwin/ppc64, don't allocate it.
...
llvm-svn: 31882
2006-11-20 19:33:51 +00:00
2cca385fbb
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
...
Also, valist should create a pointer RC reg class value, not a GPRC value.
llvm-svn: 31840
2006-11-18 01:57:19 +00:00
572e238c14
make sure to safe LR8 in the right stack slot for PPC64
...
llvm-svn: 31839
2006-11-18 01:34:43 +00:00
9ca15c8914
Pretty print 'rldicr r2, r2, 2, 61' as 'sldi r2, r2, 2'.
...
llvm-svn: 31838
2006-11-18 01:23:56 +00:00
542dfd5510
Rewrite the branch selector to be correct in the face of large functions.
...
The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model. This fixes assembler errors when compiling 403.gcc with
tail merging enabled.
Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion. Only if branches need expansion are instructions rewritten
and created. This should make branch select faster, and eliminates the
Bxx instructions from the .td file.
llvm-svn: 31837
2006-11-18 00:32:03 +00:00
33fc1d45e5
add encoding for BCC, after finally wrestling strange ppc/tblgen endianness
...
issues to the ground.
llvm-svn: 31836
2006-11-17 23:53:28 +00:00
be9377a1e3
convert PPC::BCC to use the 'pred' operand instead of separate predicate
...
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
llvm-svn: 31835
2006-11-17 22:37:34 +00:00
e0263794f4
rename PPC::COND_BRANCH to PPC::BCC
...
llvm-svn: 31834
2006-11-17 22:14:47 +00:00
8c6a41ea12
start using PPC predicates more consistently.
...
llvm-svn: 31833
2006-11-17 22:10:59 +00:00
73106b5e2a
Assert unhandled case.
...
llvm-svn: 31828
2006-11-17 18:49:39 +00:00
1823346b3e
1. Ignore the -disable-fp-elim when the routine is a leaf.
...
2. Offsets on 64-bit stores are still in bytes.
llvm-svn: 31824
2006-11-17 16:09:31 +00:00
91542a4f2d
Typo. Fix the nightly tests.
...
llvm-svn: 31823
2006-11-17 14:06:41 +00:00
3b7261b18e
implement a todo: change a map into a vector
...
llvm-svn: 31805
2006-11-17 01:52:23 +00:00
be1a4d80b3
fix typo
...
llvm-svn: 31799
2006-11-17 00:49:36 +00:00
a715288b40
implicit_def_vrrc doesn't generate code.
...
llvm-svn: 31797
2006-11-16 23:49:52 +00:00
48850c10c0
This is a general clean up of the PowerPC ABI. Address several problems and
...
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
llvm-svn: 31792
2006-11-16 22:43:37 +00:00
30055b9208
fix a regression that I introduced. stdu should scale the offset by 4
...
before printing it.
llvm-svn: 31791
2006-11-16 21:45:30 +00:00
96d7386006
add a statistic
...
llvm-svn: 31785
2006-11-16 18:13:49 +00:00
a7ff5162b0
fix broken encoding
...
llvm-svn: 31778
2006-11-16 01:01:28 +00:00
e742d9a4b7
add ppc64 r+i stores with update.
...
llvm-svn: 31776
2006-11-16 00:57:19 +00:00
6f5840c409
add patterns for ppc32 preinc stores. ppc64 next.
...
llvm-svn: 31775
2006-11-16 00:41:37 +00:00
3a494989a6
switch these back to the 'bad old way'
...
llvm-svn: 31774
2006-11-16 00:33:34 +00:00
b4e911d15a
Fix ppc64 epilog bug.
...
llvm-svn: 31771
2006-11-15 23:35:30 +00:00
5771156be0
Stop using isTwoAddress, switching to operand constraints instead.
...
Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).
llvm-svn: 31770
2006-11-15 23:24:18 +00:00
dc2c8748a7
Properly transfer kill / dead info.
...
llvm-svn: 31765
2006-11-15 20:58:11 +00:00
474b5b7c95
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
...
addrmodes.
llvm-svn: 31757
2006-11-15 19:55:13 +00:00
0e117c7e9d
Fix the PPC regressions last night
...
llvm-svn: 31752
2006-11-15 17:40:51 +00:00
1396961e85
Switch loads over to use memri as the operand instead of a reg/imm operand
...
pair for cleanliness. Add instructions for PPC32 preinc-stores with commented
out patterns. More improvement is needed to enable the patterns, but we're
getting close.
llvm-svn: 31749
2006-11-15 02:43:19 +00:00
e79a451475
group load and store instructions together. No functionality change.
...
llvm-svn: 31736
2006-11-14 19:19:53 +00:00
44dbdbe5cf
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
...
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
llvm-svn: 31734
2006-11-14 18:44:47 +00:00
b542925b22
remove a ton of custom selection logic no longer needed
...
llvm-svn: 31733
2006-11-14 18:43:11 +00:00
97ff46b3cc
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
...
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
llvm-svn: 31725
2006-11-14 05:28:08 +00:00
683712583a
minor tweaks, reject vector preinc.
...
llvm-svn: 31717
2006-11-14 01:38:31 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
1121e50f7e
teach the g5 hazard recognizer about update loads. This fixes
...
Ptrdist/anagram among others.
llvm-svn: 31708
2006-11-13 20:11:06 +00:00
1dfc6110ff
Make sure stack link is set in 64-bit.
...
llvm-svn: 31690
2006-11-11 22:22:07 +00:00
0d550cc56c
implement proper PPC64 prolog/epilog codegen.
...
llvm-svn: 31684
2006-11-11 19:05:28 +00:00
66c502b54a
Running with frame pointers prevented debugging, external probes and
...
potentially some system calls/exception handling from working. TOS must always
link to previous frame. This is a short term workaround until alloca scheme is
reworked.
llvm-svn: 31677
2006-11-11 10:21:58 +00:00
c5102bfc7c
allow the offset of a preinc'd load to be the low-part of a global. This
...
produces this clever code:
_millisecs:
lis r2, ha16(_Time.1182)
lwzu r3, lo16(_Time.1182)(r2)
lwz r2, 4(r2)
addic r4, r2, 1
addze r3, r3
blr
instead of this:
_millisecs:
lis r2, ha16(_Time.1182)
la r3, lo16(_Time.1182)(r2)
lwz r2, lo16(_Time.1182)(r2)
lwz r3, 4(r3)
addic r4, r3, 1
addze r3, r2
blr
for:
long %millisecs() {
%tmp = load long* %Time.1182 ; <long> [#uses=1]
%tmp1 = add long %tmp, 1 ; <long> [#uses=1]
ret long %tmp1
}
llvm-svn: 31673
2006-11-11 04:53:30 +00:00
2ff632c54b
Mark operands as symbol lo instead of imm32 so that they print lo(x) around
...
globals.
llvm-svn: 31672
2006-11-11 04:51:36 +00:00
b314b155ed
ppc64 doesn't have lwau, don't attempt to form it.
...
llvm-svn: 31656
2006-11-11 00:08:42 +00:00
c9fa36d706
implement preinc support for r+i loads on ppc64
...
llvm-svn: 31654
2006-11-10 23:58:45 +00:00
6c8656a6b1
dform 8/9 are identical to dform 1
...
llvm-svn: 31637
2006-11-10 17:51:02 +00:00
ce6455489a
add an initial cut at preinc loads for ppc32. This is broken for ppc64
...
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
llvm-svn: 31621
2006-11-10 02:08:47 +00:00
cd436327f1
add note about ugly codegen with preinc
...
llvm-svn: 31617
2006-11-10 01:33:53 +00:00
36a8fbf771
PPC supports i32 / i64 pre-inc load / store.
...
llvm-svn: 31599
2006-11-09 19:11:50 +00:00
b15000736c
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
6cd0909da7
Match tblegen changes.
...
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
a801fcedd3
Refactor all the addressing mode selection stuff into the isel lowering
...
class, where it can be used for preinc formation.
llvm-svn: 31536
2006-11-08 02:15:41 +00:00
6a5a4f85d3
correct the (currently unused) pattern for lwzu.
...
llvm-svn: 31535
2006-11-08 02:13:12 +00:00
be7033b346
add a note from viterbi
...
llvm-svn: 31506
2006-11-07 18:30:21 +00:00
d94477f6c9
fix encoding of BLR
...
llvm-svn: 31485
2006-11-07 01:51:50 +00:00
2959789c92
encode BLR predicate info for the JIT
...
llvm-svn: 31450
2006-11-04 05:42:48 +00:00
6be726048e
Go through all kinds of trouble to mark 'blr' as having a predicate operand
...
that takes a register and condition code. Print these pieces of BLR the
right way, even though it is currently set to 'always'.
Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.
llvm-svn: 31449
2006-11-04 05:27:39 +00:00
c8a68d08c3
Describe PPC predicates, which are a pair of CR# and condition.
...
llvm-svn: 31438
2006-11-03 23:53:25 +00:00
895d199348
remove dead vars
...
llvm-svn: 31433
2006-11-03 23:46:45 +00:00
2de0910a1b
fix a bug reid noticed
...
llvm-svn: 31385
2006-11-02 23:39:53 +00:00
de46e48420
For PR786:
...
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
584a11ae22
Implement the getRegForInlineAsmConstraint method for PPC. With recent
...
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
llvm-svn: 31367
2006-11-02 01:44:04 +00:00
8c6949e5b2
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
aa4c0f9374
1. Clean up code due to changes in SwitchTo*Section(2)
...
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
llvm-svn: 31311
2006-10-31 08:31:24 +00:00
3e36e07db2
fix miscompilation of llvm.isunordered, where we branched on the opposite
...
condition. This fixes miscompilation of Olden/bh and many others.
llvm-svn: 31301
2006-10-30 23:02:25 +00:00
0d41d19427
All targets expand BR_JT for now.
...
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
113f7470e6
implement the BlockHasNoFallThrough hook
...
llvm-svn: 31264
2006-10-28 17:35:02 +00:00
ae8c29a7d3
Doh. Must check if GV is constant first before putting it in .cstring.
...
llvm-svn: 31253
2006-10-28 05:56:51 +00:00
acc6b37d0d
don't dist internal readme's
...
llvm-svn: 31246
2006-10-28 00:49:54 +00:00
28174f5a3a
this doesn't occur any more in mason
...
llvm-svn: 31236
2006-10-27 22:02:19 +00:00
4c0cc53da1
the code in question is now:
...
cmpw cr0, r7, r3
ble cr0, LBB1_5 ;bb25
LBB1_8: ;bb17
cmpw cr0, r8, r5
bgt cr0, LBB1_2 ;bb
which is just as good as crnand.
llvm-svn: 31235
2006-10-27 22:00:55 +00:00
e1e06c2de8
Place cstrings in .cstring section.
...
llvm-svn: 31207
2006-10-26 21:48:57 +00:00
71b99297aa
Move getPreferredAlignmentLog from AsmPrinter to TargetData
...
llvm-svn: 31171
2006-10-24 20:32:14 +00:00
d43e8a7429
Add intrinsics for the rest of the DCB* instructions.
...
llvm-svn: 31148
2006-10-24 01:08:42 +00:00
23f22de26f
Implement support for branch reversal, fix a bug in branch analysis.
...
This provides stuff like:
cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)
which is particularly good for dispatch group formation.
llvm-svn: 31101
2006-10-21 06:03:11 +00:00
d881660366
Simplify code, no functionality change
...
llvm-svn: 31097
2006-10-21 05:42:09 +00:00
94e04442eb
implement support for inserting a cond branch
...
llvm-svn: 31096
2006-10-21 05:36:13 +00:00
454436dcc5
set the ppc64 stack pointer right, dynamic alloca now works for ppc64
...
llvm-svn: 31028
2006-10-18 01:20:43 +00:00
ab4df83426
Expand alloca for ppc64
...
llvm-svn: 31027
2006-10-18 01:18:48 +00:00
0408e5b7ce
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
...
llvm-svn: 31024
2006-10-17 22:41:45 +00:00
a61f0105bd
add support for inserting an uncond branch
...
llvm-svn: 31003
2006-10-17 18:06:55 +00:00
2794184191
Use S_debug for dwarf info.
...
llvm-svn: 30994
2006-10-17 11:30:57 +00:00
a47294ed7a
implement branch inspection/modification methods.
...
llvm-svn: 30946
2006-10-13 21:21:17 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
be131662c3
add note
...
llvm-svn: 30937
2006-10-13 20:20:58 +00:00
cf56917053
set isBarrier correctly
...
llvm-svn: 30936
2006-10-13 19:10:34 +00:00
4dc4f30a48
Correctly handle instruction separators.
...
llvm-svn: 30935
2006-10-13 17:56:02 +00:00
7374bc0577
mark adjcallstack up/down as clobbering and using the SP
...
llvm-svn: 30908
2006-10-12 17:56:34 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
8cfd10eff3
Don't bother setting JumpTableTextSection, it is about to disappear
...
llvm-svn: 30745
2006-10-05 03:13:59 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
028d663ee6
Move getSectionForFunction to AsmPrinter, change it to return a string.
...
llvm-svn: 30735
2006-10-05 02:42:20 +00:00
0d236450aa
implement DarwinTargetAsmInfo::getSectionForFunction, use it when outputting
...
function bodies
llvm-svn: 30733
2006-10-05 00:35:50 +00:00
41e22a5419
emit jump table before debug info
...
llvm-svn: 30731
2006-10-05 00:26:05 +00:00
aad26a19f0
Always emit the jump table after the function so it's part of the same 'atom'
...
as the function body.
llvm-svn: 30730
2006-10-05 00:24:46 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
d32cb5ee7f
wrap long lines
...
llvm-svn: 30662
2006-09-28 23:32:43 +00:00
78370606d0
Shift amounts are always 32-bits, even in 64-bit mode. This fixes
...
CodeGen/PowerPC/2006-09-28-shift_64.ll
llvm-svn: 30652
2006-09-28 20:48:45 +00:00
67f8cc51f4
Use abstract private/comment directives, to increase portability to ppc/linux
...
llvm-svn: 30621
2006-09-27 02:55:21 +00:00
ad4e7eb59e
Compile:
...
int x __attribute__((used));
to:
.data
.comm _x,4 ; 'x'
.no_dead_strip _x
on both x86 and ppc darwin targets.
llvm-svn: 30605
2006-09-26 03:39:53 +00:00
d31efd190f
Fold AND and ROTL more often
...
llvm-svn: 30577
2006-09-22 05:01:56 +00:00
a81a75c390
The DarwinAsmPrinter need not check for isDarwin. createPPCAsmPrinterPass
...
should create the right asmprinter subclass.
llvm-svn: 30542
2006-09-20 17:12:19 +00:00
8597a2fc4e
Wrap some darwin'isms with isDarwin checks.
...
llvm-svn: 30541
2006-09-20 17:07:15 +00:00
fba9e8f422
item done
...
llvm-svn: 30518
2006-09-20 06:41:56 +00:00
f62f090ea1
This is already done
...
llvm-svn: 30512
2006-09-20 04:59:33 +00:00
da9b1a9322
Improve PPC64 equality comparisons like PPC32 comparisons.
...
llvm-svn: 30510
2006-09-20 04:33:27 +00:00
aa3926b7ea
Two improvements:
...
1. Codegen this comparison:
if (X == 0x8000)
as:
cmplwi cr0, r3, 32768
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 0
ori r2, r2, 32768
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
2. Codegen this comparison:
if (X == 0x12345678)
as:
xoris r2, r3, 4660
cmplwi cr0, r2, 22136
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 4660
ori r2, r2, 22136
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
llvm-svn: 30509
2006-09-20 04:25:47 +00:00
ab33d350a7
Add a note that we should match rlwnm better
...
llvm-svn: 30508
2006-09-20 03:59:25 +00:00
601b86513d
Legalize is no longer limited to cleverness with just constant shift amounts.
...
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
llvm-svn: 30507
2006-09-20 03:47:40 +00:00
3c48ea54ee
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
...
like:
long long test(long long X, int Y) {
return 1ULL << Y;
}
long long test2(long long X, int Y) {
return -1LL << Y;
}
which we used to compile to:
_test:
li r2, 1
subfic r3, r5, 32
li r4, 0
addi r6, r5, -32
srw r3, r2, r3
slw r4, r4, r5
slw r6, r2, r6
or r3, r4, r3
slw r4, r2, r5
or r3, r3, r6
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
Now we produce:
_test:
li r2, 1
addi r3, r5, -32
subfic r4, r5, 32
slw r3, r2, r3
srw r4, r2, r4
or r3, r4, r3
slw r4, r2, r5
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
llvm-svn: 30479
2006-09-19 05:22:59 +00:00
2aa98e0363
add a note
...
llvm-svn: 30377
2006-09-14 20:56:30 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
69df6132d7
First pass at supporting relocations. Relocations are written correctly to
...
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
2006-09-08 22:42:09 +00:00
177405376c
Missing tab
...
llvm-svn: 30188
2006-09-08 13:06:56 +00:00
c9db83306f
We actually do support object file writing, so don't return true (error)
...
llvm-svn: 30173
2006-09-08 03:42:15 +00:00
ae92ce8798
1. Remove condition on delete.
...
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
2006-09-07 23:39:26 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
0e83541f8b
Break out target asm info into separate files.
...
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
12e97307a1
Completely rearchitect the interface between targets and the pass manager.
...
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
llvm-svn: 30081
2006-09-04 04:14:57 +00:00
0fc4541c67
Simplify target construction.
...
llvm-svn: 30070
2006-09-03 18:44:02 +00:00
2eebe8b05e
Handle callee saved registers in dwarf frame info (lead up to exception
...
handling.)
llvm-svn: 29954
2006-08-29 16:24:26 +00:00
18f0329cfc
Make ppc64 jit kinda work right. About 2/3 of Olden passes with this,
...
there are clearly some encoding bugs lurking in there somewhere.
llvm-svn: 29949
2006-08-29 02:30:59 +00:00
e7141c8be6
For PR387:
...
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.
llvm-svn: 29934
2006-08-28 01:02:49 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
c3acfc0b10
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
...
SDOperand arguments. Use the variants which take an array and number instead.
llvm-svn: 29907
2006-08-27 08:14:06 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
61413a3d72
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
ab8297f92d
Match tblgen changes.
...
llvm-svn: 29895
2006-08-26 01:07:58 +00:00
1b200574ad
Add a comment.
...
llvm-svn: 29889
2006-08-25 23:29:06 +00:00
d7572fb234
Encode pc-relative conditional branch offset as pc+(num of bytes / 4). The
...
asm printer will print it as offset*4. e.g. bne cr0, $+8.
The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.
llvm-svn: 29885
2006-08-25 21:54:44 +00:00
d51ce619c3
Fix some comments.
...
llvm-svn: 29880
2006-08-25 19:40:59 +00:00
3cb3921a60
Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it
...
does emit linkable .o files in very simple cases.
llvm-svn: 29850
2006-08-23 21:08:52 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
...
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
bc485fdc4c
Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code.
...
llvm-svn: 29715
2006-08-15 23:48:22 +00:00
984c1a4a8f
Emit .set directives for jump table entries when possible, which reduces
...
the number of relocations in object files, shrinkifying them.
llvm-svn: 29650
2006-08-12 21:29:52 +00:00
095e4ad2ea
Fix a bug in a recent refactoring that broke a bunch of stuff.
...
llvm-svn: 29649
2006-08-12 07:20:05 +00:00
ed728e8dc9
Eliminate use of getNode that takes a vector.
...
llvm-svn: 29614
2006-08-11 17:38:39 +00:00
d66f14e846
Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector.
...
llvm-svn: 29609
2006-08-11 17:18:05 +00:00
66f1fbaaad
Fix miscompilation of float vector returns. Compile code to this:
...
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
blr
instead of:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
*** vor f1, v2, v2
blr
llvm-svn: 29607
2006-08-11 16:47:32 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
b9d34bd098
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
8298265042
Fix some ppc64 issues with vector code.
...
llvm-svn: 29384
2006-07-28 16:45:47 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
78bf1074fc
Resolve BB references with relocation.
...
llvm-svn: 29351
2006-07-27 18:21:10 +00:00
7ec7b467df
synchronizeICache removeed from TargetJITInfo.
...
llvm-svn: 29348
2006-07-27 17:33:48 +00:00
f300896420
Remove NodeDepth
...
llvm-svn: 29338
2006-07-27 06:40:15 +00:00
787565024a
Support jump tables when in PIC relocation model
...
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
9e56e5c003
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
...
llvm-svn: 29307
2006-07-26 21:12:04 +00:00
f6acb34d23
- Refactor the code that resolve basic block references to a TargetJITInfo
...
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
of code is emitted to flush the icache. This ensures correct execution
on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.
llvm-svn: 29276
2006-07-25 20:40:54 +00:00
4f8eb5ccaf
bswapped load/store instructions are only availble in indexed addressing form.
...
As such, use xoaddr (indexed only), not xaddr for address selection.
This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.
llvm-svn: 29208
2006-07-19 17:15:36 +00:00
b00b6c2e86
Make the implicit def instructions look like other instrs.
...
llvm-svn: 29174
2006-07-18 16:33:26 +00:00
e1758d4cef
Remove what little AIX support we have. It has never been tested and isn't
...
complete.
llvm-svn: 29156
2006-07-15 01:24:23 +00:00
96aecb5d76
Add missing PPC64 extload/truncstores
...
llvm-svn: 29140
2006-07-14 04:42:02 +00:00
950dffaed6
Add a note
...
llvm-svn: 29139
2006-07-14 04:07:29 +00:00
077b86a078
Another fix in the rotate encodings, needed when the first two operands are not
...
the same.
llvm-svn: 29136
2006-07-13 21:52:41 +00:00
b42a945fd2
Print negative immediates as negative values instead of large constants
...
when using the immshifted addressing mode.
llvm-svn: 29130
2006-07-12 23:24:02 +00:00
dd57ac4871
Fix encoding of rotates, such as rldicl
...
llvm-svn: 29128
2006-07-12 22:08:13 +00:00
5b17dee741
Implement PPC64 relocations types
...
llvm-svn: 29125
2006-07-12 21:23:20 +00:00
1ec5e73b32
An overaggressive #ifdef allows a function to fall off the bottom of the
...
function instead of returning a value. This sometimes allowed the ppc32 jit
to be used in 64-bit mode.
llvm-svn: 29123
2006-07-12 20:42:10 +00:00
6e662083d9
The PPC64 JIT needs register numbers to encode instructions.
...
llvm-svn: 29114
2006-07-11 20:53:55 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
71227c23b1
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
...
llvm-svn: 29096
2006-07-11 00:48:23 +00:00
a7976d329e
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
...
into i16/i32 load/stores.
llvm-svn: 29089
2006-07-10 20:56:58 +00:00
59b6e8a683
Undisable ppc64 jit
...
llvm-svn: 29011
2006-07-06 17:10:42 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
...
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
2f8c2d8ef2
shrink libllvmgcc.dylib another 25K
...
llvm-svn: 28971
2006-06-28 22:00:36 +00:00
ca9c488528
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
...
llvm-svn: 28944
2006-06-27 21:08:52 +00:00
f882c54505
Fix ppc64 jump tables
...
llvm-svn: 28941
2006-06-27 20:46:17 +00:00
82ab3e21b1
Print stubs for external globals right.
...
llvm-svn: 28936
2006-06-27 20:20:53 +00:00
8aed3cc46b
Implement 64-bit select, bswap, etc.
...
llvm-svn: 28935
2006-06-27 20:14:52 +00:00
a2af3f47ea
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
...
and the data
llvm-svn: 28934
2006-06-27 20:07:26 +00:00
db9a95b775
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
...
the offset two bits to the left.
llvm-svn: 28933
2006-06-27 18:55:49 +00:00
a07410c95b
PPC doesn't have bit converts to/from i64
...
llvm-svn: 28932
2006-06-27 18:40:08 +00:00
3b5873456e
Add 64-bit MTCTR so that indirect calls work.
...
llvm-svn: 28931
2006-06-27 18:36:44 +00:00
e27d51e0d8
Fix an incorrect store pattern. This fixes em3d.
...
llvm-svn: 28930
2006-06-27 18:22:50 +00:00
d48ce27532
Implement 64-bit undef, sub, shl/shr, srem/urem
...
llvm-svn: 28929
2006-06-27 18:18:41 +00:00
cb5a84f446
Use i32 for shift amounts instead of i64. This gets bisort working.
...
llvm-svn: 28927
2006-06-27 17:34:57 +00:00
f7fd88356a
Add zextload from i32 -> i64, with this, perimeter works.
...
llvm-svn: 28926
2006-06-27 17:30:08 +00:00
1df0839067
Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in
...
ppc64 mode!
llvm-svn: 28923
2006-06-27 01:02:25 +00:00
9a40cca40f
Fix variable shadowing issue
...
llvm-svn: 28922
2006-06-27 00:10:13 +00:00
97b3da1519
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
...
doesn't work right).
llvm-svn: 28921
2006-06-27 00:04:13 +00:00
7ecbd301b1
Rearrange compares, add ADDI8, add sext from 32-to-64 bit register
...
llvm-svn: 28920
2006-06-26 23:53:10 +00:00
ec78cade34
Improve PPC64 calling convention support
...
llvm-svn: 28919
2006-06-26 22:48:35 +00:00
b6a65f4661
Remove two more definitions
...
llvm-svn: 28918
2006-06-26 22:47:37 +00:00
86e6046515
remove two unused instructions.
...
llvm-svn: 28917
2006-06-26 22:44:13 +00:00
a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
dc38e6f322
Correct returns of 64-bit values, though they seemed to work before...
...
llvm-svn: 28892
2006-06-21 00:34:03 +00:00
1f1b096142
Make these predicates correct in 64-bit mode too.
...
llvm-svn: 28890
2006-06-20 23:21:20 +00:00
52a956da52
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
...
llvm-svn: 28889
2006-06-20 23:18:58 +00:00
5705d4d519
remove unused flag
...
llvm-svn: 28888
2006-06-20 23:15:07 +00:00
9d65f3507e
add some logical ops
...
llvm-svn: 28887
2006-06-20 23:11:59 +00:00
7a856a6d88
remove some unused patterns
...
llvm-svn: 28886
2006-06-20 23:11:36 +00:00
d881f8257b
Add some more immediate patterns. This allows us to compile:
...
void test6() {
Y = 0xABCD0123BCDE4567;
}
into:
_test6:
lis r2, -21555
lis r3, ha16(_Y)
ori r2, r2, 291
rldicr r2, r2, 32, 31
oris r2, r2, 48350
ori r2, r2, 17767
std r2, lo16(_Y)(r3)
blr
llvm-svn: 28885
2006-06-20 23:03:01 +00:00
9834ad2fc6
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
...
set, so disable the pattern in that case.
llvm-svn: 28884
2006-06-20 22:38:59 +00:00
7e742e46ac
Add some 64-bit logical ops.
...
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
llvm-svn: 28883
2006-06-20 22:34:10 +00:00
d6e160d14d
64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis.
...
llvm-svn: 28880
2006-06-20 21:39:30 +00:00
2d4e8f7e86
Add some patterns for globals, so we can now compile this:
...
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
llvm-svn: 28879
2006-06-20 21:23:06 +00:00
868a75bec6
Remove some now-unneeded casts from instruction patterns. With the casts
...
removed, tblgen produces identical output to with them in.
llvm-svn: 28867
2006-06-20 00:39:56 +00:00
94d18df658
Add some patterns for ppc64
...
llvm-svn: 28866
2006-06-20 00:38:36 +00:00
49cadab385
Implement the getPointerRegClass method, which is required for the ptr_rc
...
magic to work.
llvm-svn: 28847
2006-06-17 00:01:04 +00:00
638ee4ee15
Upgrade some load/store instructions to use the proper addressing mode stuff.
...
llvm-svn: 28841
2006-06-16 21:29:41 +00:00
e8fe5e2bf4
In 64-bit mode, addr mode operands use G8RC instead of GPRC.
...
llvm-svn: 28840
2006-06-16 21:29:03 +00:00
a5190ae7a9
fix some assumptions that pointers can only be 32-bits. With this, we can
...
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
llvm-svn: 28839
2006-06-16 21:01:35 +00:00
b429983988
Split 64-bit instructions out into a separate .td file
...
llvm-svn: 28838
2006-06-16 20:22:01 +00:00
61d703183e
Force 64-bit register availability in 64-bit mode. For real.
...
llvm-svn: 28837
2006-06-16 20:05:06 +00:00
a7d9db2fa5
Remove the -darwin and -aix llc options, inferring darwinism and aixism from
...
the target triple & subtarget info. woo.
llvm-svn: 28835
2006-06-16 18:50:48 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
...
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
16682fff2b
Document the subtarget features better, make sure that 64-bit mode, 64-bit
...
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
llvm-svn: 28825
2006-06-16 17:50:12 +00:00
a35f306740
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
...
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
2006-06-16 17:34:12 +00:00
0c4aa14deb
First baby step towards ppc64 support. This adds a new -march=ppc64 backend
...
that is currently just like ppc32 :)
llvm-svn: 28813
2006-06-16 01:37:27 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
94bb93f8f7
Type of extract_element index operand should be iPTR.
...
llvm-svn: 28797
2006-06-15 08:18:06 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
ac59ab515a
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
...
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
llvm-svn: 28761
2006-06-12 23:59:16 +00:00
6b043a24a1
Fix spilling and reloading of CR regs to reload the right values. This fixes
...
Olden/power (and probably others) with -regalloc=local.
llvm-svn: 28760
2006-06-12 21:50:57 +00:00
b055c8737f
Work around a nasty tblgen bug where it doesn't add operands for varargs
...
nodes correctly.
llvm-svn: 28745
2006-06-10 01:15:02 +00:00
006b2c6ab9
Fix a problem exposed by the local allocator. CALL instructions are not marked
...
as using incoming argument registers, so the local allocator would clobber them
between their set and use. To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.
llvm-svn: 28744
2006-06-10 01:14:28 +00:00
c8587d4b81
Add PowerPC intrinsics to support dcbz[l]
...
llvm-svn: 28696
2006-06-06 21:29:23 +00:00
4442a70b3a
Silence -pedantic warning
...
llvm-svn: 28633
2006-06-01 17:17:06 +00:00
b9342afa56
Always reserve space for 8 spilled GPRs. GCC apparently assumes that this
...
space will be available, even if the callee isn't varargs.
llvm-svn: 28571
2006-05-30 21:21:04 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
1fbb0d38c7
Fix build failure of povray
...
llvm-svn: 28473
2006-05-25 18:06:16 +00:00
630bbcef8d
Fix Benchmarks/MallocBench/cfrac
...
llvm-svn: 28471
2006-05-25 16:54:16 +00:00
c2cd473d9b
CALL node change (arg / sign pairs instead of just arguments).
...
llvm-svn: 28462
2006-05-25 00:57:32 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
...
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
33165c246c
Fix CodeGen/Generic/vector.ll:test_div with altivec.
...
llvm-svn: 28445
2006-05-24 00:15:25 +00:00
b56d22c2f6
Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
...
change. This fixes PowerPC/fnegsel.ll.
llvm-svn: 28443
2006-05-24 00:06:44 +00:00
80b1b4d41e
Make TargetData strings less redundant.
...
llvm-svn: 28423
2006-05-20 23:28:54 +00:00
88812b5c0a
Make all of the TargetMachine subclasses use the new string TargetData methods.
...
This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
...
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
6353807fdc
Add a note about a note
...
llvm-svn: 28355
2006-05-17 19:02:25 +00:00
eb755fc1b3
Make PPC call lowering more aggressive, making the isel matching code simple
...
enough to be autogenerated.
llvm-svn: 28354
2006-05-17 19:00:46 +00:00
b1e9e37c58
Switch PPC over to a call-selection model where the lowering code creates
...
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
llvm-svn: 28346
2006-05-17 06:01:33 +00:00
b7552a88d6
3 changes, 2 of which are cleanup one of which changes codegen:
...
1. Rearrange code a bit so that the special case doesn't require indenting lots
of code.
2. Add comments describing PPC calling convention.
3. Only round up to 56-bytes of stack space for an outgoing call if the callee
is varargs. This saves a bit of stack space.
llvm-svn: 28342
2006-05-17 00:15:40 +00:00
f058f5aef1
implement passing/returning vector regs to calls, at least non-varargs calls.
...
llvm-svn: 28341
2006-05-16 23:54:25 +00:00
aa40ec1b32
Instead of implementing LowerCallTo directly, let the default impl produce an
...
ISD::CALL node, then custom lower that. This means that we only have to handle
LEGAL call operands/results, not every possible type. This allows us to
simplify the call code, shrinking it by about 1/3.
llvm-svn: 28339
2006-05-16 22:56:08 +00:00
26e2fcd8b1
Simplify the argument counting logic by only incrementing the index.
...
llvm-svn: 28335
2006-05-16 18:58:15 +00:00
76c47b50e7
Simplify the dead argument handling code.
...
llvm-svn: 28334
2006-05-16 18:54:32 +00:00
318f0d2122
Vector args passed in registers don't reserve stack space.
...
llvm-svn: 28333
2006-05-16 18:51:52 +00:00
4302e8fb67
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
...
handling. This makes the lower argument code significantly simpler (we
only need to handle legal argument types).
Incidentally, this also implements support for vector argument registers,
so long as they are not on the stack.
llvm-svn: 28331
2006-05-16 18:18:50 +00:00
d2ca9abf57
Fit in 80 cols
...
llvm-svn: 28311
2006-05-16 04:20:24 +00:00
04a9e38369
Remove some dead code, identified by coverity.
...
llvm-svn: 28303
2006-05-15 05:48:32 +00:00
ae48a894b1
Remove dead var, fix bad override.
...
llvm-svn: 28264
2006-05-12 21:09:57 +00:00
f76c42776d
remove dead variable.
...
llvm-svn: 28248
2006-05-12 17:33:59 +00:00
a296339c87
Fix PowerPC/2006-05-12-rlwimi-crash.ll
...
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.
llvm-svn: 28243
2006-05-12 16:29:37 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
b25cb79604
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
...
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
llvm-svn: 28213
2006-05-10 06:38:32 +00:00
2814134a5d
Indent .data/.text in the .s file
...
llvm-svn: 28204
2006-05-09 16:15:00 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
ce6646c366
Yet more readme updating
...
llvm-svn: 28172
2006-05-08 20:54:02 +00:00
68a45419cc
New note about something bad happening in target independent optimizers
...
llvm-svn: 28170
2006-05-08 20:08:28 +00:00
0eb8f2e496
Proving once again that I am not as smart as the compiler
...
llvm-svn: 28169
2006-05-08 19:09:24 +00:00
9b6d4c2968
Fold more shifts into inserts, and update the README
...
llvm-svn: 28168
2006-05-08 17:38:32 +00:00
dc996b3f6c
Update some stuff now that the new rlwimi code has gone in
...
llvm-svn: 28162
2006-05-08 02:52:38 +00:00
1333cead5b
New rlwimi implementation, which is superior to the old one. There are
...
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield. More regression tests
to come.
llvm-svn: 28156
2006-05-07 00:23:38 +00:00
8b9e11c110
Print a grouping around inline asm blocks so that we can tell when we are
...
using them.
llvm-svn: 28134
2006-05-05 21:50:04 +00:00
304bbf3b1d
New note, Nate, please check to see if I'm full of it :)
...
llvm-svn: 28118
2006-05-05 05:36:15 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
13d5f3eb05
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
...
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
llvm-svn: 28097
2006-05-04 16:56:45 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
e3a9c70ba0
Change from using MachineRelocation ctors to using static methods
...
in MachineRelocation to create Relocations.
llvm-svn: 28088
2006-05-03 20:30:20 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
b8065a9a3a
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
e1c96369e2
Fix a purely hypothetical problem (for now): emitWord emits in the host
...
byte format. This doesn't work when using the code emitter in a cross target
environment. Since the code emitter is only really used by the JIT, this
isn't a current problem, but if we ever start emitting .o files, it would be.
llvm-svn: 28060
2006-05-02 19:14:47 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
bbcbf48aab
Since we don't handle callee-save CRs right yet, don't allocate them. Also
...
don't step on R11 in the middle of a function when saving and restoring CRs
llvm-svn: 28058
2006-05-02 17:37:31 +00:00
287dc5be0d
Hooray, everyone now uses the same printBasicBlockLabel implementation
...
llvm-svn: 28056
2006-05-02 17:34:51 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
01364fbba8
Update the PPC compilation callback code to not need weird abi-violating
...
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.
llvm-svn: 28049
2006-05-02 04:50:05 +00:00
84b49d51be
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
...
llvm-svn: 28017
2006-04-28 21:56:10 +00:00
a4c2c4a276
Add a note
...
llvm-svn: 27999
2006-04-28 00:04:05 +00:00
318bb96f9e
No functionality changes, but cleaner code with correct comments.
...
llvm-svn: 27966
2006-04-25 04:45:59 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
c8afdfec52
Teach the JIT how to relocate LI, this fixes the JIT on Prolangs-C/TimberWolfMC
...
llvm-svn: 27943
2006-04-22 06:17:56 +00:00
57a32f0bc1
Fix the comment
...
llvm-svn: 27938
2006-04-21 22:11:27 +00:00
516b393992
Change the PPC JIT to use a Static relocation model
...
llvm-svn: 27937
2006-04-21 22:04:15 +00:00
99d3da9d2c
Fix the CodeGen/PowerPC/buildvec_canonicalize.ll regression last night.
...
llvm-svn: 27908
2006-04-20 19:01:30 +00:00
0cd0065c58
Make sure that the new instructions selected have the right type. This fixes
...
CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
llvm-svn: 27868
2006-04-20 05:58:10 +00:00
05bbec5020
add a note
...
llvm-svn: 27832
2006-04-19 16:22:38 +00:00
a922a516b0
add a note
...
llvm-svn: 27828
2006-04-19 05:55:06 +00:00
34c901b50e
These are correctly encoded by the JIT. I checked :)
...
llvm-svn: 27810
2006-04-18 19:03:38 +00:00
197d762232
add a note
...
llvm-svn: 27809
2006-04-18 18:30:19 +00:00
518834c67e
Fix a crash on:
...
void foo2(vector float *A, vector float *B) {
vector float C = (vector float)vec_cmpeq(*A, *B);
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
*A = C;
}
llvm-svn: 27808
2006-04-18 18:28:22 +00:00
1e174c87c3
pretty print node name
...
llvm-svn: 27806
2006-04-18 18:05:58 +00:00
9754d142a4
Implement an important entry from README_ALTIVEC:
...
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
llvm-svn: 27804
2006-04-18 17:59:36 +00:00
68c16a201e
move some stuff around, clean things up
...
llvm-svn: 27802
2006-04-18 17:52:36 +00:00
96d50487c9
Use vmladduhm to do v8i16 multiplies which is faster and simpler than doing
...
even/odd halves. Thanks to Nate telling me what's what.
llvm-svn: 27793
2006-04-18 04:28:57 +00:00
d6d82aa889
Implement v16i8 multiply with this code:
...
vmuloub v5, v3, v2
vmuleub v2, v3, v2
vperm v2, v2, v5, v4
This implements CodeGen/PowerPC/vec_mul.ll. With this, v16i8 multiplies are
6.79x faster than before.
Overall, UnitTests/Vector/multiplies.c is now 2.45x faster with LLVM than with
GCC.
Remove the 'integer multiplies' todo from the README file.
llvm-svn: 27792
2006-04-18 03:57:35 +00:00
7e439874cb
Lower v8i16 multiply into this code:
...
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0: ; <16 x ubyte>
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
llvm-svn: 27789
2006-04-18 03:43:48 +00:00
a2cae1bb10
Custom lower v4i32 multiplies into a cute sequence, instead of having legalize
...
scalarize the sequence into 4 mullw's and a bunch of load/store traffic.
This speeds up v4i32 multiplies 4.1x (measured) on a G5. This implements
PowerPC/vec_mul.ll
llvm-svn: 27788
2006-04-18 03:24:30 +00:00
63a5cdc423
remove done item
...
llvm-svn: 27778
2006-04-17 21:52:03 +00:00
6bd68ae81e
Don't diddle VRSAVE if no registers need to be added/removed from it. This
...
allows us to codegen functions as:
_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr
instead of:
_test_rol:
mfvrsave r2, 256
mr r3, r2
mtvrsave r3
vspltisw v2, -12
vrlw v2, v2, v2
mtvrsave r2
blr
Testcase here: CodeGen/PowerPC/vec_vrsave.ll
llvm-svn: 27777
2006-04-17 21:48:13 +00:00
72d7c27069
Vectors that are known live-in and live-out are clearly already marked in
...
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
llvm-svn: 27772
2006-04-17 21:22:06 +00:00
14c4972b6d
Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this:
...
vspltisw v2, -12
vrlw v2, v2, v2
instead of:
vspltisw v0, -12
vrlw v2, v0, v0
when a function is returning a value.
llvm-svn: 27771
2006-04-17 21:19:12 +00:00
6df094b4ab
Move some knowledge about registers out of the code emitter into the register info.
...
llvm-svn: 27770
2006-04-17 21:07:20 +00:00
0f28d48da2
Use a small table instead of macros to do this conversion.
...
llvm-svn: 27769
2006-04-17 20:59:25 +00:00
e54133cfba
Make sure to check splats of every constant we can, handle splat(31) by
...
being a bit more clever, add support for odd splats from -31 to -17.
llvm-svn: 27764
2006-04-17 18:09:22 +00:00
264c908e3a
Teach the ppc backend to use rol and vsldoi to generate splatted constants.
...
This implements vec_constants.ll:test_vsldoi and test_rol
llvm-svn: 27760
2006-04-17 17:55:10 +00:00
26fb8d9393
add a note
...
llvm-svn: 27758
2006-04-17 17:29:41 +00:00
1b3806ace5
Make some code more general, adding support for constant formation of several
...
new patterns.
llvm-svn: 27754
2006-04-17 06:58:41 +00:00
f8dd76df5b
Learn how to make odd splatted constants in range [17,29]. This implements
...
PowerPC/vec_constants.ll:test_29.
llvm-svn: 27752
2006-04-17 06:07:44 +00:00
2a099c04c1
Pull some code out into a helper function.
...
Effeciently codegen even splats in the range [-32,30].
This allows us to codegen <30,30,30,30> as:
vspltisw v0, 15
vadduwm v2, v0, v0
instead of as a cp load.
llvm-svn: 27750
2006-04-17 06:00:21 +00:00
071ad01ceb
Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,
...
if it can be implemented in 3 or fewer discrete altivec instructions, codegen
it as such. This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll
llvm-svn: 27748
2006-04-17 05:28:54 +00:00
85bfa3c2bc
Regenerate with adjusted costs
...
llvm-svn: 27746
2006-04-17 05:26:20 +00:00
aac2a200cd
Regenerate with correct offset
...
llvm-svn: 27744
2006-04-17 05:08:46 +00:00
311b1a6e23
Increase the opcodes by one each to disambiguate COPY from VMRGHW.
...
llvm-svn: 27742
2006-04-17 00:47:48 +00:00
07a3d01a91
Check in a table, generated by llvm-PerfectShuffle, of optimal shuffles
...
of various 4-element vectors.
llvm-svn: 27739
2006-04-17 00:37:02 +00:00
06a21ba96b
Implement a TODO: have the legalizer canonicalize a bunch of operations to
...
one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.
llvm-svn: 27731
2006-04-16 01:37:57 +00:00
fa5aa396c2
Make the BUILD_VECTOR lowering code much more aggressive w.r.t constant vectors.
...
Remove some done items from the todo list.
llvm-svn: 27729
2006-04-16 01:01:29 +00:00
24acbe46c0
Fix a crash when faced with a shuffle vector that has an undef in its mask.
...
llvm-svn: 27726
2006-04-15 23:48:05 +00:00
873202fabd
Add patterns for matching vnots with bit converted inputs. Most of these will
...
go away when I start using evan's binop type canonicalizer
llvm-svn: 27725
2006-04-15 23:45:24 +00:00
559c8ba466
Allow undef in a shuffle mask
...
llvm-svn: 27714
2006-04-14 23:19:08 +00:00
4211ca9108
Move the rest of the PPCTargetLowering::LowerOperation cases out into
...
separate functions, for simplicity and code clarity.
llvm-svn: 27693
2006-04-14 06:01:58 +00:00
19e9055eb5
Pull the VECTOR_SHUFFLE and BUILD_VECTOR lowering code out into separate
...
functions, which makes the code much cleaner :)
llvm-svn: 27692
2006-04-14 05:19:18 +00:00
883fb053bd
Force non-darwin targets to use a static relo model. This fixes PR734,
...
tested by CodeGen/Generic/vector.ll
llvm-svn: 27657
2006-04-13 17:10:48 +00:00
5879efe0c8
add a note, move an altivec todo to the altivec list.
...
llvm-svn: 27654
2006-04-13 16:48:00 +00:00
9857229aba
Add the README files to the distribution.
...
llvm-svn: 27651
2006-04-13 06:39:24 +00:00
147e50e1c5
Add a new way to match vector constants, which make it easier to bang bits of
...
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
llvm-svn: 27624
2006-04-12 19:07:14 +00:00
74cf9ff761
Rename get_VSPLI_elt -> get_VSPLTI_elt
...
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
llvm-svn: 27614
2006-04-12 17:37:20 +00:00
e318a7574e
Ensure that zero vectors are always v4i32, which forces them to CSE with
...
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
llvm-svn: 27609
2006-04-12 16:53:28 +00:00
f19bcd5177
Fix SingleSource/UnitTests/Vector/sumarray-dbl
...
llvm-svn: 27594
2006-04-11 19:44:43 +00:00
1bb132099f
Fix PR727, correctly handling large stack aligments on ppc
...
llvm-svn: 27593
2006-04-11 19:29:21 +00:00
aaa04230bd
we have a shuffle instr, add an example.
...
llvm-svn: 27592
2006-04-11 18:47:03 +00:00
02b3b72bfc
Suppress debug label when not debug.
...
llvm-svn: 27588
2006-04-11 08:11:53 +00:00
e4db08a2f1
Vector function results go into V2 according to GCC. The darwin ABI doc
...
doesn't say where they go :-/
llvm-svn: 27579
2006-04-11 01:38:39 +00:00
92533cfb4a
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
...
No functionality change.
llvm-svn: 27577
2006-04-11 01:21:43 +00:00
3a68f3c3ca
properly mark vector selects as expanded to select_cc
...
llvm-svn: 27544
2006-04-08 22:59:15 +00:00
0a3d1bbca4
Add VRRC select support
...
llvm-svn: 27543
2006-04-08 22:45:08 +00:00
3f9c17906f
Disable switch lowering for targets based on the selection dag isel,
...
letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
d9e80f4516
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
...
constant pool load.
llvm-svn: 27538
2006-04-08 07:14:26 +00:00
d71a1f946d
Change the interface to the predicate that determines if vsplti* can be used.
...
No functionality changes.
llvm-svn: 27536
2006-04-08 06:46:53 +00:00
c0d6518f27
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
e61cfad815
Add an item
...
llvm-svn: 27470
2006-04-06 23:16:19 +00:00
466841ddc7
Make sure to return the result in the right type.
...
llvm-svn: 27469
2006-04-06 23:12:19 +00:00
a4bbfaed5c
Match vpku[hw]um(x,x).
...
Convert vsldoi(x,x) to work the same way other (x,x) cases work.
llvm-svn: 27467
2006-04-06 22:28:36 +00:00
f38e033270
Add support for matching vmrg(x,x) patterns
...
llvm-svn: 27463
2006-04-06 22:02:42 +00:00
d1dcb52093
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
...
llvm-svn: 27457
2006-04-06 21:11:54 +00:00
a4c727f1cc
remove two done items
...
llvm-svn: 27453
2006-04-06 19:19:38 +00:00
1d33819194
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
...
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
llvm-svn: 27450
2006-04-06 18:26:28 +00:00
e8b83b4206
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
...
vperm with a perm mask lvx'd from the constant pool.
llvm-svn: 27448
2006-04-06 17:23:16 +00:00
c94d932447
Add all of the data stream intrinsics and instructions. woo
...
llvm-svn: 27442
2006-04-05 22:27:14 +00:00
39dc64c955
Fix a typo
...
llvm-svn: 27440
2006-04-05 20:15:25 +00:00
39cc717c65
Fix CodeGen/PowerPC/2006-04-05-splat-ish.ll
...
llvm-svn: 27439
2006-04-05 17:39:25 +00:00
2cf4232ced
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
...
llvm-svn: 27433
2006-04-05 06:09:26 +00:00
2f8e2b2895
add vsl
...
llvm-svn: 27425
2006-04-05 01:16:22 +00:00
575352ac20
add vmladduhm
...
llvm-svn: 27423
2006-04-05 00:49:48 +00:00
5a528e565b
Add m[tf]vscr instructions.
...
llvm-svn: 27421
2006-04-05 00:03:57 +00:00
0c82447c66
add a note
...
llvm-svn: 27419
2006-04-04 23:45:11 +00:00
281bb5da1d
Add missing byte merges.
...
llvm-svn: 27418
2006-04-04 23:43:56 +00:00
fc50ae521c
Add FP -> Int Conversions
...
llvm-svn: 27417
2006-04-04 23:25:02 +00:00
96338b6a21
add average intrinsics
...
llvm-svn: 27416
2006-04-04 23:14:00 +00:00
4464383a17
add a note
...
llvm-svn: 27414
2006-04-04 22:43:55 +00:00
4a744e5c9d
Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.
...
llvm-svn: 27413
2006-04-04 22:28:35 +00:00
95c7adc7cb
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
...
handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
llvm-svn: 27400
2006-04-04 17:25:31 +00:00
b1e6d84544
Plug in the byte and short splats
...
llvm-svn: 27387
2006-04-04 00:05:13 +00:00
447a7968af
Revert accidentally committed hunks.
...
llvm-svn: 27386
2006-04-03 23:58:04 +00:00
533aed9a35
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
...
llvm-svn: 27385
2006-04-03 23:55:43 +00:00
Dan Gohman