4ddd81657b
Disbale the broken fold of shift + sz[ext] for now
...
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
always produces zero or one.
llvm-svn: 21291
2005-04-13 21:23:31 +00:00
e0efd1fa72
remove one more occurance of this that snuck in
...
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
83075510ee
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
...
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
llvm-svn: 21268
2005-04-13 02:40:26 +00:00
af1c0f7a00
Fold shift by size larger than type size to undef
...
Make llvm undef values generate ISD::UNDEF nodes
llvm-svn: 21261
2005-04-12 23:12:17 +00:00
818eb6ddd2
Implement setcc op, -1 sequences
...
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm
llvm-svn: 21260
2005-04-12 21:22:28 +00:00
f67f3bf627
Initial support for allocation condition registers
...
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
79a3bea4ca
Implement bitfield clears
...
Implement divide by negative power of two
llvm-svn: 21240
2005-04-12 00:10:02 +00:00
08698cf644
Update PPC readme. Remove things that are done or aren't ppc specific
...
llvm-svn: 21232
2005-04-11 20:48:57 +00:00
67291ea580
ORo sets CR0
...
llvm-svn: 21227
2005-04-11 15:03:48 +00:00
f29cc88210
Revert the previous patch, which I didn't mean to check in.
...
llvm-svn: 21226
2005-04-11 15:03:41 +00:00
d3dc31009f
Fix a minor bug (ORo didn't mark that it set CR0).
...
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
llvm-svn: 21225
2005-04-11 15:01:39 +00:00
bebefac791
Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
...
(1.5%) instructions in 186.crafty
llvm-svn: 21222
2005-04-11 06:34:10 +00:00
492370311d
Fix another fixme: factor out the constant fp generation code.
...
llvm-svn: 21207
2005-04-10 06:06:10 +00:00
941a01802f
Fix 64 bit argument loading that straddles the args in regs / args on stack
...
boundary.
llvm-svn: 21206
2005-04-10 05:53:14 +00:00
b076731713
Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
...
have to inform the register allocator it might be stepped on.
llvm-svn: 21202
2005-04-10 03:59:42 +00:00
6566e8ac06
Make sure that BRCOND branches can be converted into long branches too.
...
llvm-svn: 21198
2005-04-10 01:48:29 +00:00
3345eadc37
Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
...
llvm-svn: 21197
2005-04-10 01:14:13 +00:00
9ff4b4190f
rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
...
correct. Remove the EmitComparison retvalue, as it is always the first arg.
Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty. Crafty now works!
llvm-svn: 21195
2005-04-10 01:03:31 +00:00
2121a54868
fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
...
llvm-svn: 21193
2005-04-09 23:35:05 +00:00
228fed92e6
Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
...
This caused the "use before a def" assertion on some programs.
With this patch, 254.gap now passes with the PPC backend.
llvm-svn: 21191
2005-04-09 22:05:17 +00:00
e8e070dbfb
do not set the root to null if an argument is dead
...
llvm-svn: 21188
2005-04-09 21:23:24 +00:00
8309a333dd
Add rlwnm instruction for variable rotate
...
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality
llvm-svn: 21187
2005-04-09 20:09:12 +00:00
3a7f5768c5
Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
...
llvm-svn: 21185
2005-04-09 19:47:21 +00:00
a55a5f2580
Switch this instruction selector over to using liveins and liveouts, eliminating
...
implicit defs on entry to the function. yaay :)
llvm-svn: 21184
2005-04-09 16:32:30 +00:00
2f64122319
Optimize FSEL a bit for fneg arguments. This fixes the recently added test
...
case so that we emit
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fsel f1, f1, f3, f2
blr
instead of:
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fneg f0, f1
fneg f0, f0
fsel f1, f0, f3, f2
blr
llvm-svn: 21177
2005-04-09 09:33:07 +00:00
4f77badaa3
This target does not yet support ISD::BRCONDTWOWAY
...
llvm-svn: 21163
2005-04-09 03:22:30 +00:00
e8ce0cda40
64b: Expand S/UREM
...
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
Pattern match fsub a, mul(b, c) as fnmsub
Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%
llvm-svn: 21161
2005-04-09 03:05:51 +00:00
f50b597f67
Fix 64b shifts
...
llvm-svn: 21159
2005-04-08 23:45:01 +00:00
705d3c18e8
Match Mac OS X 64 bit calling conventions
...
llvm-svn: 21157
2005-04-08 21:26:05 +00:00
b1f66d1af2
Optimized code sequences for setcc reg, 0
...
Optimized code sequence for (a < 0) ? b : 0
llvm-svn: 21150
2005-04-07 20:30:01 +00:00
532ac79122
PowerPC zero extends setcc results
...
llvm-svn: 21147
2005-04-07 19:41:49 +00:00
d20628ff7d
Pattern match bitfield insert, which helps shift long by immediate, among
...
other things.
llvm-svn: 21127
2005-04-06 23:51:40 +00:00
505f6b760d
Fix some shift bugs
...
llvm-svn: 21126
2005-04-06 22:42:08 +00:00
39ef2f1d43
Fixed version of optimized integer divide is now fixed. Calculate the
...
quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
llvm-svn: 21111
2005-04-06 06:44:57 +00:00
dd397119b0
Turn off the div -> mul optimization until it works correctly 100% of the
...
time.
llvm-svn: 21105
2005-04-06 03:36:33 +00:00
4164c4baac
Add support for MULHS and MULHU nodes
...
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
llvm-svn: 21104
2005-04-06 00:25:27 +00:00
524417357c
Behold, rlwinm with certain immediate arguments is printed as the much more
...
readable slwi or srwi (shift left/right word immediate).
llvm-svn: 21099
2005-04-05 18:19:50 +00:00
a188b698a2
Fix cut & paste errors (32->64), and codegen float->int more optimally.
...
llvm-svn: 21098
2005-04-05 17:32:30 +00:00
9203e169a7
Remove 64 bit simple ISel, it never worked correctly
...
Add initial (buggy) implementation of 64 bit pattern ISel
llvm-svn: 21096
2005-04-05 08:51:15 +00:00
4bde071216
Back out the previous change to SelectBranchCC, since there are cases it
...
could miscompile. A correct solution will be found in the near future.
llvm-svn: 21095
2005-04-05 04:32:16 +00:00
9049e4beec
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
...
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
llvm-svn: 21094
2005-04-05 04:22:58 +00:00
d6933f5078
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
...
llvm-svn: 21091
2005-04-05 00:15:08 +00:00
1d5d767a09
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
...
llvm-svn: 21090
2005-04-04 23:40:36 +00:00
d96350095c
Add support for multiply-add, multiply-sub, and their negated versions
...
llvm-svn: 21089
2005-04-04 23:01:51 +00:00
1194531057
Make sure that arg regs used by the call instruction are marked as such, so
...
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
llvm-svn: 21086
2005-04-04 22:17:48 +00:00
c7186025de
Remove unnecessary register copy now that regalloc is fixed
...
llvm-svn: 21085
2005-04-04 21:48:13 +00:00
d753765460
i1 loads should also be from the low byte of the argument word.
...
llvm-svn: 21077
2005-04-04 09:09:00 +00:00
1ce4839890
Fix i64 return, fix CopyFromReg
...
llvm-svn: 21076
2005-04-04 06:52:38 +00:00
629cdaea39
Full varargs support. All of UnitTests now passes
...
llvm-svn: 21070
2005-04-03 23:11:17 +00:00
7a3e929efc
Pass the correct value for the chain to the store
...
llvm-svn: 21066
2005-04-03 22:22:56 +00:00
f6dc43bd46
Fix SHL_PARTS
...
Start implementation of integer varargs
llvm-svn: 21065
2005-04-03 22:13:27 +00:00
34cc5b329f
Keeping up with the Joneses.
...
Implement not, nor, nand, and eqv
llvm-svn: 21060
2005-04-03 11:20:20 +00:00
165cf4844e
Set shift amount to Extend
...
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
llvm-svn: 21018
2005-04-02 05:59:34 +00:00
0b7e4cd107
This target doesn't support fabs/fneg yet.
...
llvm-svn: 21010
2005-04-02 05:03:24 +00:00
cfc452d088
Fix i64 returns
...
Generate PowerPC 'subfic' instruction when appropriate
llvm-svn: 20995
2005-04-02 00:42:16 +00:00
cda9aa7fa9
Add ISD::UNDEF node
...
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
arguments, but not shadowing their value. This allows us to do the right
thing with both fixed and vararg floating point arguments.
llvm-svn: 20988
2005-04-01 22:34:39 +00:00
1c3aea6019
Fix Olden/bh, CR0 was being set in the wrong order
...
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.
llvm-svn: 20981
2005-04-01 08:57:43 +00:00
c9e50238c5
Also apply Chris's fix to FP select and SETCC
...
llvm-svn: 20979
2005-04-01 07:21:30 +00:00
ffc7f243fe
Move the selection of the arms of the select operation up to the conditional
...
part to make sure we get the side effects and to avoid confusing the CFG.
llvm-svn: 20977
2005-04-01 07:10:02 +00:00
2095f3b06b
Fix stores to global addresses
...
Fix calls with no arguments
llvm-svn: 20975
2005-04-01 05:57:17 +00:00
839b34c367
Support indexed loads and stores. This drops Shootout/matrix time from
...
18.8 to 14.8 seconds. The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.
llvm-svn: 20973
2005-04-01 04:45:11 +00:00
f4d91610ff
Implement FP_TO_SINT and FP_TO_UINT
...
llvm-svn: 20972
2005-04-01 02:59:27 +00:00
508aac2ca8
Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
...
say that we support them, for the purposes of generating fsel instructions.
llvm-svn: 20970
2005-04-01 01:08:07 +00:00
4f3a9860d3
Factor out common code, support FP comparison in folded SetCC
...
llvm-svn: 20969
2005-04-01 00:32:34 +00:00
6215b35918
fsel generation for f32 and f64 select
...
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select
Code generation quality for Shootout is now on par with the Simple ISel
llvm-svn: 20968
2005-03-31 23:55:40 +00:00
eddfff338a
Pass the correct values to the chain argument for node construction during
...
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!
llvm-svn: 20946
2005-03-31 02:05:53 +00:00
9de7ddf7d5
Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
...
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads
As a result, all of Shootout, and likely many other programs are now
working.
llvm-svn: 20945
2005-03-31 00:15:26 +00:00
4c0780cf42
Fix calls whose arguments fit entirely in registers to not break the Chain.
...
Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel
llvm-svn: 20944
2005-03-30 19:38:35 +00:00
a8114a0f48
Fix frame index code to generate legal PowerPC instructions. About half of
...
Shootout now works.
llvm-svn: 20940
2005-03-30 02:23:08 +00:00
5851a66128
Fix external symbol printing in the AsmPrinter. Tell the ISel that we
...
don't support things like memcpy directly. This allows a handful of the
Shootout programs to work, yay!
llvm-svn: 20939
2005-03-30 01:45:43 +00:00
9c40e9c61f
Fix BranchCC (it's still dumb), and implement FP select (also dumb)
...
llvm-svn: 20935
2005-03-29 22:48:55 +00:00
28145edd30
Implement integer select and i1 sign extend
...
llvm-svn: 20934
2005-03-29 22:24:51 +00:00
28c5ac9ff4
Implement SetCC, fix ZERO_EXTEND_INREG
...
llvm-svn: 20933
2005-03-29 21:54:38 +00:00
1ce9aacf2e
fix a warning in the optimized build
...
llvm-svn: 20920
2005-03-29 15:13:27 +00:00
60956dd52f
Implement div, rem, and frameindex
...
llvm-svn: 20907
2005-03-29 00:03:27 +00:00
731bed10c7
Pattern ISel: fix argument loading for i64s (thanks chris)
...
Simple ISel: fix i64 subtract
llvm-svn: 20903
2005-03-28 23:08:54 +00:00
66acad746f
Remove fake instruction 'subc' (mnemonic for subfc).
...
More pattern isel updates
llvm-svn: 20902
2005-03-28 22:28:37 +00:00
5bdfc63516
Implement proper loads and zero-extends of all types
...
llvm-svn: 20897
2005-03-28 19:36:43 +00:00
518a994b7d
Fix that pesky floats in integer regs problem by assigning the f32 type to
...
the correct register class. Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.
llvm-svn: 20857
2005-03-26 08:25:22 +00:00
dcad53e7bd
Get closer to having varargs working. There's still something strange
...
going on with copies between floating point and integer register files
being generated. Once that is solved, varargs will be done.
llvm-svn: 20856
2005-03-26 07:46:36 +00:00
c95bf7b226
Make 64bit args and float args work correct with calls. Thanks to Chris
...
for explaining EXTRACT_ELEMENT to me.
llvm-svn: 20847
2005-03-26 02:17:46 +00:00
e70b5c79f8
Next round of pattern isel changes, mostly dealing with calls.
...
llvm-svn: 20841
2005-03-26 01:28:53 +00:00
5d7610de65
Correct a documention link
...
llvm-svn: 20840
2005-03-26 01:28:05 +00:00
0ad33afe22
Support global addresses and fix call returns. Varargs still aren't
...
handled correctly for floating point arguments, or more than 8 arguemnts.
This does however, allow hello world to run.
llvm-svn: 20832
2005-03-25 08:34:25 +00:00
ad5151d785
Implement next round of Pattern ISel fixes
...
1. void returns
2. multiplies
3. calls
llvm-svn: 20822
2005-03-24 23:35:30 +00:00
3a9a2f9ec7
Fix an incorrect argument being passed to BuildMI for indirect calls.
...
llvm-svn: 20821
2005-03-24 23:34:38 +00:00
d73c87a424
Commit Gabor Greif's patch to use iterators in lowering intrinsics.
...
llvm-svn: 20816
2005-03-24 20:07:16 +00:00
b15317b74a
eliminate dead variables, patch contributed by Gabor Greif!
...
llvm-svn: 20812
2005-03-24 17:32:20 +00:00
7ec19b4d5a
Implement more of the PPC32 Pattern ISel:
...
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel
Remove dead arguments from getGlobalBaseReg in the simple ISel
llvm-svn: 20810
2005-03-24 06:28:42 +00:00
a3abb4c01a
Fix silly "no newline at end of file" warning
...
llvm-svn: 20809
2005-03-24 06:16:18 +00:00
20e7e28ee7
Addition of the PPC32 Pattern ISel. While it is far from complete, it will
...
be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.
llvm-svn: 20805
2005-03-24 04:41:43 +00:00
82ae9e1dda
We may be adding functions to the Module during initialization, so
...
conservatively, it's modified
llvm-svn: 20735
2005-03-21 19:22:14 +00:00
531f9e92d4
This mega patch converts us from using Function::a{iterator|begin|end} to
...
using Function::arg_{iterator|begin|end}. Likewise Module::g* -> Module::global_*.
This patch is contributed by Gabor Greif, thanks!
llvm-svn: 20597
2005-03-15 04:54:21 +00:00
1f1462fafa
Fix a crash handling 'undef bool', fixing an llc crash on 186.crafty
...
llvm-svn: 20523
2005-03-08 22:53:09 +00:00
5b5caaf3cd
cleanup the cfg after lsr
...
llvm-svn: 20410
2005-03-02 21:56:00 +00:00
c8bb99760a
Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on
...
Loop Strength Reduction.
llvm-svn: 20399
2005-03-02 06:19:22 +00:00
915fd0de4b
Fix a problem where the PPC backend lost track of the fact that it had
...
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool. This should hopefully
fix oscar from sending the PPC tester spinning out of control.
llvm-svn: 20197
2005-02-15 20:26:49 +00:00
d7bffad559
Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.ll
...
llvm-svn: 19557
2005-01-14 20:22:02 +00:00
c3ed31f837
Fix: Regression/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
...
llvm-svn: 19555
2005-01-14 19:31:00 +00:00
82787e90f3
This hunk:
...
- unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
+ unsigned TrueValue = getReg(TrueVal);
Fixes the PPC regressions from last night.
The other hunk is just a clarity improvement.
llvm-svn: 19263
2005-01-02 23:07:31 +00:00
83df5d25b7
Fix a FIXME: Select instructions on longs were miscompiled.
...
While we're at it, improve codegen of select instructions. For this
testcase:
int %test(bool %C, int %A, int %B) {
%D = select bool %C, int %A, int %B
ret int %D
}
We used to generate this code:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
b .LBB_test_3 ;
.LBB_test_2: ;
or r5, r4, r4
.LBB_test_3: ;
or r3, r5, r5
blr
Now we emit:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
or r4, r5, r5
.LBB_test_2: ;
or r3, r4, r4
blr
-Chris
llvm-svn: 19214
2005-01-01 16:10:12 +00:00
a38954dd64
Specify all of the targets built.
...
llvm-svn: 18985
2004-12-16 17:26:44 +00:00
0782e27d85
Factor out common .td file chunks.
...
llvm-svn: 18982
2004-12-16 16:31:57 +00:00
cbd47631ea
Fix Regression/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll, and all programs
...
when compiled with debug information.
llvm-svn: 18835
2004-12-12 20:36:19 +00:00
10b637eade
CSE calls to getTypeSize.
...
llvm-svn: 18833
2004-12-12 20:31:00 +00:00
17550c456c
Use the target triple to pick this target.
...
llvm-svn: 18830
2004-12-12 17:40:28 +00:00
bd11625469
Fix several bugs in 'op x, imm' handling. Foremost is that we now emit
...
addi r3, r3, -1
instead of
addi r3, r3, 1
for 'sub int X, 1'.
Secondarily, this fixes several cases where we could crash given an unsigned
constant. And fixes a couple of minor missed optimization cases, such as
xor X, ~0U -> not X
llvm-svn: 18379
2004-11-30 07:30:20 +00:00
7562a05735
Fix CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
...
llvm-svn: 18376
2004-11-30 06:40:04 +00:00
ce350cbd3a
Fix test/Regression/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
...
llvm-svn: 18374
2004-11-30 06:36:11 +00:00
9eeb2033ff
Fix test/Regression/CodeGen/PowerPC/2004-11-30-shift-crash.ll
...
llvm-svn: 18371
2004-11-30 06:29:10 +00:00
c0f8a1c721
The LLVM bool type shall have 1 byte alignment on PPC.
...
llvm-svn: 18311
2004-11-28 21:16:45 +00:00
43123c9f7a
Remove the ISel->AsmPrinter link via the TargetMachine that was put in
...
place to help bring up the PowerPC back end on Darwin. This code is no
longer serves any purpose now that the AsmPrinter does the right thing
all the time printing GlobalValues. --Cruft.
llvm-svn: 18267
2004-11-27 04:45:11 +00:00
b50fd9262d
There is no reason to store <x,x>, just store <x>.
...
llvm-svn: 18263
2004-11-26 20:25:17 +00:00
3f76eb69f6
Enable optimization suggested by Chris Lattner to not emit reloc stubs for
...
static global variables whose addresses are taken. This allows us to
convert the following code for taking the address of a static function foo
addis r2, r30, ha16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")
lwz r3, lo16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")(r2)
which also includes linker stub code emitted at the end of the .s file not
shown here, and replace it with this:
addis r2, r30, ha16(l1__2E_foo_2-"L00001$pb")
la r3, lo16(l1__2E_foo_2-"L00001$pb")(r2)
which in addition to not needing linker help, also has no load instruction.
For those not up on PowerPC mnemonics, la is shorthand for add immediate.
llvm-svn: 18239
2004-11-25 07:09:01 +00:00
8cbad8efcf
Fix the build on non ppc machines
...
llvm-svn: 18235
2004-11-25 06:14:45 +00:00
497a622376
The JIT works enough
...
llvm-svn: 18228
2004-11-25 04:14:54 +00:00
da76c16ba4
Fix encoding of fsel, fixing olden/power, McCat/bisort and several others.
...
All of Olden passes now! :)
llvm-svn: 18227
2004-11-25 04:11:07 +00:00
305f78f646
Fix encoding of fneg instruction
...
llvm-svn: 18226
2004-11-25 03:53:44 +00:00
191e525bae
Fix encoding of swari, fixing several programs, including Olden/mst
...
llvm-svn: 18225
2004-11-25 03:40:20 +00:00
5d8ae54267
There is not a 1-1 mappign between llvm blocks and PPC blocks, do not use
...
LLVM blocks as the keys for the branch rewriter. This fixes treeadd and
many other programs with the JIT.
llvm-svn: 18223
2004-11-25 00:33:57 +00:00
dd516799d7
* Rename existing relocations to be more specific
...
* Add relocations for refernces to non-lazy darwin stubs and implement
them correctly.
With this change, we can correctly references external globals, and now
all but two UnitTests and all but 1 Regression/C tests pass.
More importantly, bugpoint-jit will start giving us useful testcases,
instead of always telling us that references to external globals don't
work :)
llvm-svn: 18222
2004-11-24 22:30:08 +00:00
e49936af54
Add the same optimization that we do loading from fixed alloca slots to
...
storing to fixed alloca slots.
llvm-svn: 18221
2004-11-24 21:53:14 +00:00
078b6f2b62
Write CompilationCallback as an explicit assembly stub to avoid getting GCC's
...
prolog.
llvm-svn: 18220
2004-11-24 21:01:46 +00:00
659d72e319
When rewriting the original call instruction, make sure to rewrite it to
...
call the right address.
llvm-svn: 18213
2004-11-24 18:00:02 +00:00
cb9af557e7
Force the intregs ptr into R2 and the FPregs ptr into R3. This fixes a really
...
obscure problem where we were doing:
lmw r3,0(r9)
which is undefined on PPC. Now we do:
lmw r3,0(r2)
by force, not relying on the GCC register allocator for luck :)
llvm-svn: 18212
2004-11-24 17:42:55 +00:00
130888ad37
Fix a few more tests by encoding the extsb and other XForm11 instructions
...
correctly.
llvm-svn: 18200
2004-11-24 03:52:02 +00:00
022e271db5
Fix the encoding of ORi and other DForm4 instructions. This brings us to
...
36/42 SingleSource/UnitTests passing!
llvm-svn: 18199
2004-11-24 02:15:41 +00:00
57542fcfc2
Loads are relocatable too
...
llvm-svn: 18198
2004-11-24 02:03:44 +00:00
7b1cf0d6c6
Calls do not need a MovPCtoLR instruction
...
llvm-svn: 18197
2004-11-24 02:00:06 +00:00
6a7ebe034e
Get constant pools working. This fixes even more programs, allowing us to
...
pass 24/42 in UnitTests (up from 20).
llvm-svn: 18196
2004-11-24 01:56:12 +00:00
193b6f3281
Rewrite branches more closely to correct. This makes more stuff pass, and
...
stops the infinite loops!
llvm-svn: 18194
2004-11-24 01:35:12 +00:00
b55f748b1a
Branch instructions explicitly represent CRx in them. bEcause of this, encode
...
them explicitly as well.
llvm-svn: 18193
2004-11-24 01:15:19 +00:00
674fe0bb60
Fix encoding of bctrl, and remove some unused instructions
...
llvm-svn: 18192
2004-11-24 00:16:37 +00:00
c7eeae4661
Fix encoding of blr and bctr
...
llvm-svn: 18178
2004-11-23 22:06:24 +00:00
c5fc6f5717
Use the correct register class as a constaint to gcc's inline assembly, so
...
that we don't end up trying to use r0 as a base register.
llvm-svn: 18176
2004-11-23 21:37:22 +00:00
617760687a
Save/Restore arg regs and nonvolatile regs the compiler might use during
...
CompilationCallback
llvm-svn: 18175
2004-11-23 21:34:18 +00:00
578dfd5e42
Fix the encoding of OR, AND and many other instructions
...
llvm-svn: 18174
2004-11-23 21:17:35 +00:00
a630adebc7
Remove argtype and argcount magic, which was used by the old asmprinter.
...
llvm-svn: 18170
2004-11-23 20:41:34 +00:00
be39b8f541
Get rid of flags that are dead
...
llvm-svn: 18169
2004-11-23 20:37:41 +00:00
5f4b0e1bf7
Fix encoding of rlwinm?
...
llvm-svn: 18165
2004-11-23 19:23:32 +00:00
1238cca6df
Fix encodings
...
llvm-svn: 18164
2004-11-23 19:23:18 +00:00
431e0132ef
Enumerate CR registers
...
llvm-svn: 18162
2004-11-23 18:59:59 +00:00
a8936af13e
Initial implementation of exiting CompilationCallback
...
This should save all argument registers on entry and restore on exit, despite
that, simple things seem to work!!!
llvm-svn: 18161
2004-11-23 18:49:46 +00:00
febc3eb8fa
This method is dead
...
llvm-svn: 18160
2004-11-23 18:47:55 +00:00
24ad93f55c
Remove this method.
...
llvm-svn: 18159
2004-11-23 18:47:42 +00:00
b1fd07a862
Squelch a bogus warning.
...
llvm-svn: 18156
2004-11-23 15:56:38 +00:00
7e7a08dba5
Don't return value from void function. This is only temporary anyway while
...
the JIT is made to work!
llvm-svn: 18155
2004-11-23 10:04:49 +00:00
40ff89c212
Fix a minor bug
...
llvm-svn: 18153
2004-11-23 06:56:31 +00:00
5369ab3e24
Be really paranoid about not breaking stuff yet
...
llvm-svn: 18152
2004-11-23 06:56:18 +00:00
4ff117585d
Implement the first hunk of CompilationCallback. The pieces missing are the
...
ones noted, which require funny PPC specific inline assembly.
If some angel felt the desire to help me, I think this is that last bit missing
for JIT support (however, generic code emitter might night work right with
the constant pool yet).
llvm-svn: 18151
2004-11-23 06:55:05 +00:00
7445c5eadc
Implement the stub needed to get into compilation callback.
...
llvm-svn: 18147
2004-11-23 06:27:02 +00:00
e1187d46a1
Simplify code a bit
...
llvm-svn: 18146
2004-11-23 06:05:44 +00:00
8296c4c323
Initial implementation of the JIT interfaces. Relocation is done and stubs
...
for external functions work. CompilationCallback has not been written, and
stubs for internal functions are not generated yet. This means you can call
printf and exit, and use global variables, but cannot call functions local to
a module yet.
llvm-svn: 18145
2004-11-23 06:02:06 +00:00
743a43424f
Emit relocations for the global variable using instructions. This gets us
...
LA, LOADHiAddr, CALLpcrel, and MovePCtoLR working, though the constant pool
probably is not right.
llvm-svn: 18144
2004-11-23 05:59:53 +00:00
1c95751676
Implement all of the methods
...
llvm-svn: 18142
2004-11-23 05:57:57 +00:00
0b4eb3f806
Initial checkin of the 32-bit PPC relocation types
...
llvm-svn: 18141
2004-11-23 05:57:38 +00:00
f5363dc789
Move JITInfo from PPCTM to PPC32TM
...
llvm-svn: 18140
2004-11-23 05:56:40 +00:00
ae670d5895
Do not provide the non-specialized PowerPCJITInfo object, it is pretty useless.
...
Instead, let derived classes provide specialized ones.
llvm-svn: 18139
2004-11-23 05:55:38 +00:00
6500c6d332
LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter
...
llvm-svn: 18138
2004-11-23 05:54:25 +00:00
69e4cc55ef
Remove some dead code
...
llvm-svn: 18136
2004-11-22 23:07:22 +00:00
40565d72d4
Comment out a couple of unused instructions.
...
llvm-svn: 18135
2004-11-22 23:07:01 +00:00
0e7faedde7
Disable this.
...
llvm-svn: 18130
2004-11-22 21:51:40 +00:00
8e9ed2747c
This chunk of code needs to be rewritten
...
llvm-svn: 18127
2004-11-22 21:45:54 +00:00
6c9375b20c
Fix Shootout-C++/wc, which was broken by my recent changes to emit fewer
...
reg-reg copies. The necessary conditions for this bug are a GEP that is
used outside the basic block in which it is defined, whose components
other than the pointer are all constant zero, and where the use is
selected before the definition (backwards branch to successsor block).
llvm-svn: 18084
2004-11-21 05:14:06 +00:00
aee9a76f52
ignore generated files.
...
llvm-svn: 18072
2004-11-21 00:00:54 +00:00
6f01b4cf1f
Remove this method, it's not clear how it could be implemented indep of 32 or 64-bit mode
...
llvm-svn: 18038
2004-11-20 04:17:17 +00:00
f0c6aff268
getJITStubForFunction is optional and unimplemented, just remove it.
...
llvm-svn: 18036
2004-11-20 04:14:44 +00:00
488f4a4352
Eliminate another 6k register copies that the register allocator would just
...
coalesce out of hbd. Speeds up compilation by 2% (0.6s)
llvm-svn: 17987
2004-11-19 08:01:16 +00:00
f4fd759f9e
Generate fewer reg-reg copies for the register allocator to deal with.
...
This eliminates over 2000 in hbd alone.
llvm-svn: 17973
2004-11-19 02:06:40 +00:00
2b575bec80
Eliminate another common source of moves that the register allocator
...
shouldn't be forced to coalesce for us: folded GEP operations. This too
fires thousands of times across the testsuite.
llvm-svn: 17947
2004-11-18 07:22:46 +00:00
5d9c292e7f
When accessing the base register for global variables, use the register
...
directly rather than making a copy for the register allocator to coalesce.
This kills thousands of live intervals across the testsuite.
llvm-svn: 17946
2004-11-18 06:51:29 +00:00
51f6635e42
Clean up and fix cast codegen by removing cases that are handled elsewhere,
...
and properly emitting signed short to unsigned int. This fixes the last
regression vs. the CBE, MultiSource/Applications/hbd.
llvm-svn: 17942
2004-11-18 04:56:53 +00:00
f242979cd0
Simplify namespaces
...
llvm-svn: 17870
2004-11-16 04:47:33 +00:00
a8c99d4daf
Add BCTR and LWZU instruction opcodes
...
llvm-svn: 17851
2004-11-15 21:20:09 +00:00
e225fa12ab
Handle GhostLinkage (should not ever reach the assembly printing stage!)
...
llvm-svn: 17749
2004-11-14 21:03:30 +00:00
8b8ba9fcf7
Fix build on Linux/PowerPC64 using SuSE GCC (#undef PPC)
...
llvm-svn: 17744
2004-11-14 20:34:01 +00:00
1164955bf1
Allow hbd to be bugpointable on darwin by fixing common and linkonce codegen
...
llvm-svn: 17637
2004-11-09 04:01:18 +00:00
0822032c95
Put int the getReg cast optimization from x86 so that we generate fewer
...
move instructions for the register allocator to coalesce.
llvm-svn: 17608
2004-11-08 02:25:40 +00:00
f5f0b6b6b0
Disable bogus cast elimination when the cast is used by a setcc instruction.
...
llvm-svn: 17583
2004-11-07 20:23:42 +00:00
bff3d4abf0
Thanks to sabre for pointing out that we were incorrectly codegen'ing
...
int test(int x) { return 32768 - x; }
Fixed by teaching the function that checks a constant's validity to be used
as an immediate argument about subtract-from instructions.
llvm-svn: 17476
2004-11-04 19:43:18 +00:00
57cbe39d1e
Change Library Names Not To Conflict With Others When Installed
...
llvm-svn: 17286
2004-10-27 23:18:45 +00:00
dd8f1d8b77
Remove file that is no longer used, and move include of MRegisterInfo.h
...
from PowerPCFrameInfo.h to PowerPCAsmPrinter.cpp where it is actually
needed.
llvm-svn: 17244
2004-10-26 06:02:38 +00:00
47b9d33f5b
Eliminate usage of MRegisterInfo::getRegClass(physreg)
...
llvm-svn: 17240
2004-10-26 05:40:45 +00:00
4c6e1d694c
Update to-do list
...
llvm-svn: 17235
2004-10-26 04:10:53 +00:00
26feb4f6d8
Fix treecc. Also fix a latent bug in emitBinaryConstOperation that would
...
allow and const, 0 to be incorrectly codegen'd into a rlwinm instruction.
llvm-svn: 17234
2004-10-26 03:48:25 +00:00
ff43ef3cc5
Disable the JIT until it can sorta kinda work.
...
llvm-svn: 17230
2004-10-25 20:53:41 +00:00
74b7c1f3e0
Implement more complete and correct codegen for bitfield inserts, as tested
...
by the recently committed rlwimi.ll test file. Also commit initial code
for bitfield extract, although it is turned off until fully debugged.
llvm-svn: 17207
2004-10-24 10:33:30 +00:00
9ce0da9e90
* Correctly handle the MovePCtoLR pseudo-instr with a bl to next instr
...
* Stop the confusion of using rv and Addr for global addresses: just use rv
llvm-svn: 17195
2004-10-23 23:47:34 +00:00
f1f6270708
Add BA, BL, and BLA opcodes
...
llvm-svn: 17193
2004-10-23 20:29:24 +00:00
421c3c1ec4
* Do not emit IMPLICIT_DEF pseudo-instructions
...
* Convert register numbers from their opcode value to the real value, e.g.
PPC::R1 => 1 and PPC::F1 => 1
* Add correct handling of loading of global values which are PC-relative --
implement ha16() and lo16()
llvm-svn: 17190
2004-10-23 18:28:01 +00:00
15b0fb5678
DForm_1, particularly used by store instructions, needs the immediate operand to
...
be listed second as that is how the instructions are usually created (and is the
correct asm syntax) so that it's assembled correctly from its constituents
llvm-svn: 17183
2004-10-23 06:08:38 +00:00
e882d30aa1
Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
...
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.
llvm-svn: 17182
2004-10-23 06:05:49 +00:00
55a3ccd035
The value of the XO field for MFLR and MFCTR is 339, not 399
...
llvm-svn: 17181
2004-10-23 05:38:55 +00:00
101d5d62d5
Remove extraneous blank line
...
llvm-svn: 17180
2004-10-23 04:59:22 +00:00
cea2e46821
Align function arguments in function headers
...
llvm-svn: 17178
2004-10-23 04:58:32 +00:00
6cadac8f43
Kill casts from integer types to unsigned byte, when the cast was only used
...
as the shift amount operand to a shift instruction. This was causing us to
emit unnecessary clear operations for code such as:
int foo(int x) { return 1 << x; }
llvm-svn: 17175
2004-10-23 00:50:23 +00:00
30d8baea8d
Adjust to changes in Makefile.rules
...
llvm-svn: 17167
2004-10-22 21:02:08 +00:00
c1c320c335
We won't use automake
...
llvm-svn: 17155
2004-10-22 03:35:04 +00:00
a6ecf271db
Remove debug code emitter from the JIT
...
llvm-svn: 17151
2004-10-21 03:07:38 +00:00
757cc0e84c
Make this compile.
...
llvm-svn: 17150
2004-10-21 02:44:16 +00:00
2beb63a65a
* Added basic support for JITing functions, basic blocks, instruction encoding,
...
including registers, constants, and partial support for global addresses
* The JIT is disabled by default to allow building llvm-gcc, which wants to test
running programs during configure
llvm-svn: 17149
2004-10-21 01:42:02 +00:00
86b5f8075c
Don't clear or sign extend bool->int. This fires a few dozen times on the test suite
...
llvm-svn: 17147
2004-10-20 21:55:41 +00:00
6a11a75f31
Initial automake generated Makefile template
...
llvm-svn: 17136
2004-10-18 23:55:41 +00:00
844186b8b4
Generate correct stubs for weak-linked symbols
...
llvm-svn: 17101
2004-10-17 23:01:34 +00:00
de028a4a69
PPC32GenCodeEmitter instead of PowerPCGenCodeEmitter
...
llvm-svn: 17087
2004-10-17 14:59:38 +00:00
2c873ca365
Implement bitfield insert by recognizing the following pattern:
...
1. optional shift left
2. and x, immX
3. and y, immY
4. or z, x, y
==> rlwimi z, x, y, shift, mask begin, mask end
where immX == ~immY and immX is a run of set bits. This transformation
fires 32 times on voronoi, once on espresso, and probably several
dozen times on external benchmarks such as gcc.
To put this in terms of actual code generated for
struct B { unsigned a : 3; unsigned b : 2; };
void storeA (struct B *b, int v) { b->a = v;}
void storeB (struct B *b, int v) { b->b = v;}
Old:
_storeA:
rlwinm r2, r4, 0, 29, 31
lwz r4, 0(r3)
rlwinm r4, r4, 0, 0, 28
or r2, r4, r2
stw r2, 0(r3)
blr
_storeB:
rlwinm r2, r4, 3, 0, 28
rlwinm r2, r2, 0, 27, 28
lwz r4, 0(r3)
rlwinm r4, r4, 0, 29, 26
or r2, r2, r4
stw r2, 0(r3)
blr
New:
_storeA:
lwz r2, 0(r3)
rlwimi r2, r4, 0, 29, 31
stw r2, 0(r3)
blr
_storeB:
lwz r2, 0(r3)
rlwimi r2, r4, 3, 27, 28
stw r2, 0(r3)
blr
llvm-svn: 17078
2004-10-17 05:19:20 +00:00
29dc5f2a3e
Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly
...
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.
This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.
llvm-svn: 17068
2004-10-16 20:43:38 +00:00
a3f3c8a1ad
ADd support for undef and unreachable
...
llvm-svn: 17050
2004-10-16 18:13:47 +00:00
a15c246af9
Better codegen of binary integer ops with 32 bit immediate operands.
...
This transformation fires a few dozen times across the testsuite.
For example, int test2(int X) { return X ^ 0x0FF00FF0; }
Old:
_test2:
lis r2, 4080
ori r2, r2, 4080
xor r3, r3, r2
blr
New:
_test2:
xoris r3, r3, 4080
xori r3, r3, 4080
blr
llvm-svn: 17004
2004-10-15 00:50:19 +00:00
1f596c3358
* Claim to support machine code emission - return false from
...
addPassesToEmitMachineCode()
* Add support for registers and constants in getMachineOpValue()
This enables running "int main() { ret 0 }" via the PowerPC JIT.
llvm-svn: 16983
2004-10-14 06:39:56 +00:00
8b1bf4323f
* Include the real (generated) version of getBinaryCodeForInstr()
...
* Add implementation of getMachineOpValue() for generated code emitter
* Convert assert()s in unimplemented functions to abort()s so that non-debug
builds fail predictably
* Add file header comments
llvm-svn: 16981
2004-10-14 06:07:25 +00:00
c2d6aaeaa0
* Make a PPC32-specific code emitter because we have separate classes for 32-
...
and 64-bit code emitters that cannot share code unless we use virtual
functions
* Identify components being built by tablegen with more detail by assigning them
to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building
PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64
llvm-svn: 16980
2004-10-14 06:04:56 +00:00
189f3dc8d2
There is only one field in an instruction, and that is `Inst', the final view of
...
the instruction binary format, all others are simply operands and should not
have the `field' label
llvm-svn: 16978
2004-10-14 05:55:37 +00:00
d6ac8f5e5a
PowerPC instruction definitions use LittleEndian-style encoding [0..31]
...
llvm-svn: 16977
2004-10-14 05:54:38 +00:00
ace94df71f
Update to reflect changes in Makefile rules.
...
llvm-svn: 16950
2004-10-13 11:46:52 +00:00
97327f05fc
Initial version of automake Makefile.am file.
...
llvm-svn: 16893
2004-10-10 22:20:40 +00:00
3acdb7fa1b
bling bling!
...
llvm-svn: 16873
2004-10-10 16:26:13 +00:00
b58dd6799f
Implement logical and with an immediate that consists of a contiguous block
...
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.
int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }
_andn4:
rlwinm r3, r3, 0, 0, 29
blr
_clearhi:
rlwinm r3, r3, 0, 16, 31
blr
_clearlo:
rlwinm r3, r3, 0, 0, 15
blr
_clearmid:
rlwinm r3, r3, 0, 8, 23
blr
_clearwrap:
rlwinm r3, r3, 0, 24, 7
blr
llvm-svn: 16832
2004-10-08 02:49:24 +00:00
6e6514c47e
Several fixes and enhancements to the PPC32 backend.
...
1. Fix an illegal argument to getClassB when deciding whether or not to
sign extend a byte load.
2. Initial addition of isLoad and isStore flags to the instruction .td file
for eventual use in a scheduler.
3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
that we can emit the PowerPC shifted immediate instructions far more
often. This allows us to emit the following code:
int foo(int x) { return x | 0x00F0000; }
_foo:
.LBB_foo_0: ; entry
; IMPLICIT_DEF
oris r3, r3, 15
blr
llvm-svn: 16826
2004-10-07 22:30:03 +00:00
c6b63cd2ed
Add ori reg, reg, 0 as a move instruction. This can be generated from
...
loading a 32bit constant into a register whose low halfword is all zeroes.
We now omit the ori after the lis for the following C code:
int bar(int y) { return y * 0x00F0000; }
_bar:
.LBB_bar_0: ; entry
; IMPLICIT_DEF
lis r2, 15
mullw r3, r3, r2
blr
llvm-svn: 16825
2004-10-07 22:26:12 +00:00
70a9d9c0b1
Remove unnecessary header include
...
llvm-svn: 16824
2004-10-07 22:24:32 +00:00
f94f985bbd
Correct some typeos
...
llvm-svn: 16770
2004-10-06 16:28:24 +00:00
9a1fbaf1e9
Turning on fsel code gen now that we can do so would be good.
...
llvm-svn: 16765
2004-10-06 11:03:30 +00:00
fac8529df8
Implement floating point select for lt, gt, le, ge using the powerpc fsel
...
instruction.
Now, rather than emitting the following loop out of bisect:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f4
bge .LBB_main_64 ; no_exit.0.i
.LBB_main_63: ; no_exit.0.i
b .LBB_main_65 ; no_exit.0.i
.LBB_main_64: ; no_exit.0.i
fmr f2, f1
.LBB_main_65: ; no_exit.0.i
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f5
bge .LBB_main_67 ; no_exit.0.i
.LBB_main_66: ; no_exit.0.i
b .LBB_main_68 ; no_exit.0.i
.LBB_main_67: ; no_exit.0.i
fmr f4, f1
.LBB_main_68: ; no_exit.0.i
fadd f1, f2, f4
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fcmpu cr0, f4, f0
bgt .LBB_main_70 ; no_exit.0.i
.LBB_main_69: ; no_exit.0.i
b .LBB_main_71 ; no_exit.0.i
.LBB_main_70: ; no_exit.0.i
fmr f0, f4
.LBB_main_71: ; no_exit.0.i
fsub f1, f2, f1
addi r2, r2, -1
fcmpu cr0, f1, f3
blt .LBB_main_73 ; no_exit.0.i
.LBB_main_72: ; no_exit.0.i
b .LBB_main_74 ; no_exit.0.i
.LBB_main_73: ; no_exit.0.i
fmr f3, f1
.LBB_main_74: ; no_exit.0.i
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
We emit this instead:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
fsel f1, f1, f1, f2
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f2, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f2
fsel f2, f2, f2, f4
fadd f1, f1, f2
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fsub f5, f0, f4
fsel f0, f5, f0, f4
fsub f1, f2, f1
addi r2, r2, -1
fsub f2, f1, f3
fsel f3, f2, f3, f1
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
llvm-svn: 16764
2004-10-06 09:53:04 +00:00
2f1d0ae95e
Generate better code by being far less clever when it comes to the select instruction. Don't create overlapping register lifetimes
...
llvm-svn: 16580
2004-09-29 05:00:31 +00:00
7b6df6def2
improve Type::BoolTy codegen by eliminating unnecessary clears and sign extends
...
llvm-svn: 16578
2004-09-29 03:45:33 +00:00
26566f0b68
To go along with sabre's improved InstCombining, improve recognition of
...
integers that we can use as immediate values in instructions.
Example from yacr2:
- lis r10, -1
- ori r10, r10, 65535
- add r28, r28, r10
+ addi r28, r28, -1
addi r7, r7, 1
addi r9, r9, 1
b .LBB_main_9 ; loopentry.1.i214
llvm-svn: 16566
2004-09-29 02:35:05 +00:00
8656a156cf
Correct some BuildMI arguments for the upcoming simple scheduler
...
llvm-svn: 16519
2004-09-27 05:08:17 +00:00
49cf74b26c
Fix the last of the major PPC GEP folding deficiencies. This will allow
...
the ISel to use indexed and non-zero immediate offsets for GEPs that have
more than one use. This is common for instruction sequences such as a load
followed by a modify and store to the same address.
llvm-svn: 16493
2004-09-23 05:31:33 +00:00
033b816171
add optimized code sequences for setcc x, 0
...
llvm-svn: 16478
2004-09-22 04:40:25 +00:00
6b17bf7193
s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the
...
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16471
2004-09-21 18:22:33 +00:00
87201ce8f9
s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the
...
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16470
2004-09-21 18:22:19 +00:00
e8e81a2941
Revamp the Register class, and allow the use of the RegisterGroup class to
...
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
54bcf2db01
Add 64 bit divide instructions, and use them
...
llvm-svn: 16198
2004-09-06 18:46:59 +00:00
175fdd4678
* Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared between
...
Darwin and AIX and is not 32- or 64-bit specific
* Bring back PowerPC.td as a result, to make it use the `PowerPC' class name
* Adjust Makefile accordingly
llvm-svn: 16174
2004-09-05 02:42:44 +00:00
4acadb3af7
Renamed PPC32AsmPrinter.cpp => PowerPCAsmPrinter.cpp as the Darwin and AIX asm
...
printers are now unified into one file.
llvm-svn: 16173
2004-09-05 02:27:37 +00:00
4d847047a0
Include MathExtras.h to fix build breakage, thanks to Vladimir
...
llvm-svn: 16164
2004-09-04 14:51:26 +00:00
4bfceb1ed5
All PPC instructions are now auto-printed
...
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
llvm-svn: 16163
2004-09-04 05:00:00 +00:00
6173878304
Convert remaining X-Form and Pseudo instructions over to asm writer
...
llvm-svn: 16142
2004-09-02 08:13:00 +00:00
7c16caa336
Changes For Bug 352
...
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
a113d74e4c
convert M and MD form instructions to generated asm writer
...
llvm-svn: 16121
2004-08-31 02:28:08 +00:00
143cf94f92
Move yet more instructions over to being printed by the generated asm writer
...
llvm-svn: 16112
2004-08-30 02:28:06 +00:00
6cdbd22245
Convert A-Form instructions to auto-generated asm writer
...
llvm-svn: 16107
2004-08-29 22:45:13 +00:00
8cb6bd5f3c
Improvements to int->float cast code for PPC-64
...
llvm-svn: 16105
2004-08-29 22:02:43 +00:00
4483df8b63
Implement the following missing functionality in the PPC backend:
...
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite. Fixes Regression/casts
llvm-svn: 16081
2004-08-29 08:19:32 +00:00
fa2bf42539
Register sizes are in bits, not bytes
...
llvm-svn: 16070
2004-08-27 04:28:10 +00:00
1c57b4fa32
Kill a majority of unnecessary sign extensions for byte loads
...
llvm-svn: 15991
2004-08-22 08:10:15 +00:00
64ef0262bd
Don't hard code the offset of the saved R31 in functions with frame pointers
...
llvm-svn: 15990
2004-08-22 08:09:17 +00:00
45b0b7cd7c
Back out branchless SetCC code. While it helped a lot in some cases, it
...
hurt a lot in others. Instead, improve branching version of SetCC and
Select instructions. The old code will be in CVS should we ever need to
dig it up again.
llvm-svn: 15979
2004-08-21 20:42:14 +00:00
70efc8f8e1
Switch from bytes to bits for alignment.
...
Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit
llvm-svn: 15975
2004-08-21 20:14:40 +00:00
c1ba9fb6e1
Reduce uses of getRegClass
...
llvm-svn: 15968
2004-08-21 19:51:17 +00:00
f7833ba375
Fix warning
...
llvm-svn: 15964
2004-08-21 19:11:03 +00:00
3ad3ad4f3f
Move XForm instructions over to the auto-generated asm writer
...
llvm-svn: 15962
2004-08-21 05:56:39 +00:00
abf3c4d787
remove some things from the todo list.
...
llvm-svn: 15956
2004-08-20 18:46:54 +00:00
f1cd650251
Do not register ppc64 yet, as it breaks the SparcV9 backend
...
llvm-svn: 15955
2004-08-20 18:09:18 +00:00
1b1a784afa
Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file.
...
llvm-svn: 15952
2004-08-20 09:56:22 +00:00
8f12956327
Fix opcodes being printed in caps (the more general fix may be `AsmWriter')
...
llvm-svn: 15932
2004-08-19 21:56:12 +00:00
170943a795
Stack space for argument passing is 32 regardless of 32- vs. 64-bit arch.
...
Thanks to Nate Begeman for pointing this out.
llvm-svn: 15930
2004-08-19 21:51:19 +00:00
f73c87b36c
LR needs to be saved at 16-byte offset on a 64-bit arch
...
llvm-svn: 15929
2004-08-19 21:36:14 +00:00
f35b35a926
On 64-bit PowerPC, pointers are 8 bytes, so parameter area offset is 48, not 24
...
llvm-svn: 15928
2004-08-19 21:34:05 +00:00
75e987d0b8
This PHI has 4 additional operands, not 2.
...
llvm-svn: 15926
2004-08-19 21:00:12 +00:00
a26a61aa18
Use the appropriate 64-bit register description file.
...
llvm-svn: 15922
2004-08-19 19:36:57 +00:00
a5543ac5fb
Fix more remaining 32-bit vestiges of PowerPC
...
llvm-svn: 15919
2004-08-19 18:49:58 +00:00
2ff719f74f
Fix another vestige of the 32-bit PowerPC backend.
...
llvm-svn: 15918
2004-08-19 16:50:30 +00:00
714d166c22
Correct character prepended to global symbols ('.'), use Mangler consistently
...
llvm-svn: 15917
2004-08-19 16:33:56 +00:00
0010ea3042
* Eliminate global base register, r2 is used for that on AIX/PowerPC
...
* Fix bug from 32-bit PowerPC days of 2-register long split
llvm-svn: 15916
2004-08-19 16:29:25 +00:00
6c4a085286
Wrap long lines.
...
llvm-svn: 15915
2004-08-19 16:28:30 +00:00
d5c6380015
Convert casts that will have no effect into move instructions.
...
llvm-svn: 15914
2004-08-19 08:07:50 +00:00
e4e6d92d1d
Clean up floating point instruction selection.
...
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter
llvm-svn: 15913
2004-08-19 05:20:54 +00:00
10262ab3f1
Rename var
...
llvm-svn: 15897
2004-08-18 02:22:55 +00:00
faa6e51d6e
This file is no longer used.
...
llvm-svn: 15893
2004-08-17 20:23:33 +00:00
2501f5852a
Start using alignment output routines from AsmPrinter.
...
Changes to make this more similar to the X86 asmprinter
Fix overalignment of globals.
llvm-svn: 15891
2004-08-17 19:26:03 +00:00
cc21bfd809
Print comments with ;
...
llvm-svn: 15881
2004-08-17 16:27:26 +00:00
0818541631
Re-fix hiding the Frame Pointer from the register allocator in functions
...
that have a frame pointer. This change fixes Burg. In addition, make
the necessary changes to floating point code gen and constant loading after
Chris Lattner's fixes to the asm writer. These changes fix MallocBench/gs
llvm-svn: 15873
2004-08-17 07:17:44 +00:00
f97bce7214
Use the emitGlobalConstant defined in AsmPrinter
...
llvm-svn: 15869
2004-08-17 06:37:12 +00:00
ac253447d3
New, more general, interface.
...
llvm-svn: 15866
2004-08-17 06:07:43 +00:00
9254441cdf
Rewrite targets/rules to generate files for just PowerPC or PPC{32,64}
...
llvm-svn: 15862
2004-08-17 05:11:54 +00:00
4eab7f3d5b
Register classes are target-dependent
...
llvm-svn: 15861
2004-08-17 05:10:31 +00:00
851a54656a
#include <map> is not necessary here
...
llvm-svn: 15860
2004-08-17 05:09:39 +00:00
fd2df5afab
`PowerPC' is no longer a real target
...
llvm-svn: 15859
2004-08-17 05:09:10 +00:00
38c61506a8
Move variables and methods which need PPC{32,64}* distinction to subclasses
...
llvm-svn: 15858
2004-08-17 05:08:44 +00:00
ba7fe16dbf
No need for an `is64bit' flag
...
llvm-svn: 15857
2004-08-17 05:06:47 +00:00
fe3e46a0b3
PowerPCInstrInfo and PowerPCRegisterInfo have gone away; they are replaced
...
by 32- and 64-bit customized files, named appropriately.
llvm-svn: 15856
2004-08-17 05:05:00 +00:00
de4fc10733
Consistently name passed with 32 or 64 in their name
...
llvm-svn: 15855
2004-08-17 05:02:58 +00:00
68ede7e9ba
PowerPCRegisterInfo no longer takes a bool to differentiate 32 vs 64 bits
...
llvm-svn: 15854
2004-08-17 05:02:18 +00:00
d61283f347
The PowerPCInstrInfo class has gone away.
...
llvm-svn: 15853
2004-08-17 05:00:46 +00:00
0674182457
PowerPCInstrInfo has gone away, PPC32 and PPC64 share opcodes.
...
llvm-svn: 15852
2004-08-17 04:58:50 +00:00
ac0ae7c215
PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC
...
llvm-svn: 15851
2004-08-17 04:57:37 +00:00
116f9277f6
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
...
llvm-svn: 15850
2004-08-17 04:55:41 +00:00
a8fbbc0ec3
Print float constants as 4 byte values.
...
Also, fix endianness problems when cross compiling from little-endian host.
llvm-svn: 15847
2004-08-17 02:48:44 +00:00
bc9372bf77
Make sure to put an _ prefix on all identifiers!
...
Also, add some (currently disabled) code to print float's as 32-bits.
llvm-svn: 15846
2004-08-17 02:29:00 +00:00
5491774934
More changes to make PPC32 and X86 more similar
...
llvm-svn: 15842
2004-08-16 23:38:36 +00:00
b4f1f71bf0
Minor changes to make the diff be nothing against the X86 version
...
llvm-svn: 15841
2004-08-16 23:30:16 +00:00
0ced90583d
Finegrainify namespacification
...
Start using the AsmPrinter base class to factor out a bunch of code
llvm-svn: 15840
2004-08-16 23:25:21 +00:00
f2e9ea2106
There is no need for a cast here
...
llvm-svn: 15810
2004-08-16 05:09:58 +00:00
ab6b08d937
Update the current state of the world
...
llvm-svn: 15809
2004-08-16 05:06:43 +00:00
a6808b8efc
Fix typo of the word 'implicit' I made resolving a CVS conflict. Whoops!
...
llvm-svn: 15808
2004-08-16 02:12:49 +00:00
dabf0a52c0
Fix frame pointer handling:
...
Reserve R0 in store/load from stack slot for building >32k offsets from SP
or FP. This also requires we use R11 rather than R0 for holding the LR
value we want to save or restore. Also, tell the register allocator not
to use R31 (our FP) in functions that have a frame pointer. These changes
fix Burg.
llvm-svn: 15807
2004-08-16 01:52:12 +00:00
8b44a07246
Fix mismatched adjust down/up of SP in functions that contain variable
...
sized allocas.
llvm-svn: 15806
2004-08-16 01:50:22 +00:00
48a3b942ae
Insertion methods now return void instead of #instrs inserted. Also, use
...
more powerful forms of BuildMI to concisify the code
llvm-svn: 15782
2004-08-15 22:15:56 +00:00
98de1d7795
These methods no longer take a TargetRegisterClass* operand.
...
llvm-svn: 15774
2004-08-15 21:56:44 +00:00
4922e2e8ef
Make this compile on gc 3.4.1 (static_cast to non-const type was not
...
allowed).
llvm-svn: 15766
2004-08-15 09:18:55 +00:00
78862c3717
Add future optimization opportunity
...
llvm-svn: 15760
2004-08-15 06:43:10 +00:00
373744c6dc
Fix float to int codepath by always allocating 8 bytes for the target of a double store; optimize cmplwi generation.
...
llvm-svn: 15759
2004-08-15 06:42:28 +00:00
7dfaac4300
Zimm16 is now dead. Its entry is not removed from the enum, to avoid having
...
to renumber everything. Similar elimination should be applied to other
operand enum values that are only used to format printing in the .s file.
llvm-svn: 15755
2004-08-15 05:48:47 +00:00
da2e56fb0c
Convert all of the DForm_6* operations, which makes all of the Zimm16 users
...
dead.
llvm-svn: 15754
2004-08-15 05:46:14 +00:00
94ab6273b6
Reenable the CCRC
...
llvm-svn: 15752
2004-08-15 05:31:15 +00:00
8a796858da
Convert the DForm_4 over to the asmprintergen
...
llvm-svn: 15751
2004-08-15 05:20:16 +00:00
abc8173b18
Remove dead code
...
llvm-svn: 15750
2004-08-15 00:31:02 +00:00
ec1cc1b861
Print mflr using the asmwriter generator
...
llvm-svn: 15749
2004-08-14 23:27:29 +00:00
412602d7d9
Replace PowerPCPEI.cpp with target independant PrologEpilogInserter
...
llvm-svn: 15746
2004-08-14 22:16:36 +00:00
0c8c0346f8
Add support for frame pointers, and large offsets from stack and frame pointers. Adopt elimination of MachineFunction& arg from eliminateFrameIndex.
...
llvm-svn: 15745
2004-08-14 22:13:58 +00:00
9c7ddc3e21
Add indexed forms of load doubleword and load word algebraic for 64 bit targets
...
llvm-svn: 15743
2004-08-14 22:12:20 +00:00
caeb78e720
Fix handling of FP constants with single precision, and loading of internal linkage function addresses
...
llvm-svn: 15742
2004-08-14 22:11:38 +00:00
0ad7f813d8
Add initial support for using the generated asm writer. Also, fix FP constant printing to always print 8 byte intializers. Move printing of LinkOnce stubs.
...
llvm-svn: 15741
2004-08-14 22:09:10 +00:00
8536df7dbe
Add generation of asm writer from tablegen files to Makefile
...
llvm-svn: 15740
2004-08-14 22:06:38 +00:00
6e5010d935
Remove an unneeded header and forward declaration
...
llvm-svn: 15722
2004-08-13 09:33:17 +00:00
5bf9bfe398
Fix siod by switching BoolTy to byte rather than int until CFE changes for
...
Darwin. Also, change asm printer to output proper stubs for external
functions whose address is passed as an argument to aid in bugpointing.
llvm-svn: 15721
2004-08-13 09:32:01 +00:00
420213f3c5
Fix 177.mesa compilation, don't use floating point regs for base addresses!
...
llvm-svn: 15720
2004-08-13 04:45:14 +00:00
2f1d849271
Fix llc crasher compiling siod by giving BuildMI the correct number of arguments
...
llvm-svn: 15719
2004-08-13 03:56:49 +00:00
2e8bfa2364
Longs are in one register on PowerPC 64; use appropriate instructions to operate on them.
...
llvm-svn: 15711
2004-08-13 02:20:47 +00:00
765cb5f844
Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files
...
llvm-svn: 15710
2004-08-13 02:19:26 +00:00
af77fe4097
Disable PPC64 backend by default because LLC cannot choose automatically between
...
SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.
llvm-svn: 15688
2004-08-12 17:16:43 +00:00
52a4abc299
* Correct 64-bit version: blr 1 (not 0)
...
* BuildMI() can build 0-param instructions (e.g., NOP)
llvm-svn: 15681
2004-08-12 03:30:03 +00:00
5d967b3c5e
* Print out full names for non-GPR or -FPR registers
...
* BuildMI() really *does* handle 0 params!
llvm-svn: 15680
2004-08-12 03:28:47 +00:00
58040a63ee
* Pointers are 8 bytes, hence cLong type on 64-bit PPC
...
* Fix loading of GlobalValues
llvm-svn: 15678
2004-08-12 02:53:01 +00:00
6f2e67a726
Eliminate special-casing 14-bit immediate load/store opcodes
...
llvm-svn: 15677
2004-08-12 02:51:38 +00:00
5098bd5499
Correctly print out ASCII literal strings on AIX
...
llvm-svn: 15674
2004-08-12 01:01:13 +00:00
345399b06e
Mark R2 as available for allocation on Darwin/PPC32, but not AIX/PPC64
...
llvm-svn: 15673
2004-08-12 00:10:01 +00:00
c94c0f75f4
* Move AIX into the llvm namespace to be accessed from RegisterInfo
...
* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer
llvm-svn: 15672
2004-08-11 23:47:08 +00:00
aea37d65c8
Set the is64bit flag and propagate it to PowerPCRegisterInfo
...
llvm-svn: 15671
2004-08-11 23:45:43 +00:00
39f7533b40
* Set the is64bit boolean flag in PowerPCRegisterInfo
...
* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX
llvm-svn: 15670
2004-08-11 23:44:55 +00:00
c2a043488a
64-bit instruction selector and AIX-specific 64-bit asm printer
...
llvm-svn: 15669
2004-08-11 23:42:15 +00:00
d7344dc9bd
Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes
...
llvm-svn: 15668
2004-08-11 23:33:34 +00:00
78c1dcfc3e
Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes
...
llvm-svn: 15667
2004-08-11 20:56:14 +00:00
28beda9ba4
Add doubleword load/store (64-bit only).
...
llvm-svn: 15665
2004-08-11 15:54:36 +00:00
7224ee1e4c
Hyphenate ##-bit and remove first-person from comments.
...
llvm-svn: 15663
2004-08-11 13:35:44 +00:00
f17ea0f7b7
Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer.
...
llvm-svn: 15662
2004-08-11 07:40:04 +00:00
6f0291792e
Fix a case where constantexprs could leak into the PPC isel.
...
llvm-svn: 15661
2004-08-11 07:34:50 +00:00
7526da6ead
Fix 255.vortex by using getClassB instead of getClass
...
llvm-svn: 15648
2004-08-11 03:30:55 +00:00
e67a212267
Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest.
...
llvm-svn: 15636
2004-08-11 00:11:25 +00:00
284086aa4a
Breaking up the PowerPC target into 32- and 64-bit subparts: Part II: 64-bit.
...
llvm-svn: 15635
2004-08-11 00:10:41 +00:00
d022a5ac5a
Breaking up the PowerPC target into 32- and 64-bit subparts, Part I: 32-bit.
...
llvm-svn: 15634
2004-08-11 00:09:42 +00:00
dad438bfb9
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
...
llvm-svn: 15631
2004-08-10 22:47:03 +00:00
0b9444e536
* Fix file header to use tablegen emacs mode instead of c++
...
* Wrap long line to 80 cols
llvm-svn: 15630
2004-08-10 21:24:44 +00:00
63be70d8f2
Fix casts of float to unsigned long
...
Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases
llvm-svn: 15626
2004-08-10 20:42:36 +00:00
c6b114f258
DForm 5/6 extended mneumonics take 3 arguments.
...
llvm-svn: 15620
2004-08-10 19:03:31 +00:00
09d87b4939
Fix DForm_4: format is `op r, r, i'
...
llvm-svn: 15613
2004-08-10 18:07:55 +00:00
189229151f
Stub definition of the PowerPC CodeEmitter class; this isn't functional (yet).
...
llvm-svn: 15600
2004-08-09 23:03:59 +00:00
eca36a5aa0
CodePrinter -> AsmPrinter
...
llvm-svn: 15599
2004-08-09 22:27:45 +00:00
8f951e579b
Remove ClassPrefix variable as it's no longer used.
...
llvm-svn: 15586
2004-08-09 19:13:29 +00:00
d210ed1855
Define a ClassPrefix for PowerPC.
...
llvm-svn: 15580
2004-08-09 17:46:26 +00:00
b3401c4c50
Generate a code emitter for PowerPC as well, this will be used in the JIT.
...
llvm-svn: 15578
2004-08-09 17:24:32 +00:00
5295e1db10
Use instruction formats as defined in the PowerPC ISA manual
...
llvm-svn: 15577
2004-08-09 17:24:04 +00:00
42817b7ea1
Fix stack size processing now that the return address isn't an implied
...
push onto the top of the stack like x86, which uses the local area
offset. This will allow the removal of PowerPCPEI.cpp soon.
llvm-svn: 15573
2004-08-09 01:24:32 +00:00
a8dcf2423e
Changes commited for Nate Begeman:
...
Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals
Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp
llvm-svn: 15536
2004-08-06 06:58:50 +00:00
2fc39a9c2f
Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I
...
assume Louis also holds copyright.
llvm-svn: 15534
2004-08-05 23:46:27 +00:00
e7ccf6445e
Add additional copyright notice for the PowerPC backend.
...
Thanks Nate!
llvm-svn: 15531
2004-08-05 20:36:00 +00:00
7d41ed5271
Simplify makefile by combining all TableGen dependencies into one variable
...
llvm-svn: 15527
2004-08-05 18:34:15 +00:00
2068654d68
Align dependencies so they don't hurt the eyes to look at them
...
llvm-svn: 15504
2004-08-04 21:37:41 +00:00
cdd72aaa1f
Remove unused instruction classes
...
llvm-svn: 15501
2004-08-04 21:18:57 +00:00
f74157ab15
Make tablegen targets depend on PowerPCInstrFormats.td as well
...
llvm-svn: 15500
2004-08-04 21:18:36 +00:00
08c58e63d9
getValues does not exist
...
llvm-svn: 15495
2004-08-04 17:29:14 +00:00
8a1978fd72
Remove unused opcodes.
...
llvm-svn: 15447
2004-08-03 20:23:44 +00:00
570dcf63e6
* Use simpler instruction templates to define instructions
...
* Fix several extended opcodes
llvm-svn: 15423
2004-08-02 21:58:52 +00:00
6b21bde2d6
Replace patterns 0, 4, and 5 with simpler heirarchical definitions that use the
...
official PowerPC instruction format lingo: X- and D-form.
llvm-svn: 15422
2004-08-02 21:56:35 +00:00
cd4f51b4b6
Separate instruction formats from instruction definitions.
...
llvm-svn: 15414
2004-08-02 16:54:54 +00:00
695d50d030
* Conditional save/restore of LR disabled as it's not quite correct
...
* sumarray2d fixed: large fixed-size alloca
* make is now compileable
* Re-organized tests to fit them under proper headings
Patch by Nate Begeman.
llvm-svn: 15347
2004-07-30 15:53:09 +00:00
c102577ff1
Do not mark LR as callee-save: not quite correctly done. Patch: Nate Begeman.
...
llvm-svn: 15346
2004-07-30 15:51:51 +00:00
471b43a357
* Temporarily suspend LR save/restore optimization as it is not quite correct
...
* Implement large fixed-size allocas Entire patch by Nate Begeman.
llvm-svn: 15345
2004-07-30 15:50:45 +00:00
07fad1cdee
Minor corrections
...
llvm-svn: 15309
2004-07-28 20:18:53 +00:00
7f01b2539b
Add notes on bug involving casting ulong -> double, thanks to Nate Begeman.
...
llvm-svn: 15307
2004-07-28 19:16:10 +00:00
862bb562cc
Simplify loading (un)signed constants to registers, patch by Nate Begeman.
...
llvm-svn: 15306
2004-07-28 19:13:49 +00:00
db13b6edba
Remove an extra 8 byte distance penalty. Patch by Nate Begeman.
...
llvm-svn: 15305
2004-07-28 19:13:07 +00:00
ca5880025d
Find longs by type, not by their primitive size being 64. Patch by Nate Begeman.
...
llvm-svn: 15304
2004-07-28 19:12:24 +00:00
f7037385e2
LI can only take signed values, so values > 32767 can only be loaded with ORI
...
llvm-svn: 15299
2004-07-28 00:56:04 +00:00
bd1d7dceb7
Reorganize tests to place them in proper directories.
...
llvm-svn: 15298
2004-07-28 00:55:12 +00:00
04dee3bb66
UnitTests 2003-05-26-Shorts and 2003-07-09-LoadShorts have been fixed;
...
2003-05-22-VarSizeArray is broken.
llvm-svn: 15297
2004-07-28 00:01:41 +00:00
47d5a22f8b
Fix printing of immediate operands by looking at their operand types in
...
the TargetInstrInfo. This fixes UnitTests 2003-05-26-Shorts and
2003-07-09-LoadShorts.
llvm-svn: 15296
2004-07-28 00:00:48 +00:00
92ca8eccd8
Renamed files:
...
* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
llvm-svn: 15295
2004-07-27 23:29:16 +00:00
2ffb787446
Branch selection support implemented by Nate Begeman for long branches.
...
llvm-svn: 15288
2004-07-27 18:43:04 +00:00
a594740016
Correctly print out long branches, assert on finding pseudo instr COND_BRANCH
...
Patch by Nate Begeman.
llvm-svn: 15286
2004-07-27 18:40:39 +00:00
09396bf158
Run the branch selection pass right before the asm printer.
...
Patch by Nate Begeman.
llvm-svn: 15285
2004-07-27 18:39:34 +00:00
4d66925aea
Remove empty unused method processFunctionBeforeFrameFinalized()
...
llvm-svn: 15284
2004-07-27 18:38:40 +00:00
83df71af70
Add COND_BRANCH pseudo instruction, patch by Nate Begeman.
...
llvm-svn: 15283
2004-07-27 18:35:54 +00:00
5b092c15c6
Build COND_BRANCHes which may become long or short, decided by a later pass.
...
Patch by Nate Begeman.
llvm-svn: 15282
2004-07-27 18:35:23 +00:00
a783ee55a9
Moved definition of invertPPCBranchOpcode() into PowerPCInstrInfo class.
...
Patch by Nate Begeman.
llvm-svn: 15281
2004-07-27 18:34:11 +00:00
ef8cf023a0
Add PowerPCBranchSelector to discover which are `long' branches.
...
Contributed by Nate Begeman.
llvm-svn: 15280
2004-07-27 18:33:06 +00:00
9eaa879f49
Fixed saving/restoring LR unconditionally, only done as necessary.
...
llvm-svn: 15275
2004-07-27 17:17:48 +00:00
bc1a2f96a6
Save and restore LR just like any other register and ONLY if we actually modify
...
it (due to calls or globals access). We now compile `void empty(){}' to `blr'.
llvm-svn: 15274
2004-07-27 17:17:18 +00:00
26978c3730
LR is a 32-bit int reg
...
llvm-svn: 15273
2004-07-27 17:15:32 +00:00
f1a7e941fb
MovePCtoLR (which is `bl' in disguise) modifies LR implicitly
...
llvm-svn: 15272
2004-07-27 17:15:05 +00:00
2bcffa484b
Register LR is callee-saved
...
llvm-svn: 15271
2004-07-27 17:14:34 +00:00
640ec1e5e6
Add IMPLICIT_DEF of LR for branch-and-link instrs (calls and global accesses)
...
llvm-svn: 15270
2004-07-27 17:13:58 +00:00
b5ed14486b
Do not store the stack pointer if the stack size is 0.
...
Also, convert C-style comments to C++ and make sure code wraps at 80 cols.
llvm-svn: 15245
2004-07-26 22:00:26 +00:00
58499ead7d
ADDI can take several forms, including:
...
addi r1, r2, 0
addi r1, <frame index #n>, 0
so we must check for the second parameter being a register for this instruction
to be considered a reg-to-reg copy.
llvm-svn: 15244
2004-07-26 21:50:38 +00:00
6c125a92d7
assert() on MachineInstr properties instead of checking them dynamically
...
llvm-svn: 15243
2004-07-26 21:35:58 +00:00
43f1c4045a
* Recognize `addi r1, r2, 0' a move instruction
...
* List formats of instructions currently recognized as moves
llvm-svn: 15242
2004-07-26 21:29:00 +00:00
74e3a17958
* Rewrote casts
...
* Implemented GEP folding
* Dynamically output global address stuff once per function
* Fix casting fp<->short/byte
Patch contributed by Nate Begeman.
llvm-svn: 15237
2004-07-26 18:13:24 +00:00
ed664f91a4
Increment the label number in runOnFunction() rather than while printing out
...
some instruction. Patch by Nate Begeman.
llvm-svn: 15236
2004-07-26 16:28:33 +00:00
d815472ebd
More notes on bugs, unimplemented features, and suggested code improvements.
...
Written by Nate Begeman.
llvm-svn: 15235
2004-07-26 16:23:55 +00:00
40f07ec771
Fix subtracting values > 2^15 in the prologue/epilogue, by Nate Begeman.
...
llvm-svn: 15234
2004-07-26 16:22:52 +00:00
8930d4f24e
Running list of bugs, unimplemented features, currently broken tests, until we
...
have a nightly tester set up for PowerPC.
llvm-svn: 15147
2004-07-23 22:37:22 +00:00
c150bdb52e
Eliminate spurious empty space; make code easier to page through.
...
llvm-svn: 15146
2004-07-23 22:35:49 +00:00
66c816a6a3
Simplify boolean test.
...
llvm-svn: 15145
2004-07-23 21:43:26 +00:00
26a04b79cb
Implement casting a floating point to 32-bit unsigned value
...
llvm-svn: 15143
2004-07-23 20:32:59 +00:00
7dba17d1ce
* Codegen of GEPs dramatically improved by folding multiplies and adds
...
* Function pointers implemented correctly using appropriate stubs
Contributed by Nate Begeman.
llvm-svn: 15133
2004-07-23 16:08:20 +00:00
4fb48609dc
Bool alignment on MacOSX/PowerPC is 4 bytes.
...
llvm-svn: 15122
2004-07-23 01:11:46 +00:00
db72025d1d
* Change class of BoolTy back to cInt
...
* Fix indentation back to 2 spaces
llvm-svn: 15121
2004-07-23 01:11:19 +00:00
333f58836c
* Change bool from cInt to cByte (for now)
...
* Don't allow negative immediates to users of unsigned immediates
* Fix long compares
* Support <const int>, op as a potential immediate candidate
* Fix sign extension of short and byte loads
* Fix and improve integer casts
* Fix passing of doubles as vararg functions
Patch contributed by Nate Begeman.
llvm-svn: 15109
2004-07-22 15:58:04 +00:00
dbd14bc3e5
* Add the lost fix to define the second reg of a 2-reg representation of longs
...
* Fix opcode RLWNM -> RLWINM since it uses an immediate const shift value
llvm-svn: 15087
2004-07-21 20:30:18 +00:00
87e07f8596
* Speed up canUseAsImmediateForOpcode() by comparing Operand before
...
dyn_cast<>ing and checking Constant's value
* Convert tabs to spaces
llvm-svn: 15086
2004-07-21 20:22:06 +00:00
8d75aa4475
* Fix printing of signed immediate values (Nate Begeman)
...
* Fix printing of `zeroinitializer'
* Fix printing of `linkonce' globals, complete with stubs
llvm-svn: 15084
2004-07-21 20:11:11 +00:00
072af37088
* Fix printing of signed immediate values
...
* Generation of opcodes that take 16 bit immediates
* Rewrote multiply to be correct for 64 bit values
* Rewrote all the long handling to be correct for PowerPC
* Fix visitSelectInst() to define the upper register of the pair of regs
representing a long value
Patch contributed by Nate Begeman.
llvm-svn: 15083
2004-07-21 20:09:08 +00:00
455622577a
Use addSImm() instead of addImm() for stack offsets, which may be negative.
...
llvm-svn: 15081
2004-07-21 19:36:57 +00:00
984bfdc702
Add SUBI instruction
...
llvm-svn: 15077
2004-07-21 15:53:04 +00:00
75f3291ef3
Shorts are aligned to 2 bytes, bools to 1 byte (in structs).
...
llvm-svn: 15048
2004-07-20 20:59:57 +00:00
8e36261aa8
Treat external variables similarly to those with weak linkage: load indirect.
...
llvm-svn: 15047
2004-07-20 20:43:05 +00:00
4aab086eda
Differentiate between global and weak symbol loads
...
llvm-svn: 15037
2004-07-20 15:52:25 +00:00
684ef6ca20
* Differentiate between global and weak symbol loads
...
* Fix functions that take more than 32 bytes of args
* Alignment of doubles in structs is 4 bytes, not 8
* Fix passing long args: rN = hi, rN+1 = lo
* Rewrite signed divide
* Rewrite Intrinsic::returnaddress
Patch courtesy of Nate Begeman.
llvm-svn: 15036
2004-07-20 15:51:37 +00:00
42666aed5e
Differentiate between global and weak symbol loads
...
llvm-svn: 15035
2004-07-20 15:45:27 +00:00
dff882a230
Double alignment in structs is 4 bytes, not 8. Patch by Nate Begeman.
...
llvm-svn: 15034
2004-07-20 15:43:25 +00:00
e036ff8b32
Fix stack frame layout in prologue/epilogue. Patch courtesy of Nate Begeman.
...
llvm-svn: 15026
2004-07-20 02:23:09 +00:00
5e744fa1a3
Move handing of GlobalValues from getReg() to copyConstantToRegister(), this
...
will avoid extra register-to-register copies. Thanks to Chris for the idea.
llvm-svn: 15019
2004-07-20 00:59:38 +00:00
22802cc6cd
* Fn args passed in registers are now recorded as used by the call instruction
...
`-> asm printer updated to not print out those registers with the call instr
All of Shootout tests now work. Great thanks to Nate Begeman for the patch!
llvm-svn: 15015
2004-07-20 00:42:19 +00:00
818a9dc317
* cFP class split into cFP32 and cFP64
...
* Fn args passed in registers are now recorded as used by the call instruction
`-> asm printer updated to not print out those registers with the call instr
* Stack frame layout in prolog/epilog fixed, spills and vararg fns now work
* float/double to signed int codegen now correct
* various single precision float codegen bugs fixed
* const integer multiply codegen fixed
* select and setcc blocks inserted into the correct place in machine CFG
* load of integer constant code optimized
All of Shootout tests now work. Great thanks to Nate Begeman for the patch!
llvm-svn: 15014
2004-07-20 00:41:46 +00:00
6bdfbaf80d
Fix infinite loop
...
llvm-svn: 14971
2004-07-18 18:45:01 +00:00
aba6c47900
CPR Fixes
...
llvm-svn: 14961
2004-07-18 07:29:35 +00:00
e6f4a5ebb0
We don't really need to #include IPO.h into this file.
...
llvm-svn: 14911
2004-07-17 18:37:46 +00:00
b85c2522fa
* Use LI(S) to copy constants into registers intead of ADDI(S) as the latter is
...
a funky way to "use" R0 for a 0-valued operand
* Add IMPLICIT_DEFs for incoming function arguments via registers to help the
register allocator not clobber those registers
* Implement comparisons with longs
* Teach emitSelectOperation() to fold the SetCC operation
Patch contributed by Nate Begeman
llvm-svn: 14901
2004-07-16 21:06:24 +00:00
db032fb1f9
* Store all non-volatile int registers R13-31 on the stack, restore on exit
...
* Fix comment formatting
llvm-svn: 14900
2004-07-16 20:55:20 +00:00
780da8425f
Fix code formatting
...
llvm-svn: 14899
2004-07-16 20:54:25 +00:00
3adf84ba0d
Implement PowerPCInstrInfo::isMoveInstr(), patch by Nate Begeman
...
llvm-svn: 14898
2004-07-16 20:51:55 +00:00
f0def96a36
Add prototype for TargetInstrInfo::isMoveInstr()
...
llvm-svn: 14897
2004-07-16 20:50:55 +00:00
9c2c293225
* Enable allocation of registers r2-r10
...
* Allocate registers 13-31 backwards (to be able to store them all at once)
llvm-svn: 14896
2004-07-16 20:35:20 +00:00
6ed15fd181
Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman
...
llvm-svn: 14895
2004-07-16 20:33:41 +00:00
8c9938654a
The generated instruction selector isn't (yet) functional
...
llvm-svn: 14894
2004-07-16 20:31:13 +00:00
d4ac818593
* Output non-lazy linking stubs for external global variables
...
* Get rid of dead and #if 0'd code
* Minor for loop speed-up: save end iterator instead of querying every time
llvm-svn: 14893
2004-07-16 20:29:04 +00:00
a6b9a566b9
Define double alignment as 8 bytes now that assert(DoubleAlignment == PointerSize)
...
has been eliminated
llvm-svn: 14891
2004-07-16 19:32:12 +00:00
d350b64352
* Add spaces between words and numbers in comments printed out for longs/floats
...
* Print out IMPLICIT_DEFS as comments in the assembly, patch by Nate Begeman
llvm-svn: 14890
2004-07-16 19:01:13 +00:00
5ce1408537
Do IMPLICIT_DEFs on incoming args' hard regs, to avoid confusing the regalloc.
...
Support single-fp incoming args.
Support single-fp outgoing args ('call' operands).
Support double-fp return values.
llvm-svn: 14880
2004-07-16 10:31:25 +00:00
2453818b8a
The powerpc is now gone. However it is now just known as the Skeleton target.
...
llvm-svn: 14877
2004-07-16 07:14:34 +00:00
c9819f09c2
Revert stuff that I didn't mean to checkin
...
llvm-svn: 14844
2004-07-15 02:33:38 +00:00
7dc9de5f43
Patches towards fixing PR341
...
llvm-svn: 14841
2004-07-15 02:14:30 +00:00
2661c50173
Make sure MTSPR instruction is inserted into the BasicBlock
...
llvm-svn: 14822
2004-07-14 18:26:31 +00:00
5193410cd9
Don't define the same register twice when loading a ConstantPointerRef to a reg
...
llvm-svn: 14819
2004-07-14 17:57:04 +00:00
d4cbe67ce6
* Fix multiplication by powers of two and otherwise
...
* Clarify variable name (StoreInst SI instead of LI)
llvm-svn: 14818
2004-07-14 15:29:51 +00:00
aa678b5ed4
* Specify that FP arith options have 3 operands
...
* Correctly load FP constants from the constant pool, should be refactored
llvm-svn: 14799
2004-07-13 15:35:45 +00:00
be1b680f54
Correctly load FP constants out of the constant pool.
...
llvm-svn: 14782
2004-07-12 23:49:47 +00:00
dcb0eec80d
Implement getModuleMatchQuality and getJITMatchQuality() for PowerPC
...
llvm-svn: 14780
2004-07-12 23:36:12 +00:00
b889c6b261
Delete the allocate*TargetMachine function, which is now dead.
...
The shared command line options are now in a header that makes sense.
llvm-svn: 14757
2004-07-11 04:17:58 +00:00
c2726e63ed
Delete the allocate*TargetMachine function, which is now dead .
...
The shared command line options are now in a header that makes sense.
llvm-svn: 14756
2004-07-11 04:17:10 +00:00
73eb9436ee
Make these format a bit nicer
...
llvm-svn: 14747
2004-07-11 03:27:42 +00:00
4266f8017d
Auto-registrate target
...
llvm-svn: 14745
2004-07-11 02:48:49 +00:00
97c176b639
Add compilability
...
llvm-svn: 14744
2004-07-11 02:48:28 +00:00
82a065dc41
* Add support for indexing into structures, thanks to Chris (x86)
...
The large diff is because of indentation of a whole region
* Fix querying predecessor blocks in SelectPHINodes(), thanks to Brian (v8)
* Add support for external functions malloc() and free()
* Fix some code indentation
Remember, kids: It's not plagiarism if you "creatively borrow" from your
sources. It's called "research"!
llvm-svn: 14723
2004-07-09 15:45:07 +00:00
14d02cd2d8
Read/write the offset value for stack-relative loads via correct instr operand.
...
llvm-svn: 14722
2004-07-09 15:37:16 +00:00
aefab3404e
Add support for __fixdfdi(), __floatdisf(), and __floatdidf() external functions
...
llvm-svn: 14703
2004-07-08 19:41:16 +00:00
4c4e044e65
* Use several Function* for external functions instead of a std::map
...
* Non-const FP values must be loaded into int regs (for vararg fns) via memory
llvm-svn: 14701
2004-07-08 18:27:59 +00:00
59b2d4ef9d
* Add support for loading FP constants from the constant pool
...
* Load FP values into int regs as well for vararg functions; without memory ops!
llvm-svn: 14700
2004-07-08 18:02:38 +00:00
b604b4df21
* Fix header comment, excise references to X86
...
* Add suport for printing out references to constant pool indices
llvm-svn: 14699
2004-07-08 17:58:04 +00:00
3955f9079b
* Use a map for caching lookups to external functions (fp div/rem)
...
* Tabs to spaces
llvm-svn: 14673
2004-07-07 20:07:22 +00:00
6ff655117d
* Wrap long lines (comments and code)
...
* Tabs to spaces
llvm-svn: 14672
2004-07-07 20:01:36 +00:00
ef84814ea9
Add fmod() to the Module being compiled so that it gets a stub in the asm file
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llvm-svn: 14670
2004-07-07 15:36:18 +00:00
4556d889f4
* Add support for calling vararg functions (must pass doubles in int regs too)
...
* Make visitSetCondInst() share condition-generating code with EmitComparison()
* There are 13 FPRs for function-passing arguments, not 8
* Do not rely on registers being sequential, use an array lookup
* In unimplemented switch cases, send an error and abort instead of silent
fall-through
* Add doInitialization() for adding function prototypes for external math fns
* Minor changes: fix indentation, spacing, code clarity
llvm-svn: 14653
2004-07-06 22:51:53 +00:00
2138f1b2b0
Use the more compact `bl' instead of cryptic (but equivalent) `bcl 20,31'
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llvm-svn: 14652
2004-07-06 22:40:34 +00:00
e9b763a83f
* Add utility functions: convert SetCC => PPC opcode and invert PPC opcode
...
* If SetCondInst is folded into BranchInst (and it is the only user), do not
emit code for SetCondInst
* Fix assembly opcodes in comments in visitSetCondInst()
* Fix codegen of conditional branches
llvm-svn: 14643
2004-07-06 15:32:44 +00:00
4308baa0f1
Add FIXME notes for spilling int/fp regs (need to calculate stack space).
...
llvm-svn: 14581
2004-07-02 17:54:38 +00:00
3594324248
Fix all of those problems that the PPC backend has running 176.gcc :)
...
llvm-svn: 14565
2004-07-02 05:48:42 +00:00
24a0371791
* Follow the PowerPC convention of leaving 24 bytes for linking on the stack.
...
* Also leave space for spilling integer registers (this should be calculated)
llvm-svn: 14554
2004-07-01 21:35:00 +00:00
d028593c6e
* Get rid of constant-expr handling code: we use the ConstantExpr lowering pass
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* Use the SetCC handling code in the format of Brian's V8
* Add FIXMEs where calls to functions are being made without adding them to the
Module first... they cause missing symbols at assembly-time.
llvm-svn: 14553
2004-07-01 21:34:10 +00:00
1f3a7f0255
Wrap long line
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llvm-svn: 14552
2004-07-01 21:27:59 +00:00
d575287551
* Do not allocate r0 as we use it indiscriminantly in the instr selector.
...
* Do not define CR register class because we don't (yet) have the i4 type
llvm-svn: 14551
2004-07-01 21:24:50 +00:00
fcc59bd0e0
Check if operand has an allocated reg before requesting it.
...
llvm-svn: 14550
2004-07-01 21:09:12 +00:00
0648a903c7
* Coalesce the handy CALL* alias opcodes with the standard ones
...
* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls
llvm-svn: 14511
2004-06-30 22:00:45 +00:00
299fa1b147
* Allow more registers to be allocated from the general register pool
...
* Define the condition register class
llvm-svn: 14510
2004-06-30 21:54:50 +00:00
fee5a22f8a
* Inquire about the number of operands from the instruction directly
...
* Only check for a register if we are sure the instruction has one allocated
llvm-svn: 14509
2004-06-30 21:54:12 +00:00
2b9106f808
Always assume a function may have calls because the printer may add `bl' to get
...
the PC in a code sequence for global variables.
llvm-svn: 14506
2004-06-30 00:09:12 +00:00
351646f31e
* Don't save LR when outputting globals: it's already saved on the stack once
...
for the function
* Registers aren't necessarily sequential wrt their enums, don't rely on it
when emitting function arguments into sequential registers
* Remove X86-specific comments about AL/BL/AH/BH/EDX/etc
* Add an abort() for an unimplemented signed right shift
* The src operand for a GEP was never emitted! Fixed.
* We can skip zero-valued GEP indices as they are no-ops.
"Hello, World!" now works.
llvm-svn: 14505
2004-06-29 23:45:05 +00:00
c794feab51
* Stop using BBNumbering, we don't really need it
...
* Only increment labelNumber once, because it's used by both Load{hi,lo}Addr
* There is no .bss section on PowerPC
* Use .align 2 instead of other random numbers
llvm-svn: 14504
2004-06-29 23:40:57 +00:00
d409669877
Set up the prologue and epilogue to be more like the manual and GCC output.
...
llvm-svn: 14502
2004-06-29 23:38:26 +00:00
7454c6fff0
* Use LA instead of LWZ for LoadLoAddr
...
* Specify the isCall bit and caller-save registers for some call instrs
llvm-svn: 14501
2004-06-29 23:37:36 +00:00
5459dfb47b
Only allocate non-volatile registers R13-31 (for now).
...
llvm-svn: 14500
2004-06-29 23:35:32 +00:00
4efe3da794
Lower ConstantExpressions before the code generator.
...
llvm-svn: 14497
2004-06-29 23:33:20 +00:00
802403723b
* Fix saving LR in function prologue
...
* Adjust epilogue restore sequence to match the PowerPC documentation
llvm-svn: 14480
2004-06-29 17:14:42 +00:00
811f5c2c4c
Assembly syntax/comment fixes by Nate Begeman.
...
llvm-svn: 14479
2004-06-29 17:13:26 +00:00
c5f9b356af
The code generator should work with unreachable blocks. If not, then this
...
is a bug that should be fixed in the code generator, not papered over with
the simplifycfg pass. Eliminating this makes bugpoint much more useful
llvm-svn: 14477
2004-06-29 07:20:16 +00:00
15c10883ff
Can't print out machine code before it is constructed.
...
llvm-svn: 14472
2004-06-28 21:16:57 +00:00
3aad397726
Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman.
...
llvm-svn: 14470
2004-06-28 18:27:08 +00:00
767fa11096
Set isBranch and isTerminator bits on all branch instructions.
...
llvm-svn: 14469
2004-06-28 18:23:35 +00:00
2f0cda8b2a
Fix loading and storing PC-relative static variables, courtesy of Nate Begeman.
...
llvm-svn: 14468
2004-06-28 18:20:59 +00:00
75985d725c
No need to generate a lazy-linking stub for internal functions, they can be
...
resolved by the static linker.
llvm-svn: 14467
2004-06-28 18:03:37 +00:00
8455e0177b
Do not set the `link' bit when branching to the first BB of a function, as it
...
will cause an infinite loop. The link bit is only used for calling functions.
llvm-svn: 14466
2004-06-28 17:57:40 +00:00
9cb88aae40
Fix spacing around function arguments.
...
llvm-svn: 14463
2004-06-28 15:53:27 +00:00
c52ea2574d
Allow debugging machine instrs (by printout) before/after isel and regalloc
...
llvm-svn: 14416
2004-06-25 19:57:47 +00:00
26e36e5758
Combine several if stmts with returns into an if-then-elseif-else chain.
...
llvm-svn: 14414
2004-06-25 19:24:52 +00:00
c22fd9a6a5
Do not move any values into registers for a void return (there isn't anything).
...
llvm-svn: 14413
2004-06-25 19:04:27 +00:00
b5932a5708
Convert tabs to spaces.
...
llvm-svn: 14412
2004-06-25 18:45:07 +00:00
5dbf760e00
Fix opcode: no immediate in an `or r1, r2, r3' (all registers) instr.
...
llvm-svn: 14411
2004-06-25 18:36:53 +00:00
c56b66f504
* Be consistent about MachineBB labels and references to them in instr stream
...
* Use MachineBB's built-in numbering system instead of reinventing one
llvm-svn: 14408
2004-06-25 15:42:10 +00:00
a27375832b
* Initialize the entire array statically, not member-at-a-time
...
* Remove x86-specific comment re: intel vs. at&t assembly syntax
llvm-svn: 14406
2004-06-25 15:11:34 +00:00
468d9a0087
Fix bug in previous checkin.
...
llvm-svn: 14405
2004-06-25 14:57:19 +00:00
9ff1cda1a8
* Wrap long lines
...
* Replace silent fall-through FIXME comments with an error to cerr and an abort
* No need to set size of statically initialized arrays
llvm-svn: 14404
2004-06-25 14:50:41 +00:00
08b0e61841
Excise X86-specific comments.
...
llvm-svn: 14403
2004-06-25 14:13:26 +00:00
5e3afa0d4c
Add option to print out machine code before register allocation.
...
llvm-svn: 14387
2004-06-24 23:55:01 +00:00
a79dd915b7
Use DEBUG() guard for printing out debug info.
...
llvm-svn: 14386
2004-06-24 23:54:05 +00:00
c45a5a369d
Add a `break' in the switch/case statement between the int/fp sections.
...
llvm-svn: 14385
2004-06-24 23:53:24 +00:00
a08a2363ec
* Lowercase the register names
...
* Parenthesize assert() expressions correctly
* Fix spacing around for() and if() statements
llvm-svn: 14384
2004-06-24 23:51:00 +00:00
842c710028
* Tabs to spaces
...
* Send an error message to std::cerr before abort()ing
llvm-svn: 14381
2004-06-24 23:19:36 +00:00
f62ee7a11b
* Tabs to spaces
...
* Remove unnecessary parens, braces, clean up code layout
llvm-svn: 14379
2004-06-24 23:04:11 +00:00
9adccb6a50
Unindent some more code to be consistent.
...
llvm-svn: 14377
2004-06-24 22:00:15 +00:00
1e057bf1b7
Unindent some code, it only needs 2 spaces.
...
llvm-svn: 14376
2004-06-24 21:56:15 +00:00
29b3dd7d35
In emitting code for a GEP instr, iterate over GEPTypes because there is one
...
more operand in GEPOps than there are types in GEPTypes: the pointer that is the
first operand of the GEP instruction.
llvm-svn: 14375
2004-06-24 21:54:47 +00:00
f57c3cd1e8
* Order #includes
...
* Use the DEBUG() guard for debug printouts
llvm-svn: 14367
2004-06-24 17:31:42 +00:00
c88c1ba066
Spell out `NoFramePointerElim'.
...
llvm-svn: 14300
2004-06-21 21:18:48 +00:00
5cb198a9c6
Use the common `NoFPElim' setting instead of our own.
...
llvm-svn: 14298
2004-06-21 21:10:24 +00:00
5e323e10df
* Make indentation consistent at 2 chars
...
* Doxygenify function comments
* Wrap code at 80 cols
llvm-svn: 14295
2004-06-21 20:22:03 +00:00
a97f29237e
This file is no longer applicable.
...
llvm-svn: 14294
2004-06-21 20:17:41 +00:00
302df232b5
llvm/IntrinsicLowering.h => llvm/CodeGen/IntrinsicLowering.h
...
llvm-svn: 14292
2004-06-21 18:30:31 +00:00
11f74d7072
Intrinsic::isnan has gone away, support for it commented out.
...
Intrinsic::isunordered has arrived, and we just use the standard lowering
pass for it.
llvm-svn: 14290
2004-06-21 17:58:36 +00:00
c3a0b330c9
Convert tabs to spaces.
...
llvm-svn: 14289
2004-06-21 17:41:12 +00:00
254d2cf452
Type::getPrimitiveID() -> getTypeID()
...
llvm-svn: 14288
2004-06-21 17:25:55 +00:00
6292a056a8
Type::getPrimitiveID() -> getTypeID()
...
llvm-svn: 14287
2004-06-21 17:19:08 +00:00
e05203fb40
Initial revision
...
llvm-svn: 14283
2004-06-21 16:55:25 +00:00
bba0f0e492
Add file comment.
...
llvm-svn: 14172
2004-06-14 15:13:59 +00:00
6d6b3b3ce9
Fix the fixed stack offset, patch contributed by Vladimir Prus
...
llvm-svn: 14110
2004-06-10 06:19:25 +00:00
daeeaa72cd
fine grainify namespacification
...
llvm-svn: 11959
2004-02-28 19:53:18 +00:00
6a35516dcc
Add back machine code deleter pass until we get a MachineCode pass
...
that will be responsible for the creation of MachineFunctions and will
be required by all MachineFunctionPass passes.
llvm-svn: 11453
2004-02-15 00:03:15 +00:00
80da865f77
Change MachineBasicBlock's vector of MachineInstr pointers into an
...
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
llvm-svn: 11340
2004-02-12 02:27:10 +00:00
ac2ced8554
Include PowerPC.h. Flesh out the stub versions of addPassesToEmitAssembly()
...
and addPassesToJITCompile() slightly.
llvm-svn: 11076
2004-02-02 19:06:36 +00:00
2458bd6507
Add comments describing how you would add prototypes for factory methods for
...
PowerPC-specific passes here.
llvm-svn: 11073
2004-02-02 19:05:28 +00:00
f0cc848602
Add the JITInfo object, accessor & initializer.
...
llvm-svn: 10972
2004-01-23 06:39:30 +00:00
4880432af8
Add CodeEmitter and JITInfo stubs. Dump the old
...
PowerPCTargetMachine::addPassesToJITCompile() method, in favor of the
TargetJITInfo interface.
llvm-svn: 10971
2004-01-23 06:35:43 +00:00
b14a3f73cd
Import of skeletal PowerPC backend I have had laying around for months...
...
llvm-svn: 10937
2004-01-21 21:13:19 +00:00
Nate Begeman