13830229fd
comment fix
...
llvm-svn: 151339
2012-02-24 02:15:21 +00:00
9d2d2adc25
replace a balnk with -
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llvm-svn: 151337
2012-02-24 02:05:28 +00:00
19b0c8244b
80 columns of Mips InstPrinter Makefile
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llvm-svn: 151332
2012-02-24 01:47:01 +00:00
fa7a53746c
Switch ARM target to register masks.
...
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.
This patch does cause some assembly changes. Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected. MachineCopyPropagation may sometimes
leave a dead copy behind.
llvm-svn: 151331
2012-02-24 01:19:29 +00:00
3a21e2c33e
Make sure the regs are low regs for tMUL size reduction.
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llvm-svn: 151318
2012-02-24 00:53:11 +00:00
c01104dfbf
Thumb2 size reduction fix for tied operands of tMUL.
...
The tied source operand of tMUL is the second source operand, not the
first like every other two-address thumb instruction. Special case it
in the size reduction pass to make sure we create the tMUL instruction
properly.
llvm-svn: 151315
2012-02-24 00:33:36 +00:00
d4a77c4682
When emitting a cmp with 0 for a lowered select, mask out the high
...
bits of the value carying the boolean condition, as their contents
are undefined. This fixes rdar://10887484.
llvm-svn: 151310
2012-02-24 00:09:36 +00:00
a2d3608f78
MCize function entry label emission on PowerPC64 properly.
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llvm-svn: 151278
2012-02-23 20:28:39 +00:00
6fbcd8d439
Updated the llvm-mc disassembler C API to support for the X86 target.
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rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
llvm-svn: 151267
2012-02-23 18:18:17 +00:00
d5d166d4d4
Fix the numbering of some of the registers and reclassify a couple of them.
...
Also, some basic clean up. Patch by Evandro Menezes.
llvm-svn: 151266
2012-02-23 18:17:17 +00:00
a354d58f8d
Remove unused variable.
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llvm-svn: 151251
2012-02-23 11:01:22 +00:00
f258a15bdf
Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bits
...
of x are zero. This optimizes rev + lsr 16 to rev16.
rdar://10750814
llvm-svn: 151230
2012-02-23 02:58:19 +00:00
e87681cf34
Optimize a couple of common patterns involving conditional moves where the false
...
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
llvm-svn: 151224
2012-02-23 01:19:06 +00:00
ad4d9f5848
Allow the use of an alternate symbol for calculating a function's size.
...
The standard function epilog includes a .size directive, but ppc64 uses
an alternate local symbol to tag the actual start of each function.
Until recently, binutils accepted the .size directive as:
.size test1, .Ltmp0-test1
however, using this directive with recent binutils will result in the error:
.size expression for XXX does not evaluate to a constant
so we must use the label which actually tags the start of the function.
llvm-svn: 151200
2012-02-22 21:11:47 +00:00
8b98bf2d6b
Properly emit _fltused with FastISel. Refactor to share code with SDAG.
...
Patch by Joe Groff!
llvm-svn: 151183
2012-02-22 19:06:13 +00:00
5dfe6dab25
Remove extra semi-colons.
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llvm-svn: 151169
2012-02-22 17:25:00 +00:00
2a783d5b94
Efficient pattern for store truncate. Patch by Evandro Menezes.
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llvm-svn: 151166
2012-02-22 16:45:10 +00:00
cc830f8cda
Declare register classes as const. Fix a couple pointers to register classes that weren't already const.
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llvm-svn: 151138
2012-02-22 07:28:11 +00:00
760b134ffa
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
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llvm-svn: 151134
2012-02-22 05:59:10 +00:00
e67173e718
Adding support for Microsoft's thiscall calling convention. LLVM side of the patch.
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llvm-svn: 151123
2012-02-22 03:04:40 +00:00
5f37f1c39d
Clarify ARM calling conventions.
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llvm-svn: 151113
2012-02-22 01:07:19 +00:00
a7721f6b4d
Use a function in MathExtras to do sign extension.
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llvm-svn: 151107
2012-02-22 00:16:54 +00:00
6909faaf35
Calls don't really change the stack pointer.
...
Even if a call instruction has %SP<imp-def> operands, it doesn't change
the value of the stack pointer.
llvm-svn: 151104
2012-02-21 23:47:43 +00:00
0460ae8d80
Proper support for a bastardized darwin-eabi hybird ABI.
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llvm-svn: 151083
2012-02-21 20:46:00 +00:00
da84e64683
Clear virtual registers after they are no longer referenced.
...
Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0.
This makes sharing code for pre/postRA passes more robust.
Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA().
To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs().
PEI resets virtual regs when it's done scavenging.
PTX will either have to provide its own PEI pass or assign physregs.
llvm-svn: 151032
2012-02-21 04:51:23 +00:00
547d4c0662
Improve generated code for extending loads and some trunc stores on ARM.
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Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.
llvm-svn: 150956
2012-02-20 09:24:05 +00:00
636a3d618c
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
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llvm-svn: 150918
2012-02-19 11:37:01 +00:00
de121a1000
Remove some unneeded includes and fix ordering in X86ISelLowering.cpp. Remove unneeded 'using namespace'.
...
llvm-svn: 150916
2012-02-19 07:15:48 +00:00
65a4ceea1e
Unify all shuffle mask checking functions take a mask and VT instead of VectorShuffleSDNode.
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llvm-svn: 150913
2012-02-19 05:41:45 +00:00
3e5c04e432
Make a bunch of X86ISelLowering shuffle functions static now that they are no longer needed by isel.
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llvm-svn: 150908
2012-02-19 02:53:47 +00:00
608dc6e257
comment fix ARM.h
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llvm-svn: 150904
2012-02-19 02:04:03 +00:00
e1d619691b
some comment fix for X86 and ARM
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llvm-svn: 150902
2012-02-19 02:03:36 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
57d3aaed78
Add X86InstrSVM.td that I forgot to add in r150873.
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llvm-svn: 150874
2012-02-18 08:34:12 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
4fad5b2b9e
Handle regmask operands in ARMInstrInfo.
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llvm-svn: 150833
2012-02-17 19:23:15 +00:00
96732a438d
Fix ARMBaseInstrInfo::getInstrLatency for calls.
...
Calls always clobber CPSR.
llvm-svn: 150831
2012-02-17 19:07:59 +00:00
9f6101191b
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
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llvm-svn: 150805
2012-02-17 08:55:11 +00:00
ba172d2d59
Remove the last of the old vector_shuffle patterns from X86 isel.
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llvm-svn: 150795
2012-02-17 07:02:34 +00:00
d608bac682
Do not promote i32 arguments to i64. This was causing unnecessary sign extension
...
instructions to be emitted.
llvm-svn: 150782
2012-02-17 02:20:26 +00:00
dd6c1cd4e8
add Emacs tag and fix some comment error in file headers
...
llvm-svn: 150775
2012-02-17 01:23:50 +00:00
fcd29ae390
[fast-isel] Add support for returning non-legal types with no sign- or zero-
...
entend flag.
llvm-svn: 150774
2012-02-17 01:21:28 +00:00
5bade3dc6e
Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.
...
llvm-svn: 150769
2012-02-17 00:27:16 +00:00
b4d2ccf2ab
Remove comment.
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llvm-svn: 150739
2012-02-16 22:52:29 +00:00
a0d3c75015
Remove unnecessary assignment to temporary, ResultReg.
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llvm-svn: 150737
2012-02-16 22:45:33 +00:00
bc6ba479b6
Remove the YMM_HI_6_15 hack.
...
Call clobbers are now represented with register mask operands. The
regmask can easily represent the fact that xmm6 is call-preserved while
ymm6 isn't. This is automatically computed by TableGen from the
CalleeSavedRegs containing xmm6.
llvm-svn: 150709
2012-02-16 17:56:06 +00:00
97e3115dc2
Use the same CALL instructions for Windows as for everything else.
...
The different calling conventions and call-preserved registers are
represented with regmask operands that are added dynamically.
llvm-svn: 150708
2012-02-16 17:56:02 +00:00
4705b0cc1c
Remove trailing whitespace. Add newline.
...
llvm-svn: 150706
2012-02-16 17:48:20 +00:00
55a2a96153
Oop - r150653 + r150654 broke one of my test cases. Backing out for now...
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llvm-svn: 150655
2012-02-16 02:32:10 +00:00
11ca986b17
FPSCR shouldn't be reserved.
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llvm-svn: 150654
2012-02-16 02:28:14 +00:00
8a450cb2fa
Enable register mask operands for x86 calls.
...
Call instructions no longer have a list of 43 call-clobbered registers.
Instead, they get a single register mask operand with a bit vector of
call-preserved registers.
This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call
instruction, and it speeds up building call instructions because those
43 imp-def operands no longer need to be added to use-def lists. (And
removed and shifted and re-added for every explicit call operand).
Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and
BranchFolding are significantly faster because they can deal with call
clobbers in bulk.
Overall, clang -O2 is between 0% and 8% faster, uniformly distributed
depending on call density in the compiled code. Debug builds using
clang -O0 are 0% - 3% faster.
I have verified that this patch doesn't change the assembly generated
for the LLVM nightly test suite when building with -disable-copyprop
and -disable-branch-fold.
Branch folding behaves slightly differently in a few cases because call
instructions have different hash values now.
Copy propagation flushes its data structures when it crosses a register
mask operand. This causes it to leave a few dead copies behind, on the
order of 20 instruction across the entire nightly test suite, including
SPEC. Fixing this properly would require the pass to use different data
structures.
llvm-svn: 150638
2012-02-16 00:02:50 +00:00
30804c24ca
Optimize redundant sign extends and negation of predicates.
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llvm-svn: 150606
2012-02-15 18:52:27 +00:00
53da633f93
Revert "Replacing HexagonOptimizeSZExtends with HexagonPeephole."
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This reverts commit 1656806a944bbd23e98c6e578810fe02495ab741.
llvm-svn: 150605
2012-02-15 18:34:25 +00:00
d9811eb7be
Revert "Optimize redundant sign extends and negation of predicates"
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as it's breaking the build.
This reverts commit 11241abca5e2a313412fed594bb9d9fa2a2057fb.
llvm-svn: 150604
2012-02-15 18:32:25 +00:00
99571325f1
Replacing HexagonOptimizeSZExtends with HexagonPeephole.
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llvm-svn: 150603
2012-02-15 18:31:35 +00:00
4736aee81e
Optimize redundant sign extends and negation of predicates
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llvm-svn: 150601
2012-02-15 18:22:18 +00:00
0bc5132457
Add braces to if clause to make symmetric with associate else clause.
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llvm-svn: 150591
2012-02-15 17:36:21 +00:00
dfb45f4d68
Strip the pointer casts from the constants here.
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The c'tor list is stored as a list of 'void ()*'s, so all of the functions are
bitcast to that. However, the dyn_cast doesn't automagically look through
bitcasts. Do that for it.
<rdar://problem/10813350>
llvm-svn: 150572
2012-02-15 09:14:08 +00:00
c9ce9d2315
Added TargetPassConfig::disablePass/substitutePass as a general mechanism to override specific passes.
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llvm-svn: 150562
2012-02-15 03:21:47 +00:00
f0687634c3
Use a temporary variable, rather then a series of redundant calls.
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llvm-svn: 150538
2012-02-15 00:36:26 +00:00
c21ebf5c41
Stop custom lowering forr x86 DEC64m from happening if the load in the lowered sequence has more than 1 user
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llvm-svn: 150537
2012-02-15 00:33:37 +00:00
dccc4794e6
Use a temporary variable, rather then a series of redundant calls.
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llvm-svn: 150536
2012-02-15 00:23:55 +00:00
5b9c3974d2
Remove unnecessary assignment to temporary, ResultReg.
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llvm-svn: 150520
2012-02-14 22:29:48 +00:00
cfad98f745
Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel.
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llvm-svn: 150462
2012-02-14 08:14:53 +00:00
876f24f706
Third time's the charm...?
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llvm-svn: 150447
2012-02-14 00:34:30 +00:00
185455df7e
Unswap swap operands, partially reducing confusion.
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llvm-svn: 150444
2012-02-14 00:17:12 +00:00
05d6f2ff1e
Don't reserve the R0 and R1 registers here. We don't use these registers, and
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marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.
llvm-svn: 150437
2012-02-13 23:47:16 +00:00
aef4ca78c5
Make operands for VSWP read-modify-write.
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llvm-svn: 150433
2012-02-13 23:37:19 +00:00
8b19d78808
Still more vector_shuffle pattern removal.
...
llvm-svn: 150365
2012-02-13 07:23:41 +00:00
32e983e4fc
Fix various issues (or do cleanups) found by enabling certain MSVC warnings.
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- Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default.
- Remove misplaced llvm_unreachable.
- Add static to a declaration of a function on MSVC x86 only.
- Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable.
llvm-svn: 150364
2012-02-13 06:30:56 +00:00
74650add0e
Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel.
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llvm-svn: 150363
2012-02-13 05:48:49 +00:00
6d471c9e49
Recommit r150328. Previous test failures should be fixed by r150360.
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llvm-svn: 150362
2012-02-13 05:10:10 +00:00
87119fa37f
Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.
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llvm-svn: 150360
2012-02-13 04:30:38 +00:00
0826c17d00
Revert r150328, "Remove more vector_shuffle patterns."
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It caused 3 failures on pre-penryn and non-x86(generic) hosts.
llvm-svn: 150357
2012-02-13 00:10:15 +00:00
71be57bb32
Fixed bug when custom lowering DEC64m on x86.
...
If the DEC node had more than one user, it was doing this lowering but
leaving the original DEC node around and so decrementing twice.
Fixes PR11964.
llvm-svn: 150356
2012-02-13 00:10:03 +00:00
e24c94af81
Remove more vector_shuffle patterns.
...
llvm-svn: 150328
2012-02-12 08:14:35 +00:00
4b273cb7ea
Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI calls
...
to TargetLibraryInfo and use one of them in GlobalOpt.
llvm-svn: 150323
2012-02-12 02:15:20 +00:00
d40d9eb2b3
Remove more vector_shuffle patterns.
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llvm-svn: 150321
2012-02-12 01:07:34 +00:00
330ca97700
Remove more vector_shuffle patterns.
...
llvm-svn: 150314
2012-02-11 23:31:01 +00:00
c6b4017ce2
Add support for implicit TLS model used with MS VC runtime.
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Patch by Kai Nacke!
llvm-svn: 150307
2012-02-11 17:26:53 +00:00
915e3d9568
Don't mix declarations and code.
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llvm-svn: 150305
2012-02-11 16:01:02 +00:00
428704eb52
Make the EDis tables const.
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llvm-svn: 150304
2012-02-11 14:51:07 +00:00
478e8de8ef
Reuse the enum names from X86Desc in the X86Disassembler.
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This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.
llvm-svn: 150303
2012-02-11 14:50:54 +00:00
981c6cf7b3
Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel.
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llvm-svn: 150299
2012-02-11 07:43:35 +00:00
11826a6e10
Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel.
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llvm-svn: 150296
2012-02-11 06:24:48 +00:00
1c9dd2974f
Revert r150222, as the clang driver now handles this properly.
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Now that the clang driver passes the CPU and feature information to
the backend when processing assembly files (150273), this isn't necessary.
llvm-svn: 150274
2012-02-10 20:38:46 +00:00
c7f4841769
Make valgrind happy.
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llvm-svn: 150251
2012-02-10 16:07:59 +00:00
f08915ca8e
unnecessary include
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llvm-svn: 150228
2012-02-10 04:10:44 +00:00
f4ff234384
PTX no longer needs to provide its own backend.
...
llvm-svn: 150227
2012-02-10 04:10:40 +00:00
d3f8fe81f4
RegAlloc superpass: includes phi elimination, coalescing, and scheduling.
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Creates a configurable regalloc pipeline.
Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.
When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.
CodeGen transformation passes are never "required" as an analysis
ProcessImplicitDefs does not require LiveVariables.
We have a plan to massively simplify some of the early passes within the regalloc superpass.
llvm-svn: 150226
2012-02-10 04:10:36 +00:00
ffc02c5ffc
ARM on darwin, v6 implies the presence of VFP for the assembler.
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rdar://10838899
llvm-svn: 150222
2012-02-10 02:21:49 +00:00
545983ea46
Test for commit access.
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llvm-svn: 150178
2012-02-09 15:20:33 +00:00
d9ba4fd48f
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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llvm-svn: 150169
2012-02-09 10:56:31 +00:00
a0cd970b81
More tweaks to get the size of the X86 disassembler tables down.
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llvm-svn: 150167
2012-02-09 08:58:07 +00:00
487e744f66
Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.
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llvm-svn: 150161
2012-02-09 07:45:30 +00:00
4519fd0b21
Handle register masks when searching for EFLAGS clobbers.
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Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.
llvm-svn: 150117
2012-02-09 00:17:22 +00:00
1fa5bcbe2a
Codegen pass definition cleanup. No functionality.
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Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.
While cleaning up declarations, cleaned up comments (sorry for large diff).
llvm-svn: 150100
2012-02-08 21:23:13 +00:00
3ed444a16a
Move pass configuration out of pass constructors: StackSlotColoring.
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llvm-svn: 150097
2012-02-08 21:22:57 +00:00
df7e3769b5
Move pass configuration out of pass constructors: PostRAScheduler.
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llvm-svn: 150096
2012-02-08 21:22:53 +00:00
58648e4e98
Move pass configuration out of pass constructors: BranchFolderPass
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llvm-svn: 150095
2012-02-08 21:22:48 +00:00
dd37d52f95
Added TargetPassConfig::setOpt
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llvm-svn: 150093
2012-02-08 21:22:39 +00:00
c044917a8a
Move pass configuration out of pass constructors: TailDuplicate::PreRegAlloc
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llvm-svn: 150091
2012-02-08 21:22:30 +00:00
6f35837048
Use TSFlag bit to describe instruction properties.
...
Creating the isPredicated TSFlag enables the code
to use the property defined in the instruction format
instead of using a large switch statement.
llvm-svn: 150078
2012-02-08 18:25:47 +00:00
1adc1d53dd
Fixed a bug in printing "cmp" pseudo ops.
...
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0 llc 0x0000000001355803
> 1 llc 0x0000000001355dc9
> 2 libpthread.so.0 0x00007f79a30575d0
> 3 libc.so.6 0x00007f79a23a1945 gsignal + 53
> 4 libc.so.6 0x00007f79a23a2f21 abort + 385
> 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240
> 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119
I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.
You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.
llvm-svn: 150068
2012-02-08 08:37:26 +00:00
172b9243cd
Remove a couple unneeded intrinsic patterns
...
llvm-svn: 150067
2012-02-08 08:29:30 +00:00
5405571fe0
Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns.
...
llvm-svn: 150060
2012-02-08 06:36:57 +00:00
0ee8c513f7
[fast-isel] Add support for SUBs with non-legal types.
...
llvm-svn: 150047
2012-02-08 02:45:44 +00:00
bd471255a9
[fast-isel] Add support for ORs with non-legal types.
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llvm-svn: 150045
2012-02-08 02:29:21 +00:00
ded4c99f2e
[fast-isel] Add support for indirect branches.
...
llvm-svn: 150014
2012-02-07 23:56:08 +00:00
1b81fddd65
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
...
llvm-svn: 150008
2012-02-07 22:50:41 +00:00
45d8f8a08c
Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexed
...
load / store) if the ADD / SUB has a live definition of CPSR.
Bug reported by David Meyer. Alas, no test case.
llvm-svn: 149970
2012-02-07 07:09:28 +00:00
b27fd77c3f
Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.
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llvm-svn: 149968
2012-02-07 06:28:42 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
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llvm-svn: 149961
2012-02-07 02:50:20 +00:00
685b20c114
[fast-isel] Add support for ADDs with non-legal types.
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llvm-svn: 149934
2012-02-06 23:50:07 +00:00
34914910f5
Add TargetPassConfig to the PassManager for use inside passes
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llvm-svn: 149926
2012-02-06 22:51:15 +00:00
8b2dcad4b5
Enable streaming of bitcode
...
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
llvm-svn: 149918
2012-02-06 22:30:29 +00:00
8213c8af29
Remove some dead code and tidy things up now that vectors use ConstantDataVector
...
instead of always using ConstantVector.
llvm-svn: 149912
2012-02-06 21:56:39 +00:00
d5d95b0b51
[unwind removal] We no longer have 'unwind' instructions being generated, so
...
remove the code that handles them.
llvm-svn: 149901
2012-02-06 21:16:41 +00:00
2496717052
X86: Don't call malloc for 4 bits. No functionality change.
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llvm-svn: 149866
2012-02-06 12:06:18 +00:00
ae87d7b4b2
Hexagon: Remove forbidden iostream includes (it introduces static initializers)
...
Reorder includes while at it.
llvm-svn: 149863
2012-02-06 10:19:29 +00:00
1f71057747
Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding.
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llvm-svn: 149859
2012-02-06 07:17:51 +00:00
613d6d3b43
DefinesPredicate should only look for def operands. Patch by Ludwig Meier.
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llvm-svn: 149846
2012-02-05 19:55:04 +00:00
994c1103c8
Remove dead test: this was already checked and handled a few lines
...
above.
llvm-svn: 149841
2012-02-05 19:30:06 +00:00
ae22c60f90
Persuade GCC that there is nothing worth warning about here (there isn't).
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llvm-svn: 149834
2012-02-05 14:20:11 +00:00
efabc2572f
Don't initialize CV in terms of itself! Spotted by GCC.
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llvm-svn: 149833
2012-02-05 14:16:09 +00:00
ebd90c58e6
Begin fleshing out more convenience predicates in llvm::Triple and
...
convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.
This round of predicates is focused on OS-categorization predicates.
llvm-svn: 149815
2012-02-05 08:26:40 +00:00
c4965bce14
Convert assert(0) to llvm_unreachable
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llvm-svn: 149814
2012-02-05 07:21:30 +00:00
4ed7278ff4
Convert assert(0) to llvm_unreachable in X86 Target directory.
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llvm-svn: 149809
2012-02-05 05:38:58 +00:00
83f3bdaa45
Convert some assert(0) in default of switch statements to llvm_unreachable.
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llvm-svn: 149808
2012-02-05 03:43:23 +00:00
1d471e31ba
Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
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llvm-svn: 149807
2012-02-05 03:14:49 +00:00
cf9e8f6968
reapply the patches reverted in r149470 that reenable ConstantDataArray,
...
but with a critical fix to the SelectionDAG code that optimizes copies
from strings into immediate stores: the previous code was stopping reading
string data at the first nul. Address this by adding a new argument to
llvm::getConstantStringInfo, preserving the behavior before the patch.
llvm-svn: 149800
2012-02-05 02:29:43 +00:00
4daa67483d
Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file.
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llvm-svn: 149795
2012-02-05 00:55:56 +00:00
f8ea108c05
TargetPassConfig: confine the MC configuration to TargetMachine.
...
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.
Sorry for the target header churn. Attempting to stabilize them.
llvm-svn: 149754
2012-02-04 02:56:59 +00:00
b84a4b4c64
[fast-isel] Add support for URem.
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llvm-svn: 149716
2012-02-03 21:23:45 +00:00
e023d5d7f3
[fast-isel] Rename isZExt to isSigned. No functional change intended.
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llvm-svn: 149714
2012-02-03 21:14:11 +00:00
aaa55a88b6
[fast-isel] Add support for UDIV.
...
llvm-svn: 149712
2012-02-03 21:07:27 +00:00
41f0e78b6c
[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.
...
llvm-svn: 149706
2012-02-03 20:27:51 +00:00
a8a8ac5d47
[fast-isel] Add support for selecting UIToFP.
...
llvm-svn: 149704
2012-02-03 19:42:52 +00:00
47e6d26911
Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation.
...
llvm-svn: 149683
2012-02-03 06:52:33 +00:00
d5ffe0900d
Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.
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llvm-svn: 149680
2012-02-03 06:32:21 +00:00
ccb673659a
Added TargetPassConfig. The first little step toward configuring codegen passes.
...
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.
llvm-svn: 149672
2012-02-03 05:12:41 +00:00
808a7a6ce6
whitespace
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llvm-svn: 149671
2012-02-03 05:12:30 +00:00
f0b08445f6
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is
...
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.
llvm-svn: 149668
2012-02-03 04:33:00 +00:00
bb682450f9
Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.
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llvm-svn: 149655
2012-02-03 01:13:49 +00:00
5e1ac45b93
Require non-NULL register masks.
...
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.
llvm-svn: 149646
2012-02-02 23:52:57 +00:00
caed1c9370
Add pseudo-registers for pairs, triples, and quads of D registers.
...
NEON loads and stores accept single and double spaced pairs, triples,
and quads of D registers. This patch adds new register classes to
accurately model those constraints:
Dn, Dn+1 Dn, Dn+2
----------------------
DPair DPairSpc
DTriple DTripleSpc
DQuad DQuadSpc
Also extend the existing QQ and QQQQ register classes to contains all Q
pairs and quads instead of just the aligned ones.
These new register classes will make it possible to accurately model
constraints on NEON loads and stores, and we can get rid of all the NEON
pseudo-instructions. The late scheduler will be able to accurately
model instruction dependencies from the explicit operands.
This more than doubles the number of ARM registers, but the backend
passes are quite good at handling this. The llc -O0 compile time only
regresses by 1.5%. Future work on register mask operands will recover
this regression.
llvm-svn: 149640
2012-02-02 22:45:32 +00:00
6fbb4d2842
Minor change in signature of the getZeroVector()
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llvm-svn: 149601
2012-02-02 09:20:18 +00:00
fb44980b41
Optimization for SIGN_EXTEND operation on AVX.
...
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.
llvm-svn: 149600
2012-02-02 09:10:43 +00:00
26f302d568
Unbreak the MSVC build.
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llvm-svn: 149599
2012-02-02 08:36:09 +00:00
0269caafa6
Set EFLAGS correctly in EmitLoweredSelect on X86.
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llvm-svn: 149597
2012-02-02 07:48:37 +00:00
961883c1cf
Set the correct stack pointer register.
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llvm-svn: 149585
2012-02-02 03:17:04 +00:00
f029537e68
Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and
...
selector registers.
llvm-svn: 149584
2012-02-02 03:13:40 +00:00
d9fef17749
Add DWARF numbers of 64-bit registers.
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llvm-svn: 149583
2012-02-02 02:56:14 +00:00
77295818f0
Fix the cmake build
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llvm-svn: 149561
2012-02-01 23:40:51 +00:00
8523b16ff5
Instruction scheduling itinerary for Intel Atom.
...
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
c7024a48db
Move ARM subreg index compositions to the SubRegIndex itself.
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llvm-svn: 149557
2012-02-01 23:16:43 +00:00
9f05206659
Avoid creating an extract element to an illegal type after LegalizeTypes has run.
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llvm-svn: 149548
2012-02-01 22:15:20 +00:00
d06df96a7c
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
...
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.
Patch by Sergei Larin!
llvm-svn: 149547
2012-02-01 22:13:57 +00:00
e273cb08c4
Tidy up.
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llvm-svn: 149521
2012-02-01 18:45:51 +00:00
824eed70a6
Passing AVX 256-bit structures in Win64 was wrong.
...
Fixed Win64 calling conventions.
llvm-svn: 149494
2012-02-01 10:46:14 +00:00
34cca175ab
Shortened code in shuffle masks
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llvm-svn: 149493
2012-02-01 10:33:05 +00:00
0e48c70ba7
Optimization for "truncate" operation on AVX.
...
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.
llvm-svn: 149485
2012-02-01 07:56:44 +00:00
513aaa5691
SwitchInst refactoring.
...
The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want.
What was done:
1. Changed semantics of index inside the getCaseValue method:
getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous.
2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned.
3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment.
4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst.
4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor.
4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor.
Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang.
llvm-svn: 149481
2012-02-01 07:49:51 +00:00
9cdb8bdf04
Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900.
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llvm-svn: 149478
2012-02-01 06:51:58 +00:00
17c981a45b
Revert Chris' commits up to r149348 that started causing VMCoreTests unit test to fail.
...
These are:
r149348
r149351
r149352
r149354
r149356
r149357
r149361
r149362
r149364
r149365
llvm-svn: 149470
2012-02-01 04:51:17 +00:00
a2147ce313
Tidy up. One more return type mismatch fix.
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llvm-svn: 149452
2012-01-31 23:51:09 +00:00
44091c2f10
Refactor loop for better readability.
...
Excellent suggestion from Ben Kramer.
llvm-svn: 149417
2012-01-31 20:56:55 +00:00
b4d3a6af97
Add explanatory comment.
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llvm-svn: 149416
2012-01-31 20:34:53 +00:00
a173ee56fd
Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly.
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llvm-svn: 149396
2012-01-31 18:14:05 +00:00
b85e40f738
Remove pcmpgt/pcmpeq intrinsics as clang is not using them.
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llvm-svn: 149367
2012-01-31 06:52:44 +00:00
8ea967d050
with recent changes, ConstantArray is never a "string". Remove the associated
...
methods and constant fold the clients to false.
llvm-svn: 149362
2012-01-31 06:05:00 +00:00
3a565d6241
use the right accessor for ConstantDataArray.
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llvm-svn: 149342
2012-01-31 03:16:39 +00:00
4e7992eeba
PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.
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llvm-svn: 149294
2012-01-30 23:10:32 +00:00
7cdb2ff6b5
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
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llvm-svn: 149291
2012-01-30 22:47:12 +00:00
9a9bb5c5db
Intel syntax. Support .intel_syntax directive.
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llvm-svn: 149270
2012-01-30 20:02:42 +00:00
396c590818
Fix refacto.
...
llvm-svn: 149269
2012-01-30 20:01:35 +00:00
e577cfe172
Eliminate narrowing conversion in initializer list, to make C++11 happy
...
llvm-svn: 149254
2012-01-30 16:57:18 +00:00
20af25f47b
X86: Simplify shuffle mask generation code.
...
llvm-svn: 149248
2012-01-30 15:16:21 +00:00
516cba3380
Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
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llvm-svn: 149232
2012-01-30 07:50:31 +00:00
ca29bcfc10
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
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llvm-svn: 149216
2012-01-30 01:10:15 +00:00
d0c46550fe
Cleanups for EABI standard functions
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llvm-svn: 149195
2012-01-29 09:11:50 +00:00
1b42e64280
Use base AAPCS for varargs functions even for AAPCS-VFP CC
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llvm-svn: 149194
2012-01-29 09:06:09 +00:00
de0c335560
Add a note about a potential optimization for clz/ctz patterns for ARM
...
(and other targets).
llvm-svn: 149182
2012-01-28 18:30:07 +00:00
b47489d4ef
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
...
Fixes PR11877
llvm-svn: 149180
2012-01-28 15:58:32 +00:00
63fe5697f4
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
...
llvm-svn: 149142
2012-01-27 19:48:28 +00:00
5639e9e8fb
Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition.
...
llvm-svn: 149122
2012-01-27 07:09:40 +00:00
8f28dbdde5
Keep source location information for X86 MCFixup's.
...
llvm-svn: 149106
2012-01-27 00:51:27 +00:00
20275a8577
Better user diagnostics for more ARM MachO relocation errors.
...
llvm-svn: 149102
2012-01-27 00:37:12 +00:00
b591277c4a
Better diagnostic for malformed .org assembly directive.
...
Provide source line number information.
llvm-svn: 149101
2012-01-27 00:37:08 +00:00
5e5eabb5ab
Keep source information, if available, around for ARM Fixups.
...
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
llvm-svn: 149093
2012-01-26 23:20:15 +00:00
fc9dce25f7
Handle call-clobbered ymm registers on Win64.
...
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
llvm-svn: 149088
2012-01-26 22:59:28 +00:00
c8f2b7877b
Tidy up. Fix mismatched return types for error handling.
...
llvm-svn: 149062
2012-01-26 15:56:45 +00:00
6685c08e5f
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
...
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
llvm-svn: 149057
2012-01-26 09:25:43 +00:00
5f29b0e57b
Fix for the following bug in AVX codegen for double-to-int conversions:
...
. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
. Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
. Consequently, the conversion produces incorrect numbers.
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode.
As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec).
llvm-svn: 149056
2012-01-26 08:51:39 +00:00
86e44bc829
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
...
llvm-svn: 149054
2012-01-26 07:51:55 +00:00
1c0e22f57a
Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
...
llvm-svn: 149053
2012-01-26 07:31:30 +00:00
b91760eff8
Remove some more patterns by custom lowering intrinsics to target specific nodes.
...
llvm-svn: 149052
2012-01-26 07:18:03 +00:00
7722a2d4e3
Properly emit ctors / dtors with priorities into desired sections
...
and let linker handle the rest.
This finally fixes PR5329
llvm-svn: 148990
2012-01-25 22:24:19 +00:00
82f76d1275
ARM assemly parsing and validation of IT instruction.
...
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
llvm-svn: 148969
2012-01-25 19:52:01 +00:00
33633a90a0
fix a bug I introduced in r148929, this is not a splat!
...
Thanks to Eli for noticing.
llvm-svn: 148947
2012-01-25 09:56:22 +00:00
7834900950
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
...
llvm-svn: 148933
2012-01-25 06:43:11 +00:00
47a86bdbe2
use ConstantVector::getSplat in a few places.
...
llvm-svn: 148929
2012-01-25 06:02:56 +00:00
ce4f9c5668
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
...
llvm-svn: 148927
2012-01-25 05:37:32 +00:00
5bcf070e68
Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
...
llvm-svn: 148922
2012-01-25 04:42:03 +00:00
012f041bce
Mark 64-bit register RA_64 unused too.
...
llvm-svn: 148918
2012-01-25 04:19:22 +00:00
01d3c42f90
Modify MipsFrameLowering::emitPrologue and emitEpilogue.
...
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
instructions which store callee-saved registers have been emitted.
llvm-svn: 148917
2012-01-25 04:12:04 +00:00
d1d4b3efcf
Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to
...
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.
llvm-svn: 148916
2012-01-25 03:55:10 +00:00
3ad5bc019a
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
...
llvm-svn: 148914
2012-01-25 03:52:09 +00:00
6c421ea484
MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.
...
inttypes.h is not supplied in msvc.
llvm-svn: 148912
2012-01-25 03:34:41 +00:00
96a21dcea3
Target/Mips: Unbreak CMake build.
...
llvm-svn: 148909
2012-01-25 03:15:46 +00:00
86d5fadd57
Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
...
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.
llvm-svn: 148908
2012-01-25 03:01:35 +00:00
ff36fd3de3
Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
...
load an immediate.
llvm-svn: 148900
2012-01-25 01:43:36 +00:00
086cbfac7d
NEON VLD4(all lanes) assembly parsing and encoding.
...
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
ccb6d55dae
Tidy up. Rename VLD4DUP patterns for consistency.
...
llvm-svn: 148883
2012-01-24 23:47:07 +00:00
b78403ce48
NEON VLD3(all lanes) assembly parsing and encoding.
...
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
d7970f9e4b
Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
...
which is what N32/64 does.
llvm-svn: 148875
2012-01-24 23:18:43 +00:00
7e6c195c11
Pass CCState by reference.
...
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
77dbd786c8
Pattern for f32 to i64 conversion.
...
llvm-svn: 148869
2012-01-24 22:05:25 +00:00
a410ed3ced
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
...
llvm-svn: 148864
2012-01-24 21:43:36 +00:00
9f7ec1538f
64-bit sign extension in register instructions.
...
llvm-svn: 148862
2012-01-24 21:41:09 +00:00
8e2722cdb0
NEON VST4(one lane) assembly parsing and encoding.
...
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
d845d9d9e9
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
...
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
14952a0e32
NEON VLD4(one lane) assembly parsing and encoding.
...
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
3cfef8d467
NEON Two-operand assembly aliases for VSRA.
...
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
7ae12cc546
NEON Two-operand assembly aliases for VSLI.
...
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
7b6f0f67aa
NEON Two-operand assembly aliases for VSRI.
...
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
681db34eae
NEON add correct predicates for some asm aliases.
...
llvm-svn: 148815
2012-01-24 17:23:29 +00:00
139822fc83
C++, CBE, and TLOF support for ConstantDataSequential
...
llvm-svn: 148805
2012-01-24 14:17:05 +00:00
0b0c5d8c4c
ZERO_EXTEND operation is optimized for AVX.
...
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
llvm-svn: 148803
2012-01-24 13:54:13 +00:00
3cad0c21ed
Use correct register class for am2offset register operands.
...
This pacifies machine verifier
llvm-svn: 148782
2012-01-24 04:58:56 +00:00
0d8e67aebd
Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
...
llvm-svn: 148771
2012-01-24 03:03:17 +00:00
da70eac268
NEON VST4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
ed561fc850
NEON VLD4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
1e946a4f91
Tidy up. Remove some vertical space for readability.
...
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
ed975232bc
Revert r148686 (and r148694, a fix to it) due to a serious layering
...
violation -- MC cannot depend on CodeGen.
Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.
Fixing this is likely going to require some non-trivial refactoring.
llvm-svn: 148759
2012-01-24 00:30:17 +00:00
17bacab475
Fix typo.
...
llvm-svn: 148757
2012-01-24 00:12:39 +00:00
d3d36d9315
NEON VST3(single element from one lane) assembly parsing.
...
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
eba7d3dba9
Fix typo.
...
llvm-svn: 148751
2012-01-23 23:56:33 +00:00
1a74724fc9
NEON VST3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
ac2af3ffab
NEON VLD3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
820417af07
Add missed mayStore flag to STREXD / t2STREXD
...
llvm-svn: 148742
2012-01-23 22:57:52 +00:00
cf893a437e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
...
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
a8b444b08b
NEON VLD3 lane-indexed assembly parsing and encoding.
...
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
e660fdd953
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
...
llvm-svn: 148721
2012-01-23 20:20:06 +00:00
d28ef9ac46
Simplify some NEON assembly pseudo definitions.
...
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
880bc1644b
Intel syntax: Parse segment registers.
...
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
28ea8f523b
ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
...
llvm-svn: 148694
2012-01-23 09:14:42 +00:00
edd1d0acfc
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
...
llvm-svn: 148687
2012-01-23 08:18:28 +00:00
482cdc4ebd
An option to selectively enable parts of ARM EHABI support.
...
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.
llvm-svn: 148686
2012-01-23 07:57:39 +00:00
6b90c5d03e
Update more places to use target specific nodes for vector shifts instead of intrinsics.
...
llvm-svn: 148685
2012-01-23 06:46:22 +00:00
5e80db4e4f
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
...
llvm-svn: 148684
2012-01-23 06:16:53 +00:00
20c98df340
Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
...
llvm-svn: 148672
2012-01-23 00:06:44 +00:00
0b7ad76bd0
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
...
llvm-svn: 148670
2012-01-22 23:36:02 +00:00
bd4884371b
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
...
llvm-svn: 148667
2012-01-22 22:42:16 +00:00
e197d943f3
Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class.
...
llvm-svn: 148665
2012-01-22 20:05:26 +00:00
094626414d
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
...
llvm-svn: 148664
2012-01-22 19:15:14 +00:00
5482b9f535
Add fused multiple+add instructions from VFPv4.
...
Patch by Ana Pazos!
llvm-svn: 148658
2012-01-22 12:07:33 +00:00
a4ed5246d8
Make code a little less verbose.
...
llvm-svn: 148651
2012-01-22 03:07:48 +00:00
cb3433cd58
Remove unused X86 ISD node type defines.
...
llvm-svn: 148644
2012-01-22 01:15:56 +00:00
123adfa0f3
Move some vector shift patterns into their instruction definitions.
...
llvm-svn: 148643
2012-01-22 00:41:20 +00:00
dcaa5fbd08
Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
...
llvm-svn: 148641
2012-01-21 18:37:15 +00:00
5cff13a3fb
Remove unused variables.
...
llvm-svn: 148635
2012-01-21 10:42:44 +00:00
39bc1e4d25
Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
...
llvm-svn: 148632
2012-01-21 08:49:33 +00:00
78dcaed8ca
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
...
llvm-svn: 148601
2012-01-21 00:07:56 +00:00
ce6a2ca8c8
Intel syntax: Robustify register parsing.
...
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
...
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
d0930fff85
Intel syntax: Parse ... PTR [-8]
...
llvm-svn: 148570
2012-01-20 21:21:01 +00:00
f36613cb45
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
...
llvm-svn: 148569
2012-01-20 21:14:06 +00:00
6c7aaec077
ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
...
We have patterns for vector sext and zext operations but were missing
anyext. Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.
llvm-svn: 148568
2012-01-20 20:59:56 +00:00
90f5780fc1
VST2 four-register w/ update pseudos for fixed/register update.
...
rdar://10724489
llvm-svn: 148560
2012-01-20 19:16:00 +00:00
a9d36fbca7
NEON use vmov.i32 to splat some f32 values into vectors.
...
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
llvm-svn: 148556
2012-01-20 18:09:51 +00:00
084b9f4134
Remove a bunch of unused variable assignments.
...
Found by the clang static analyzer.
llvm-svn: 148541
2012-01-20 14:42:32 +00:00
a409479023
Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
...
llvm-svn: 148537
2012-01-20 09:29:03 +00:00
3469212c82
Add support for selecting 256-bit PALIGNR.
...
llvm-svn: 148532
2012-01-20 05:53:00 +00:00
32c7c25dcb
Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
...
llvm-svn: 148513
2012-01-20 00:05:46 +00:00
116e99a469
Silence warnings about mixing enums.
...
llvm-svn: 148495
2012-01-19 21:11:13 +00:00
f83dcfd052
Post process 'and', 'sub' instructions and select better encoding, if available.
...
llvm-svn: 148489
2012-01-19 18:40:55 +00:00
2529dd9e00
Intel syntax: There is no need to create unary expr for simple negative displacement.
...
llvm-svn: 148486
2012-01-19 18:15:51 +00:00
4a62ff9bcb
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
...
llvm-svn: 148485
2012-01-19 17:53:25 +00:00
4c7eb477b5
Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.
...
llvm-svn: 148473
2012-01-19 12:53:06 +00:00
a875b7ccc7
Folding table additions and fixes for AVX.
...
llvm-svn: 148467
2012-01-19 08:50:38 +00:00
80576e8d1f
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
...
llvm-svn: 148466
2012-01-19 08:19:12 +00:00
235c8d2d94
ARM assembly diagnostic caret in better position for FPImm.
...
llvm-svn: 148459
2012-01-19 02:47:30 +00:00
44e5c39c29
Thumb2 relaxation for tADR to t2ADR.
...
llvm-svn: 148456
2012-01-19 02:09:38 +00:00
b008df40d3
Add comment and fix range check in condition.
...
llvm-svn: 148455
2012-01-19 01:50:30 +00:00
2879467d4e
- Slight change to finalizeBundle() interface. LastMI is not exclusive (pointing
...
to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
will find the last instruction in the bundle by following the 'InsideBundle'
marker. This is useful in case bundles are formed early (i.e. during MI
scheduling) but finalized later (i.e. after register allocator has finished
rewriting virtual registers with physical registers).
llvm-svn: 148444
2012-01-19 00:46:06 +00:00
ecc0084f72
Add a TargetOption for disabling tail calls.
...
llvm-svn: 148442
2012-01-19 00:34:10 +00:00
1eb2bb2295
Rename Finalizebundle to finalizeBundle to conform to coding guideline.
...
llvm-svn: 148440
2012-01-19 00:06:10 +00:00
ff482f733b
Add experimental -x86-use-regmask command line option.
...
It adds register mask operands to x86 call instructions. Once all the
backend passes support register mask operands, this will be permanently
enabled.
llvm-svn: 148438
2012-01-18 23:52:22 +00:00
f1fb1d2375
Ignore register mask operands when lowering instructions to MC.
...
This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.
llvm-svn: 148437
2012-01-18 23:52:19 +00:00
94298a906a
Thumb2 alternate syntax for LDR(literal) and friends.
...
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
llvm-svn: 148432
2012-01-18 22:46:46 +00:00
de47cced25
Process instructions after match to select alternative encoding which may be more desirable.
...
llvm-svn: 148431
2012-01-18 22:42:29 +00:00
cbd3f27354
Replace FIXME with explanatory comment.
...
llvm-svn: 148427
2012-01-18 22:04:42 +00:00
cb80eb2e75
Thumb2 relaxation for LDR(literal).
...
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.
rdar://10711829
llvm-svn: 148424
2012-01-18 21:54:16 +00:00
9ab3d8be4e
Rename pattern for clarity.
...
llvm-svn: 148422
2012-01-18 21:54:09 +00:00
e2d298168c
Tidy up. 80 columns.
...
llvm-svn: 148401
2012-01-18 18:52:20 +00:00
aba3de99c0
Tidy up. MCAsmBackend naming conventions.
...
llvm-svn: 148400
2012-01-18 18:52:16 +00:00
adcc938c46
Thumb2 load/store fixups don't set the thumb bit.
...
Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.
rdar://10348687.
llvm-svn: 148366
2012-01-18 00:40:25 +00:00
3b50c9ec7f
Move some ARM specific MCAssmebler bits into the ARMAsmBackend.
...
llvm-svn: 148364
2012-01-18 00:23:57 +00:00
f43b599550
Add a CoveredBySubRegs property to Register descriptions.
...
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
llvm-svn: 148363
2012-01-18 00:16:39 +00:00
fdbb12b235
Implement ARMBaseRegisterInfo::getCallPreservedMask().
...
Move ARM callee-saved lists into ARMCallingConv.td.
llvm-svn: 148357
2012-01-17 23:09:00 +00:00
d51a710bde
Move X86 callee saved register lists to the X86CallConv .td file.
...
Add a trivial implementation of the getCallPreservedMask() hook.
llvm-svn: 148347
2012-01-17 22:47:01 +00:00
c9ed518792
Intel syntax: Fix parser match class to check memory operand size.
...
llvm-svn: 148338
2012-01-17 21:48:03 +00:00
a7143b6a2b
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
...
llvm-svn: 148334
2012-01-17 21:25:10 +00:00
2ed6718616
Untabify.
...
llvm-svn: 148322
2012-01-17 19:09:22 +00:00
8b39be79ad
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
...
llvm-svn: 148321
2012-01-17 19:08:07 +00:00
41b9ddeb7a
Intel syntax: Robustify memory operand parsing.
...
llvm-svn: 148312
2012-01-17 18:00:18 +00:00
86c3807b99
Fix warning.
...
llvm-svn: 148301
2012-01-17 09:31:09 +00:00
86e5390dbf
Fix 11769.
...
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.
llvm-svn: 148298
2012-01-17 09:13:19 +00:00
9cafcd8baa
Remove unnecessary AVX check from an assert. hasSSE2 is enough.
...
llvm-svn: 148295
2012-01-17 08:23:44 +00:00
8093eac51d
Moving options declarations around.
...
More short term hackery until we have a way to configure passes that work on LiveIntervals.
llvm-svn: 148289
2012-01-17 06:54:59 +00:00
37b10ef250
Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
...
llvm-svn: 148285
2012-01-17 04:44:50 +00:00
486df738c3
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
...
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)
llvm-svn: 148262
2012-01-16 23:24:27 +00:00
b1691ccaaa
Cleanup PPC RLWINM8 vs RLWINM
...
No test case: output assembly will be identical.
llvm-svn: 148261
2012-01-16 23:22:50 +00:00
206ca569aa
Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.
...
llvm-svn: 148240
2012-01-16 16:42:21 +00:00
75e3db4c7a
Get rid of unused codegen-only instruction.
...
llvm-svn: 148239
2012-01-16 16:29:35 +00:00
db8890aedd
Give priority to AVX over SSE for 128-bit floating point unpck instructions.
...
llvm-svn: 148233
2012-01-16 09:56:42 +00:00
5d8e42755c
Refactor variables unused under non-assert builds (& remove two entirely unused variables).
...
llvm-svn: 148230
2012-01-16 05:17:39 +00:00
57935243bd
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.
...
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.
Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.
llvm-svn: 148225
2012-01-15 19:27:55 +00:00
339ced4e34
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
...
llvm-svn: 148218
2012-01-15 13:16:05 +00:00
c10e1abaf3
Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem.
...
llvm-svn: 148196
2012-01-14 18:29:57 +00:00
d78429f850
Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions.
...
llvm-svn: 148194
2012-01-14 18:14:53 +00:00
6bb95253eb
After r147827 and r147902, it's now possible for unallocatable registers to be
...
live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
cbnz r6, LBB89_12
...
LBB89_12:
ble LBB89_1
The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.
rdar://10676853
llvm-svn: 148168
2012-01-14 01:53:46 +00:00
71a185c5c6
Fix pasto from r146196.
...
llvm-svn: 148167
2012-01-14 01:50:21 +00:00
35545421c8
Use RegisterTuples to generate pseudo-registers.
...
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.
This makes the call clobber lists longer, but I intend to get rid of
those soon.
llvm-svn: 148151
2012-01-13 22:55:42 +00:00
7066d28043
Revert r148131, it was committed before it was ready.
...
llvm-svn: 148134
2012-01-13 19:28:58 +00:00
7ecdc6d4f5
Refactor.
...
llvm-svn: 148131
2012-01-13 19:12:18 +00:00
e52d86a740
Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted.
...
llvm-svn: 148112
2012-01-13 09:21:41 +00:00
b1c2ebf6ee
use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1.
...
llvm-svn: 148109
2012-01-13 08:32:21 +00:00
cb7e13d7c0
Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
...
llvm-svn: 148108
2012-01-13 08:12:35 +00:00
9f14d9f939
Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32.
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llvm-svn: 148106
2012-01-13 06:59:47 +00:00
e77e84e4b7
Added the MachineSchedulerPass skeleton.
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llvm-svn: 148105
2012-01-13 06:30:30 +00:00
a4c5a47b97
Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750.
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llvm-svn: 148101
2012-01-13 06:12:41 +00:00
2aa07f832e
Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
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llvm-svn: 148096
2012-01-13 05:04:25 +00:00
9c8456f7ef
Fix off-by-one error.
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llvm-svn: 148077
2012-01-13 00:41:53 +00:00
ee5eaebc58
Fix the code that was WRONG.
...
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.
llvm-svn: 148064
2012-01-12 23:05:03 +00:00
060f6ccdb8
Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure
...
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed.
Added a test.
llvm-svn: 148044
2012-01-12 20:33:10 +00:00
00e861ed57
Support segmented stacks on 64-bit FreeBSD.
...
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.
llvm-svn: 148041
2012-01-12 20:24:30 +00:00
10745d3381
Support segmented stacks on win32.
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Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.
llvm-svn: 148040
2012-01-12 20:22:08 +00:00
4a6e778aae
Rename X86ATTAsmParser -> X86AsmParser
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We are using one parser to parse att as well as intel style syntax.
llvm-svn: 148032
2012-01-12 18:03:40 +00:00
9ece950ddb
After Jakob's r147938 exception handling on i386 was completely broken.
...
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.
This should fix nightly tester failures.
llvm-svn: 148030
2012-01-12 17:37:18 +00:00
0a0a829bea
Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors.
...
The attached testcase was stuck in an endless loop.
llvm-svn: 148027
2012-01-12 15:31:55 +00:00
5b3aa60b44
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63.
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llvm-svn: 148024
2012-01-12 12:41:34 +00:00
fc6be102ae
Add predicate method check match memory operand size, if available.
...
In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.
llvm-svn: 148006
2012-01-12 01:51:42 +00:00
46831de240
Add intel style operand parser skeleton.
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This is a work in progress.
llvm-svn: 148002
2012-01-12 01:36:43 +00:00
eb21da060b
Switch all of the uses of my InsertDAGNode helper to follow the exact
...
same pattern. We already had this pattern is a few places, but others
tried to make a rough approximation of an actual DAG structure. As not
everywhere went to this trouble, nothing could rely on this being done.
In fact, I've checked all references to these node Ids, and the ones
that are using the topo-sort properties are actually satisfied with
a strict-weak-ordering. The requirement appears to be that Use >= Def.
I've added a big blurb of comments to this bit of the transform to
clarify why the order is so important for the next reader of the code.
I'm starting with this change as it is very small, and trivially
reverted if something breaks or the >= above really does need to be >.
If that proves the case, we can hide the problem by reverting this
patch, but the problem exists elsewhere as well, and so a more
comprehensive solution will be needed.
llvm-svn: 148001
2012-01-12 01:34:44 +00:00
d284c1d80d
Fix assert.
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llvm-svn: 147966
2012-01-11 20:55:27 +00:00
d90466bcbf
Support segmented stacks on mac.
...
This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support
frames with static size
Patch by Brian Anderson.
llvm-svn: 147960
2012-01-11 19:00:37 +00:00
4eecacb9c8
Generate the segmented stack prologue for fastcc too.
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Patch by Brian Anderson.
llvm-svn: 147958
2012-01-11 18:41:19 +00:00
3212a34269
Revert r147945 which disabled an addressing mode transformation. I had
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hoped this would revive one of the llvm-gcc selfhost build bots, but it
didn't so it doesn't appear that my transform is the culprit.
If anyone else is seeing failures, please let me know!
llvm-svn: 147957
2012-01-11 18:36:12 +00:00
2b89448d60
Use unsigned comparison in segmented stack prologue.
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This is a comparison of two addresses, and GCC does the comparison unsigned.
Patch by Brian Anderson.
llvm-svn: 147954
2012-01-11 18:23:35 +00:00
6635ae1c17
Explicitly set the scale to 1 on some segstack prologue instrs.
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Patch by Brian Anderson.
llvm-svn: 147952
2012-01-11 18:14:03 +00:00
21f83d9f36
Add XOP Intrinsics and tests
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llvm-svn: 147949
2012-01-11 15:20:20 +00:00
baae7e4577
Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead.
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llvm-svn: 147948
2012-01-11 14:07:51 +00:00
9bc48e5215
Disable the transformation I added in r147936 to see if it fixes some
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strange build bot failures that look like a miscompile into an infloop.
I'll investigate this tomorrow, but I'd both like to know whether my
patch is the culprit, and get the bots back to green.
llvm-svn: 147945
2012-01-11 12:17:47 +00:00
3eacfb83fa
Hoist a really redundant code pattern into a helper function, and delete
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lots of lines of code. No functionality changed.
llvm-svn: 147942
2012-01-11 11:04:36 +00:00
b0049f4a43
Simplify the AND-rooted mask+shift checking code to match that of the
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SRL-rooted code.
llvm-svn: 147941
2012-01-11 09:35:04 +00:00
3dbcda8478
Unify the interface of the three mask+shift transform helpers, and
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factor the differences that were hiding in one of them into its other
caller, the SRL handling code. No change in behavior.
llvm-svn: 147940
2012-01-11 09:35:02 +00:00
aa01e6661a
Clarify and make explicit some of the requirements for transforming
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mask+shift pairs at the beginning of the ISD::AND case block, and then
hoist the final pattern into a helper function, simplifying and
reflowing it appropriately. This should have no observable behavior
change, but several simplifications fell out of this such as directly
computing the new mask constant, etc.
llvm-svn: 147939
2012-01-11 09:35:00 +00:00
6039983755
Fix undefined code and reenable test case.
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I don't think the compact encoding code is right, but at least is has
defined behavior now.
llvm-svn: 147938
2012-01-11 09:08:04 +00:00
51d3076bbf
Hoist the logic to transform shift+mask combinations into sub-register
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extracts and scaled addressing modes into its own helper function. No
functionality changed here, just hoisting and layout fixes falling out
of that hoisting.
llvm-svn: 147937
2012-01-11 08:48:20 +00:00
55b2cdee26
Teach the X86 instruction selection to do some heroic transforms to
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detect a pattern which can be implemented with a small 'shl' embedded in
the addressing mode scale. This happens in real code as follows:
unsigned x = my_accelerator_table[input >> 11];
Here we have some lookup table that we look into using the high bits of
'input'. Each entity in the table is 4-bytes, which means this
implicitly gets turned into (once lowered out of a GEP):
*(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2));
The shift right followed by a shift left is canonicalized to a smaller
shift right and masking off the low bits. That hides the shift right
which x86 has an addressing mode designed to support. We now detect
masks of this form, and produce the longer shift right followed by the
proper addressing mode. In addition to saving a (rather large)
instruction, this also reduces stalls in Intel chips on benchmarks I've
measured.
In order for all of this to work, one part of the DAG needs to be
canonicalized *still further* than it currently is. This involves
removing pointless 'trunc' nodes between a zextload and a zext. Without
that, we end up generating spurious masks and hiding the pattern.
llvm-svn: 147936
2012-01-11 08:41:08 +00:00
647841b181
Add big endian mips support. Based on a patch by Jack Carter.
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llvm-svn: 147924
2012-01-11 04:04:14 +00:00
870c4e92b9
Add the skeleton of an asm parser for mips.
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llvm-svn: 147923
2012-01-11 03:56:41 +00:00
642f0f6a40
ARM Ld/St Optimizer fix.
...
Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits.
Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12
llvm-svn: 147922
2012-01-11 03:56:08 +00:00
995c63329a
Fixed order of operands in comment to match code.
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llvm-svn: 147890
2012-01-10 22:53:20 +00:00
96cd35cf6d
Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.
...
Add a test that checks the stack alignment of a simple function for
Darwin, Linux and NetBSD for 32bit and 64bit mode.
llvm-svn: 147888
2012-01-10 22:43:53 +00:00
20f1dd5faf
Consider unknown alignment caused by OptimizeThumb2Instructions().
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This function runs after all constant islands have been placed, and may
shrink some instructions to their 2-byte forms. This can actually cause
some constant pool entries to move out of range because of growing
alignment padding.
Treat instructions that may be shrunk the same as inline asm - they
erode the known alignment bits.
Also reinstate an old assertion in verify(). It is correct now that
basic block offsets include alignments.
Add a single large test case that will hopefully exercise many parts of
the constant island pass.
<rdar://problem/10670199>
llvm-svn: 147885
2012-01-10 22:32:14 +00:00
1a8f0ccd8c
Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a few
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failing test cases on our internal AVX nightly tester.
rdar://10663637
llvm-svn: 147881
2012-01-10 22:14:06 +00:00
74ac7d50a1
ARM updating VST2 pseudo-lowering fixed vs. register update.
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rdar://10663487
llvm-svn: 147876
2012-01-10 21:11:12 +00:00
233149cf06
Fix some leftover control reaches end of non-void function warnings.
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llvm-svn: 147874
2012-01-10 20:47:20 +00:00
ad5b42c02f
Move default case for covered enum outside of switch.
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llvm-svn: 147870
2012-01-10 19:43:09 +00:00
d5ab02600e
For i386, don't use the generic code.
...
As the comment around 7746 says, it's better to use the x87 extended precision
here than SSE. And the generic code doesn't know how to do that. It also regains
the speed lost for the uint64_to_float.c testcase.
<rdar://problem/10669858>
llvm-svn: 147869
2012-01-10 19:41:30 +00:00
3f1035410f
Fix a -Wreturn-type warning in g++.
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llvm-svn: 147867
2012-01-10 19:10:22 +00:00
f3e8502cc1
Add 'llvm_unreachable' to passify GCC's understanding of the constraints
...
of several newly un-defaulted switches. This also helps optimizers
(including LLVM's) recognize that every case is covered, and we should
assume as much.
llvm-svn: 147861
2012-01-10 18:08:01 +00:00
67bf992a8f
Add definition for intel asm variant.
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Right now, this just adds additional entries in match table. The parser does not use them yet.
llvm-svn: 147859
2012-01-10 17:51:54 +00:00
edbb58c577
Remove unnecessary default cases in switches that cover all enum values.
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llvm-svn: 147855
2012-01-10 16:47:17 +00:00
077ae1d760
Add definitions for AMD's bobcat (aka btver1)
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llvm-svn: 147846
2012-01-10 11:50:02 +00:00
430f3f1bd6
Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside.
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llvm-svn: 147844
2012-01-10 08:23:59 +00:00
b0c0f72ae6
Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is the final piece to remove the AVX hack that disabled SSE.
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llvm-svn: 147843
2012-01-10 06:54:16 +00:00
d97bbd7b60
Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. AVX is now an SSE level and no longer disables SSE checks.
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llvm-svn: 147842
2012-01-10 06:37:29 +00:00
eb8f9e9e5b
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget.
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llvm-svn: 147841
2012-01-10 06:30:56 +00:00
f09a316542
Accurately model hardware alignment rounding.
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On Thumb, the displacement computation hardware uses the address of the
current instruction rouned down to a multiple of 4. Include this
rounding in the UserOffset we compute for each instruction.
When inline asm is present, the instruction alignment may not be known.
Constrain the maximum displacement instead in that case.
This makes it possible for CreateNewWater() and OffsetIsInRange() to
agree about the valid displacements. When they disagree, infinite
looping happens.
As always, test cases for this stuff are insane.
<rdar://problem/10660175>
llvm-svn: 147825
2012-01-10 01:34:59 +00:00
5cb98f1062
Remove the logging streamer.
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llvm-svn: 147820
2012-01-10 00:40:39 +00:00
1a80e3a26b
Catch runaway ARMConstantIslandPass even in -Asserts builds.
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The pass is prone to looping, and it is better to crash than loop
forever, even in a -Asserts build.
<rdar://problem/10660175>
llvm-svn: 147806
2012-01-09 22:16:24 +00:00
29ba4f97e6
Fix asm string wrt variants.
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llvm-svn: 147805
2012-01-09 21:32:02 +00:00
85d684a4d9
Split AsmParser into two components - AsmParser and AsmParserVariant
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AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.
llvm-svn: 147787
2012-01-09 19:13:28 +00:00
c16622daff
Don't rely on the fact that shift values are never very large, and thus
...
this substraction will result in small negative numbers at worst which
become very large positive numbers on assignment and are thus caught by
the <=4 check on the next line. The >0 check clearly intended to catch
these as negative numbers.
Spotted by inspection, and impossible to trigger given the shift widths
that can be used.
llvm-svn: 147773
2012-01-09 09:47:25 +00:00
f287a4509e
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.
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llvm-svn: 147770
2012-01-09 09:02:13 +00:00
b89805c77d
Add HasAVX predicate to some of the AVX patterns.
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llvm-svn: 147769
2012-01-09 08:34:00 +00:00
a51f7f75c2
Reorder a bunch of patterns to put the AVX version first thus giving it priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget.
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llvm-svn: 147768
2012-01-09 08:10:38 +00:00
ef7f5bf8c9
Clean up patterns for MOVNT*. Not sure why there were floating point types on MOVNTPS and MOVNTDQ. And v4i64 was completely missing.
...
llvm-svn: 147767
2012-01-09 06:52:46 +00:00
c1f5622ad3
Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no AVX equivalent so we should use the SSE version.
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llvm-svn: 147766
2012-01-09 06:38:55 +00:00
a081644f8a
Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues.
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llvm-svn: 147765
2012-01-09 05:07:01 +00:00
210e4f81b3
Change some places that were checking for AVX OR SSE1/2 to use hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h
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llvm-svn: 147764
2012-01-09 02:28:15 +00:00
744f6311d3
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
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llvm-svn: 147762
2012-01-09 00:11:29 +00:00
c1ab7afec8
Enable FISTTP* instructions when AVX is enabled.
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llvm-svn: 147758
2012-01-08 23:04:21 +00:00
4882e488f7
Don't forget to transfer implicit uses of return instruction.
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llvm-svn: 147752
2012-01-08 20:41:16 +00:00
540651cf59
Reverted commit #147601 upon Evan's request.
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llvm-svn: 147748
2012-01-08 17:20:33 +00:00
083dbdca7f
Match SelectionDAG logic for enabling movt.
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Darwin doesn't do static, and ELF targets only support static.
llvm-svn: 147740
2012-01-07 20:49:15 +00:00
f210619d08
Fix typo in the X86 backend readme. Patch from Jaeden Amero.
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llvm-svn: 147739
2012-01-07 20:35:21 +00:00
6898db6269
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
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llvm-svn: 147738
2012-01-07 19:42:13 +00:00
ca66bba45e
Remove unnecessary check of hasAVX(). It's already included in hasXMM().
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llvm-svn: 147734
2012-01-07 18:48:43 +00:00
8cdce7e690
Use getRegForValue() to materialize the address of ARM globals.
...
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.
<rdar://problem/10658692>
llvm-svn: 147720
2012-01-07 04:07:22 +00:00
0708209642
Split Finish into Finish and FinishImpl to have a common place to do end of
...
file error checking. Use that to error on an unfinished cfi_startproc.
The error is not nice, but is already better than a segmentation fault.
llvm-svn: 147717
2012-01-07 03:13:18 +00:00
501e3095e8
Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug is
...
exposed with an upcoming change will would delete the copy to return register
because there is no use! It's amazing anything works.
llvm-svn: 147715
2012-01-07 02:55:54 +00:00
68f034ee1a
Use movw+movt in ARMFastISel::ARMMaterializeGV.
...
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.
This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.
<rdar://problem/10629774>
llvm-svn: 147712
2012-01-07 01:47:05 +00:00
c206d46709
Make the 'x' constraint work for AVX registers as well.
...
Fixes rdar://10614894
llvm-svn: 147704
2012-01-07 01:02:09 +00:00
68a922c0e9
Enable aligned NEON spilling by default.
...
Experiments show this to be a small speedup for modern ARM cores.
llvm-svn: 147689
2012-01-06 22:19:37 +00:00
690511137c
Abort AdjustBBOffsetsAfter early when possible.
...
llvm-svn: 147685
2012-01-06 21:40:15 +00:00
64dc8aa44f
Initializing to false makes better sense. Thanks, David.
...
llvm-svn: 147679
2012-01-06 20:11:59 +00:00
a3d90a9467
Fix uninitialized variable warning.
...
llvm-svn: 147676
2012-01-06 20:02:49 +00:00
6b64c3c683
Fix uninitialized variable warning.
...
llvm-svn: 147675
2012-01-06 19:59:58 +00:00
29b0737452
Mark scalar FMA4 instructions as ignoring the VEX.L bit.
...
llvm-svn: 147602
2012-01-05 08:56:10 +00:00
9255b6d9fe
Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX.
...
Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX)
Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov
llvm-svn: 147601
2012-01-05 08:46:19 +00:00
ac27f0c830
Replace the uint64_t -> double convertion algorithm with one that's more efficient.
...
This small bit of ASM code is sufficient to do what the old algorithm did:
movq %rax, %xmm0
punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
#ifdef __SSE3__
haddpd %xmm0, %xmm0
#else
pshufd $0x4e, %xmm0, %xmm1
addpd %xmm1, %xmm0
#endif
It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on
all processors.
<rdar://problem/7719814>
llvm-svn: 147593
2012-01-05 02:13:20 +00:00
d110e2a83f
Reapply r146997, "Heed spill slot alignment on ARM."
...
Now that canRealignStack() understands frozen reserved registers, it is
safe to use it for aligned spill instructions.
It will only return true if the registers reserved at the beginning of
register allocation allow for dynamic stack realignment.
<rdar://problem/10625436>
llvm-svn: 147579
2012-01-05 00:26:57 +00:00
9cb477db25
Avoid reserving an ARM base pointer during register allocation.
...
Once register allocation has started the reserved registers are frozen.
Fix the ARM canRealignStack() hook to respect the frozen register state.
Now the hook returns false if register allocation was started with frame
pointer elimination enabled.
It also returns false if register allocation started without a reserved
base pointer, and stack realignment would require a base pointer. This
bug was breaking oggenc on armv6.
No test case, an upcoming patch will use this functionality to realign
the stack for spill slots when possible.
llvm-svn: 147578
2012-01-05 00:26:52 +00:00
9c48f26341
Silence warnings of a mysterious compiler that still defaults to C89.
...
llvm-svn: 147553
2012-01-04 22:06:45 +00:00
aac3e06bf7
Enable -soft-float for MIPS.
...
llvm-svn: 147541
2012-01-04 19:29:11 +00:00
3b775b8cc3
Rename immLUiOpnd.
...
llvm-svn: 147519
2012-01-04 03:09:26 +00:00
b89a4bfe41
- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit
...
versions derive from them.
- JALR64 is not needed since N64 does not emit jal.
- Add template parameter to BranchLink that sets the rt field.
- Fix the set of temporary registers for O32 and N64.
llvm-svn: 147518
2012-01-04 03:02:47 +00:00
c669d7a6db
Have getRegForInlineAsmConstraint return the correct register class when target
...
is Mips64.
llvm-svn: 147516
2012-01-04 02:45:01 +00:00
801d98b3f0
Fix more places which should be checking for iOS, not darwin.
...
llvm-svn: 147513
2012-01-04 01:55:04 +00:00
104dbb0fd1
For x86, canonicalize max
...
(x > y) ? x : y
=>
(x >= y) ? x : y
So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0
This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl %esi, %edi
testl %edi, %edi
movl $0, %eax
cmovgl %edi, %eax
=>
xorl %eax, %eax
subl %esi, $edi
cmovsl %eax, %edi
rdar://10633221
llvm-svn: 147512
2012-01-04 01:41:39 +00:00
6ca97df951
Fix 80-column violations.
...
llvm-svn: 147495
2012-01-03 23:19:12 +00:00
1b7f2a7638
Revert r146997, "Heed spill slot alignment on ARM."
...
This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.
<rdar://problem/10625436>
llvm-svn: 147487
2012-01-03 22:34:35 +00:00
6d31bac85e
Revert 147426 because it caused pr11696.
...
llvm-svn: 147485
2012-01-03 22:19:42 +00:00
493c1b3152
Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather
...
then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409
llvm-svn: 147481
2012-01-03 21:05:52 +00:00
b982d8eb65
Fix malformed assert.
...
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.
llvm-svn: 147459
2012-01-03 19:03:59 +00:00
c1215324a3
Intel style asm variant does not need '%' prefix.
...
llvm-svn: 147453
2012-01-03 18:22:10 +00:00
5bacb7e9e5
Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions.
...
llvm-svn: 147430
2012-01-02 09:17:37 +00:00
53d559641f
Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection.
...
llvm-svn: 147428
2012-01-02 08:46:48 +00:00
6c7a0e6c8b
Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.
...
llvm-svn: 147426
2012-01-02 08:05:46 +00:00
b910984458
Allow CRC32 instructions to be selected when AVX is enabled.
...
llvm-svn: 147411
2012-01-01 19:51:58 +00:00
1c064e0a89
Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
...
llvm-svn: 147409
2012-01-01 19:40:22 +00:00
47aecca51a
X86Disassembler: Fix undefined behavior found by GCC 4.6
...
llvm-svn: 147404
2012-01-01 17:55:36 +00:00
6e54ba7eee
Merge X86 SHUFPS and SHUFPD node types.
...
llvm-svn: 147394
2011-12-31 23:50:21 +00:00
d51092d93a
Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load.
...
llvm-svn: 147393
2011-12-31 23:24:49 +00:00
0e796fee11
Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected.
...
llvm-svn: 147392
2011-12-31 23:15:11 +00:00
cd1d447d62
Cleanup Mips code and rename some variables. Patch by Jack Carter
...
llvm-svn: 147383
2011-12-30 21:09:41 +00:00
d5b2834fb7
Improve Mips JIT.
...
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.
Patch by Sasa Stankovic
llvm-svn: 147382
2011-12-30 21:04:30 +00:00
a5d1fc2cc7
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal.
...
llvm-svn: 147369
2011-12-30 07:16:00 +00:00
2ba766ae84
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
...
llvm-svn: 147368
2011-12-30 06:23:39 +00:00
03a0beda88
Add FMA4 instructions to disassembler.
...
llvm-svn: 147367
2011-12-30 05:20:36 +00:00
cd93de93fa
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
...
llvm-svn: 147366
2011-12-30 04:48:54 +00:00
c0f9bcb5d5
Combine FMA4 SS/SD patterns with the instruction definitions.
...
llvm-svn: 147365
2011-12-30 03:33:59 +00:00
51fe43fcd9
Combine FMA4 PS/PD patterns with the instruction definitions.
...
llvm-svn: 147364
2011-12-30 03:17:15 +00:00
6c08930c5e
Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms.
...
llvm-svn: 147361
2011-12-30 02:18:36 +00:00
2ca79b9d4b
Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.
...
llvm-svn: 147360
2011-12-30 01:49:53 +00:00
692d1fb355
Cleanup stack/frame register define/kill states. This fixes two bugs:
...
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
llvm-svn: 147359
2011-12-30 00:34:00 +00:00
d773607eee
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
...
llvm-svn: 147353
2011-12-29 20:43:40 +00:00
8cab06a214
Expose FMA3 instructions to the disassembler.
...
llvm-svn: 147351
2011-12-29 20:03:14 +00:00
e1bd05128e
Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled.
...
llvm-svn: 147349
2011-12-29 19:46:19 +00:00
dd286a5201
Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.
...
llvm-svn: 147348
2011-12-29 19:25:56 +00:00
a060afb5ba
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339.
...
llvm-svn: 147347
2011-12-29 18:47:31 +00:00
97f05c5768
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.
...
llvm-svn: 147345
2011-12-29 18:08:36 +00:00
1559123c77
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.
...
llvm-svn: 147344
2011-12-29 18:00:08 +00:00
9e61291bf5
Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns.
...
llvm-svn: 147342
2011-12-29 17:41:56 +00:00
7bd3305f3e
Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A.
...
llvm-svn: 147339
2011-12-29 15:51:45 +00:00
0fdf720ded
Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8.
...
llvm-svn: 147337
2011-12-29 03:34:54 +00:00
862c9b65be
Remove some elses after returns.
...
llvm-svn: 147336
2011-12-29 03:20:51 +00:00
274e20a499
Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path.
...
llvm-svn: 147335
2011-12-29 03:09:33 +00:00
3a01ddb7e9
Fix type-checking for load transformation which is not legal on floating-point types. PR11674.
...
llvm-svn: 147323
2011-12-28 21:24:44 +00:00
b3515a8d4b
Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.
...
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.
llvm-svn: 147308
2011-12-28 08:14:01 +00:00
b668401b2e
Clean up some Release build warnings.
...
llvm-svn: 147289
2011-12-27 11:41:05 +00:00
df34d152bd
Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't.
...
llvm-svn: 147287
2011-12-27 06:27:23 +00:00
1fc8263b4d
Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks.
...
llvm-svn: 147269
2011-12-25 18:50:24 +00:00
a56ab0ede7
Section relative fixups are a coff concept, not a x86 one. Replace the
...
x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.
llvm-svn: 147252
2011-12-24 14:47:52 +00:00
a3d54fe0ae
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the
...
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type
We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]
llvm-svn: 147251
2011-12-24 12:12:34 +00:00
38ce24455d
Add systematic testing for cttz as well, and fix the bug I spotted by
...
inspection earlier.
llvm-svn: 147250
2011-12-24 11:46:10 +00:00
767bbe48c1
Chandler fixed this.
...
llvm-svn: 147247
2011-12-24 11:23:32 +00:00
c9fcde2347
Expand more when we have a nice 'tzcnt' instruction, to avoid generating
...
'bsf' instructions here.
This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.
llvm-svn: 147246
2011-12-24 11:11:38 +00:00
7e9453e916
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the
...
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:
(sizeof(x)*8 - 1) ^ __builtin_clz(x)
Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.
The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.
Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.
These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.
llvm-svn: 147244
2011-12-24 10:55:54 +00:00
103318e9ea
Fix Comments.
...
llvm-svn: 147238
2011-12-24 04:17:01 +00:00
1cf7576707
Add MachineMemOperands to instructions generated in storeRegToStackSlot or
...
loadRegFromStackSlot.
llvm-svn: 147235
2011-12-24 03:11:18 +00:00
6f54a46133
Detect unaligned loads/stores that have been added for Mips64 support.
...
llvm-svn: 147234
2011-12-24 03:07:37 +00:00
695d113adc
If target ABI is N64, LEA should be daddiu.
...
llvm-svn: 147232
2011-12-24 02:59:27 +00:00
908d2ed14e
Move x86 specific bits of the COFF writer to lib/Target/X86.
...
llvm-svn: 147231
2011-12-24 02:14:02 +00:00
0965585cb1
Experimental support for aligned NEON spills.
...
ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.
Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.
This feature is off by default, controlled by an -align-neon-spills
command line option.
llvm-svn: 147211
2011-12-23 00:36:18 +00:00
1a74de9504
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
...
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
llvm-svn: 147204
2011-12-22 23:39:48 +00:00
00bbedff03
Fix 80-column violations.
...
llvm-svn: 147192
2011-12-22 22:35:21 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
...
rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
268d2599e0
Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.
...
Noticed by inspection; I don't have a testcase for this.
llvm-svn: 147188
2011-12-22 22:12:44 +00:00
c4d8d2f155
Tidy up. Use predicate function a bit more liberally.
...
llvm-svn: 147184
2011-12-22 22:02:35 +00:00
6ca42c5be3
Fix incorrect relocation generation. Patch by Kristof Beyls.
...
Fixes PR11214.
llvm-svn: 147180
2011-12-22 21:36:43 +00:00
f0d25117c6
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
...
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
llvm-svn: 147170
2011-12-22 19:55:21 +00:00
b65dd04923
Remove some bogus comments.
...
llvm-svn: 147169
2011-12-22 19:45:01 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
...
llvm-svn: 147158
2011-12-22 19:20:45 +00:00
250096233b
Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting
...
it. It does need some some tests...
llvm-svn: 147154
2011-12-22 18:38:06 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
...
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
21488b8839
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
...
llvm-svn: 147152
2011-12-22 17:37:00 +00:00
3794d82af5
Tidy up. Trailing whitespace.
...
llvm-svn: 147151
2011-12-22 17:17:10 +00:00
62bffd8827
Nuke invalid comment from copy/paste.
...
llvm-svn: 147150
2011-12-22 17:04:50 +00:00
1dc45d8df4
Move the Mips only bits of the ELF writer to lib/Target/Mips.
...
llvm-svn: 147133
2011-12-22 03:03:17 +00:00
84d00f11cd
Make the virtual methods in ARMELFObjectWriter public.
...
llvm-svn: 147132
2011-12-22 02:58:12 +00:00
cc369ac0a2
Move the MBlaze ELF writer bits to lib/Target/MBlaze.
...
llvm-svn: 147129
2011-12-22 02:28:24 +00:00
428b9ee036
Fix cmake.
...
llvm-svn: 147126
2011-12-22 02:06:17 +00:00
38a400df3b
Move PPC bits to lib/Target/PowerPC.
...
llvm-svn: 147124
2011-12-22 01:57:09 +00:00
2da9777cef
Hopefully fix the cmake build.
...
llvm-svn: 147121
2011-12-22 01:11:01 +00:00
4449b21294
Fix name in comments.
...
llvm-svn: 147119
2011-12-22 01:06:53 +00:00
e2eed9649e
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
...
ELF relocations.
Patch by Jack Carter.
llvm-svn: 147118
2011-12-22 01:05:17 +00:00
32a756b7ce
Unbreak cmake build after r147115.
...
llvm-svn: 147117
2011-12-22 01:03:35 +00:00
a0124055b1
Move the ARM specific parts of the ELF writer to Target/ARM.
...
llvm-svn: 147115
2011-12-22 00:37:50 +00:00
2b80dad572
ARM NEON mnemonic aliase for vrecpeq.
...
llvm-svn: 147109
2011-12-21 23:52:37 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
...
llvm-svn: 147104
2011-12-21 23:24:15 +00:00
260b4b336a
ARM NEON optional data type on VSWP instructions.
...
llvm-svn: 147103
2011-12-21 23:09:28 +00:00
a50e24fcb3
ARM NEON mnemonic aliases for vzipq and vswpq.
...
llvm-svn: 147102
2011-12-21 23:04:33 +00:00
1152cc0cad
ARM asm parser should be more lenient w/ .thumb_func directive.
...
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
3172488cc0
Fix 80-column violations.
...
llvm-svn: 147095
2011-12-21 20:59:09 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
3588a43e3a
Move common code into an MRI function.
...
llvm-svn: 147071
2011-12-21 19:50:05 +00:00
c80a264386
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
...
llvm-svn: 147069
2011-12-21 19:40:55 +00:00
3ede414127
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
...
necessary. Please chime in if I'm mistaken.
llvm-svn: 147065
2011-12-21 19:14:52 +00:00
7248bda595
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
...
llvm-svn: 147064
2011-12-21 18:56:22 +00:00
b264d33854
Move the X86 specific bits of the ELF writer to the Target/X86 directory.
...
Other targets will follow shortly.
llvm-svn: 147060
2011-12-21 17:30:17 +00:00
1ad4095d6b
Reduce the exposure of Triple::OSType in the ELF object writer. This will
...
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
2011-12-21 17:00:36 +00:00
b8b1b4c1de
Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.
...
llvm-svn: 147046
2011-12-21 08:06:52 +00:00
f30188418b
Fix typo in a couple comments
...
llvm-svn: 147045
2011-12-21 06:30:53 +00:00
dc8a1aaea6
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
...
llvm-svn: 147032
2011-12-21 03:04:10 +00:00
7de7ab83fa
ARM assembly parsing allows constant expressions for lane indices.
...
llvm-svn: 147028
2011-12-21 01:19:23 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
...
The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
1d8efaba7e
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
...
case for DCLO and DCLZ.
llvm-svn: 147022
2011-12-21 00:20:27 +00:00
410ce9cb44
Expand 64-bit CTPOP and CTTZ.
...
llvm-svn: 147021
2011-12-21 00:14:05 +00:00
91c052c4d8
Expand 64-bit atomic load and store.
...
llvm-svn: 147019
2011-12-21 00:02:58 +00:00
4706ac9715
Add definition of DSBH (Double Swap Bytes within Halfwords) and
...
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
llvm-svn: 147017
2011-12-20 23:56:43 +00:00
43c1ff4db3
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
...
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
llvm-svn: 147015
2011-12-20 23:47:44 +00:00
79aed157e7
64-bit uint-fp conversion nodes are expanded.
...
llvm-svn: 147014
2011-12-20 23:40:56 +00:00
2bb8d068f5
Enable custom lowering DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 147013
2011-12-20 23:35:46 +00:00
8e2c02e2d6
Set the correct stack pointer register that should be saved or restored.
...
llvm-svn: 147012
2011-12-20 23:28:36 +00:00
cd22e4a81e
ARM .req register name aliases are case insensitive, just like regnames.
...
llvm-svn: 147009
2011-12-20 23:11:00 +00:00
cb2a85bc22
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
...
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
llvm-svn: 147008
2011-12-20 23:10:57 +00:00
2c8d1734f8
Fix indentation.
...
llvm-svn: 147007
2011-12-20 22:58:01 +00:00
cf10f08825
64-bit data directive.
...
llvm-svn: 147005
2011-12-20 22:52:19 +00:00
494fdf1499
32-to-64-bit sext_inreg pattern.
...
llvm-svn: 147004
2011-12-20 22:40:40 +00:00
8756816e6f
Add 64-bit extload patterns.
...
llvm-svn: 147003
2011-12-20 22:36:08 +00:00
0cee2045c9
Add patterns for matching extloads with 64-bit address. The patterns are enabled
...
only when the target ABI is N64.
llvm-svn: 147001
2011-12-20 22:33:53 +00:00
4eda145c7f
Move comment to appropriate place.
...
llvm-svn: 147000
2011-12-20 22:26:38 +00:00
dac1d48d8d
Add code in MipsDAGToDAGISel for selecting constant +0.0.
...
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
llvm-svn: 146999
2011-12-20 22:25:50 +00:00
b95c102c2f
Heed spill slot alignment on ARM.
...
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
llvm-svn: 146997
2011-12-20 22:15:04 +00:00
14468c6cb6
Revert part of r146995 that was accidentally commmitted.
...
llvm-svn: 146996
2011-12-20 22:09:36 +00:00
4e210691c0
32-to-64-bit sign extension pattern.
...
llvm-svn: 146995
2011-12-20 22:06:20 +00:00
9b9bd1cc15
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
...
only when the target ABI is N64.
llvm-svn: 146992
2011-12-20 21:50:49 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
...
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
135d244b56
First steps in ARM AsmParser support for .eabi_attribute and .arch
...
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
ec7e6e0946
This is the second fix related to VZEXT_MOVL node.
...
The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
llvm-svn: 146975
2011-12-20 13:34:28 +00:00
24680c24d8
Begin teaching the X86 target how to efficiently codegen patterns that
...
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
llvm-svn: 146974
2011-12-20 11:19:37 +00:00
e805b16e3d
Fix up the CMake build for the new files added in r146960, they're
...
likely to stay either way that discussion ends up resolving itself.
llvm-svn: 146966
2011-12-20 08:42:11 +00:00
a379b18173
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
...
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
75f12cc3fe
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
...
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
llvm-svn: 146949
2011-12-20 01:29:27 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
94580ab375
Add basic generic CodeGen support for half.
...
llvm-svn: 146927
2011-12-20 00:02:33 +00:00
045b6c71a6
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
...
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
...
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
...
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
64f4de29e0
ARM NEON two-operand aliases for VPADD.
...
rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
2a232d81f6
Remove definitions of double word shift plus 32 instructions. Assembler or
...
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
llvm-svn: 146893
2011-12-19 19:44:09 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
...
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
c4db30e358
Remove unused predicate.
...
llvm-svn: 146889
2011-12-19 19:32:20 +00:00
3c9f336361
Remove the restriction on the first operand of the add node in SelectAddr.
...
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
llvm-svn: 146888
2011-12-19 19:28:37 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
...
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
9ae4fc035b
ARM NEON implied destination aliases for VMAX/VMIN.
...
llvm-svn: 146885
2011-12-19 18:57:38 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
a7d2421603
Tidy up.
...
llvm-svn: 146882
2011-12-19 18:11:17 +00:00
24159e346d
Remove a register class that can just as well be synthesized.
...
Add the new TableGen register class synthesizer feature to the release
notes.
llvm-svn: 146875
2011-12-19 16:53:40 +00:00
c7b437ae34
Emit a getMatchingSuperRegClass() implementation for every target.
...
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
llvm-svn: 146873
2011-12-19 16:53:34 +00:00
1b54835a10
Another variadics tweak.
...
llvm-svn: 146852
2011-12-18 20:51:31 +00:00
530b820500
Use the fancy new VariadicFunction template instead of a plain variadic function.
...
Some compilers were complaining about passing StringRef to it.
llvm-svn: 146850
2011-12-18 19:59:20 +00:00
32481916eb
Hexagon: Remove unused variables.
...
llvm-svn: 146846
2011-12-18 12:00:09 +00:00
a913dde0ef
Remove an unused X86ISD node type.
...
llvm-svn: 146833
2011-12-17 19:16:44 +00:00
792edd3c75
X86: Factor the bswap asm matching to be slightly less horrible to read.
...
llvm-svn: 146831
2011-12-17 14:36:05 +00:00
903231bc58
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
...
llvm-svn: 146805
2011-12-17 01:25:34 +00:00
d3df3d3527
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
...
asm parsing and testcase.
llvm-svn: 146801
2011-12-17 01:14:52 +00:00
da07b3ad42
Make sure that the lower bits on the VSELECT condition are properly set.
...
llvm-svn: 146800
2011-12-17 01:08:46 +00:00
465cdf3ba4
Preserve more memory operands in ARMExpandPseudo.
...
I don't think this affects anything but verbose assembly.
llvm-svn: 146787
2011-12-17 00:07:02 +00:00
9790187b6c
Fix off-by-one error in bucket sort.
...
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
llvm-svn: 146767
2011-12-16 23:00:05 +00:00
5af144809e
Don't adjust for alignment padding in OffsetIsInRange.
...
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.
When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.
llvm-svn: 146751
2011-12-16 19:10:00 +00:00
9ca2e7293b
Hexagon: Fix a nasty order-of-initialization bug.
...
Reenable the tests.
llvm-svn: 146750
2011-12-16 19:08:59 +00:00
2a05f691ab
Note ARM constant island alignment in the release notes.
...
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.
llvm-svn: 146739
2011-12-16 16:07:41 +00:00
a4d411cb1b
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
...
llvm-svn: 146726
2011-12-16 08:06:31 +00:00
93d990bd61
Target/Hexagon: Fix CMake build.
...
llvm-svn: 146724
2011-12-16 06:21:02 +00:00
4a29971f02
ARM NEON aliases for vmovq.f*
...
llvm-svn: 146714
2011-12-16 00:12:22 +00:00
66886253a7
Thumb2 ADR assembly parsing w/o the .w suffix.
...
llvm-svn: 146710
2011-12-15 23:52:17 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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llvm-svn: 146709
2011-12-15 23:46:18 +00:00
c9e935c7e2
Move parts of lib/Target that use CodeGen into lib/CodeGen.
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llvm-svn: 146702
2011-12-15 22:58:58 +00:00
c9bf1b1bff
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
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llvm-svn: 146700
2011-12-15 22:56:53 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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llvm-svn: 146699
2011-12-15 22:56:33 +00:00
b3705e0b9e
Add MCTargetDesc library to Hexagon target
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llvm-svn: 146692
2011-12-15 22:29:08 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
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llvm-svn: 146691
2011-12-15 22:27:11 +00:00
cba8e8c3e0
Enable proper constant island alignment by default.
...
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.
llvm-svn: 146690
2011-12-15 22:14:45 +00:00
41dbf59e12
Add missing zmovl AVX patterns which were causing crashes.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146689
2011-12-15 22:11:31 +00:00
c2f16a3499
Silence warning.
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llvm-svn: 146686
2011-12-15 21:54:55 +00:00
2f50e92f40
ARM NEON two-register double spaced register list parsing support.
...
llvm-svn: 146685
2011-12-15 21:44:33 +00:00
75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
c44b5e469b
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
...
llvm-svn: 146671
2011-12-15 18:57:27 +00:00
9dd3f62b38
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
...
llvm-svn: 146664
2011-12-15 17:54:01 +00:00
275e874c67
Pass optLevel to XCoreDAGToDAGISel.
...
Patch by Kyriakos Georgiou.
llvm-svn: 146656
2011-12-15 15:18:35 +00:00
b7a0b89ff0
Use SmallVector/assign(), rather than std::vector/push_back().
...
llvm-svn: 146627
2011-12-15 01:16:09 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
...
rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
ae94fb4009
The saved registers weren't being processed in the correct order. This lead to
...
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
llvm-svn: 146612
2011-12-14 23:53:24 +00:00
9efd7ebf0a
Consider CPE alignment in CreateNewWater().
...
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
llvm-svn: 146609
2011-12-14 23:48:54 +00:00
da51104282
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
...
Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
8e987f5e25
Nuke old code. Missed in last commit.
...
llvm-svn: 146590
2011-12-14 21:41:32 +00:00
88ac761aa4
ARM NEON refactor VST2 w/ writeback instructions.
...
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
llvm-svn: 146588
2011-12-14 21:32:11 +00:00
b7ec06c5c9
ARM NEON improve factoring a bit. No functional change.
...
llvm-svn: 146585
2011-12-14 20:59:15 +00:00
da103bf9ec
Model ARM predicated write as read-mod-write. e.g.
...
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
llvm-svn: 146583
2011-12-14 20:00:08 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
e5585e8fed
Fix speling and 80-col.
...
llvm-svn: 146575
2011-12-14 18:49:13 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
...
emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
4288b9786f
Fix copy/pasto that skipped the 'modify' step.
...
llvm-svn: 146571
2011-12-14 18:12:37 +00:00
1bb6e066f6
ARM/Thumb2 mov vs. mvn alias goes both ways.
...
llvm-svn: 146570
2011-12-14 17:56:51 +00:00
ded6160473
VFP2 is required for FP loads. Noticed by inspection.
...
llvm-svn: 146569
2011-12-14 17:55:03 +00:00
fce28914ea
Tidy up.
...
llvm-svn: 146568
2011-12-14 17:32:02 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
a26979be29
Fix 80-column violation and extraneous brackets.
...
llvm-svn: 146566
2011-12-14 17:26:05 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
6eb142a616
Thumb2 pre/post indexed stores can be from any non-PC GPR.
...
rdar://10549786
llvm-svn: 146518
2011-12-13 21:10:25 +00:00
5ac89675a0
Thumb2 tweak for ccout handling in RSB parsing.
...
llvm-svn: 146516
2011-12-13 21:06:41 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
...
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
...
llvm-svn: 146507
2011-12-13 20:08:32 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
5e9d16cb53
Expand .cprestore directive to multiple instructions if the offset does not fit
...
in a 16-bit field.
llvm-svn: 146469
2011-12-13 03:09:05 +00:00
637cc6a8aa
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
...
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
llvm-svn: 146466
2011-12-13 01:56:10 +00:00
bfa576fe8e
Account for CPE alignment when searching for new water.
...
Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.
Also take the extra padding into account when the water is above the
use.
llvm-svn: 146458
2011-12-13 00:44:30 +00:00
4ea3c8f54a
Target/Hexagon: Fix CMake build. We don't use add_llvm_library_dependencies().
...
llvm-svn: 146457
2011-12-13 00:36:04 +00:00
8889bb08b8
LLVMBuild: Introduce a common section which currently has a list of the
...
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
llvm-svn: 146436
2011-12-12 22:45:54 +00:00
5d5e0d819d
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
...
-relocation-model=static.
llvm-svn: 146432
2011-12-12 22:39:35 +00:00
faa88c0add
Fix indentation.
...
llvm-svn: 146431
2011-12-12 22:38:19 +00:00
36e0519ca2
fix warning
...
llvm-svn: 146420
2011-12-12 21:52:59 +00:00
fadc2c83e5
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
...
These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
llvm-svn: 146417
2011-12-12 21:45:15 +00:00
1213a7a57f
Hexagon backend support
...
llvm-svn: 146412
2011-12-12 21:14:40 +00:00
27a7489a03
LLVMBuild: Remove trailing newline, which irked me.
...
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
7c0face455
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
91a7bcbb9b
Add a postOffset() alignment argument.
...
This computes the offset of the layout sucessor block, considering its
alignment as well.
llvm-svn: 146401
2011-12-12 19:25:54 +00:00
0863de458d
Fix typo.
...
llvm-svn: 146400
2011-12-12 19:25:51 +00:00
6dd2488383
XOP encoding bits and logic.
...
llvm-svn: 146397
2011-12-12 19:12:26 +00:00
17c27a8898
Also set the proper alignment on inner islands and the function itself.
...
Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.
This is all gated by -arm-align-constant-islands.
llvm-svn: 146391
2011-12-12 18:45:45 +00:00
2a75997858
Make MF a class member instead of passing it around everywhere.
...
Also add an MCP member pointing to the machine constant pool.
No functional change intended.
llvm-svn: 146382
2011-12-12 18:16:53 +00:00
b5f52aad22
Add a -arm-align-constant-islands flag, default off.
...
Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment. When the command line
flag is set, also align the basic block containing the constant pool
entries.
This is only a partial implementation of constant island alignment. More
to come.
llvm-svn: 146375
2011-12-12 16:49:37 +00:00
1fdfec63a4
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
...
llvm-svn: 146344
2011-12-11 19:12:35 +00:00
4683740967
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
...
llvm-svn: 146341
2011-12-11 14:35:48 +00:00
64ba50a972
Mips: Don't create a dangling IR function just to get the address of a symbol.
...
llvm-svn: 146340
2011-12-11 12:21:34 +00:00
a6c59b8fc8
Also remove unnecessary includes from this file, which was supposed to be part
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of r146334!
llvm-svn: 146338
2011-12-11 00:45:13 +00:00
a461c1c069
Minimize #include's and forward-declares in Target.
...
llvm-svn: 146335
2011-12-10 22:35:47 +00:00
b9cda978ab
Refactor the implementation of the TargetOptions out of TargetMachine, taking
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the only parts of TM that depends on CodeGen headers with it.
llvm-svn: 146334
2011-12-10 22:34:41 +00:00
6641294e3b
Revert r146322 to appease buildbots. Original commit message:
...
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
llvm-svn: 146328
2011-12-10 19:55:03 +00:00
df0b779e9f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
...
llvm-svn: 146322
2011-12-10 08:42:24 +00:00
67a7f18faf
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
...
llvm-svn: 146318
2011-12-10 04:50:53 +00:00
146ac7b609
Try to align the point where a large basic block is split.
...
The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.
This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.
<rdar://problem/10550705>
There is still an issue with correctly packing differently aligned
entries in the island.
llvm-svn: 146314
2011-12-10 02:55:10 +00:00
b3734522fa
More debug output formatting.
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llvm-svn: 146313
2011-12-10 02:55:06 +00:00
c7f355b8e1
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
...
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146300
2011-12-10 00:01:02 +00:00
4e36a934dc
Splats can contain undef's; make sure to handle them correctly. PR11526.
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llvm-svn: 146299
2011-12-09 23:54:42 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
ef70e9b704
ARM allows '' syntax, not just '#imm' for assembly.
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Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
ea1b353e67
ARM NEON data type aliases for VBIC(register).
...
llvm-svn: 146281
2011-12-09 21:46:04 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
f85723626c
User a helper overload for a common pattern.
...
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
8a4009dab2
Tidy up. Better base class factoring.
...
llvm-svn: 146267
2011-12-09 19:07:20 +00:00
b076e6f3d5
Tidy up. Better base class factoring.
...
llvm-svn: 146266
2011-12-09 18:54:11 +00:00
5f5fa12413
Tweak debugging output.
...
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
863683c590
This is now implemented.
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llvm-svn: 146258
2011-12-09 15:45:57 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
...
llvm-svn: 146257
2011-12-09 15:44:03 +00:00
2dc5dec41d
X86: Split (v)rounds[sd] into a normal and an intrinsic version.
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llvm-svn: 146256
2011-12-09 15:43:55 +00:00
feb9f27de1
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
...
llvm-svn: 146247
2011-12-09 06:41:08 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
...
llvm-svn: 146246
2011-12-09 06:32:46 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
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llvm-svn: 146201
2011-12-08 22:51:25 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
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llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
bb15fec2b8
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
...
llvm-svn: 146193
2011-12-08 22:15:21 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
...
code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
98bc797b4d
ARM asm parser, just issue a warning for a duplicate reg in a list.
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For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
f10ee84956
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
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MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
llvm-svn: 146183
2011-12-08 21:05:38 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
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llvm-svn: 146182
2011-12-08 20:56:26 +00:00
57a7f41d5d
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
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Fixes failures caused by r146171.
llvm-svn: 146180
2011-12-08 20:51:38 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
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llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
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llvm-svn: 146177
2011-12-08 20:42:35 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
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- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
...
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
4edc7360c7
ARM assembler support for register name aliases.
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rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
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if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
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sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
d19760a40c
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
...
llvm-svn: 146151
2011-12-08 14:43:19 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
528ff4bee0
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
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llvm-svn: 146137
2011-12-08 04:36:44 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
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llvm-svn: 146125
2011-12-08 01:30:04 +00:00
14e024dff7
Drop the HasInlineAsm flag.
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It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
llvm-svn: 146124
2011-12-08 01:22:39 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
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llvm-svn: 146123
2011-12-08 01:12:35 +00:00
bd97f5d753
Simplify offset verification.
...
llvm-svn: 146121
2011-12-08 01:10:05 +00:00
0dd1bc9c79
Fix copy/past-o.
...
llvm-svn: 146120
2011-12-08 01:02:26 +00:00
31a462c02c
ARM NEON two-operand aliases for VMUL.
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llvm-svn: 146119
2011-12-08 00:59:47 +00:00
2a82333f54
Don't include alignment padding in BBInfo.Size.
...
Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
llvm-svn: 146118
2011-12-08 00:55:02 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
...
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
086d013e56
ARM VFP support 'flds/fldd' aliases for 'vldr'
...
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
66232aa19d
Add newline.
...
llvm-svn: 146100
2011-12-07 23:26:03 +00:00
36d2198dae
Add 64-bit HWR29 register.
...
llvm-svn: 146099
2011-12-07 23:23:52 +00:00
9778e7a67c
32 to 64-bit anyext pattern.
...
llvm-svn: 146097
2011-12-07 23:21:19 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
...
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
56b70de01b
Variable cleanup. Based on past patch submittals variable names have
...
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
llvm-svn: 146088
2011-12-07 22:35:30 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
...
llvm-svn: 146086
2011-12-07 22:11:43 +00:00
6820eebde1
Define base class for WrapperPICPat.
...
llvm-svn: 146081
2011-12-07 21:54:54 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4f864b78e6
Fix comment.
...
llvm-svn: 146063
2011-12-07 20:15:01 +00:00
d16e926a6b
Fix comment.
...
llvm-svn: 146062
2011-12-07 20:13:53 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d633c2f120
Nuke inadvertant debugging commit.
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llvm-svn: 146057
2011-12-07 19:56:16 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
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rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
...
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
...
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
1d578e8835
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
...
llvm-svn: 146031
2011-12-07 08:30:53 +00:00
302cf8d5d0
Adjust the stack by one pointer size for all frameless stacks.
...
llvm-svn: 146030
2011-12-07 07:58:55 +00:00
3c86459997
Fix off-by-one error when encoding the stack size for a frameless stack.
...
llvm-svn: 146029
2011-12-07 07:49:49 +00:00
7f8e563a69
Add bundle aware API for querying instruction properties and switch the code
...
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
ac9df3d411
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
...
llvm-svn: 146024
2011-12-07 06:34:06 +00:00
16c744180d
make base register selection used in eliminateFrameIndex 64-bit clean
...
llvm-svn: 146023
2011-12-07 06:34:02 +00:00
abbc2529c1
set mayStore and mayLoad on CR pseudos
...
llvm-svn: 146022
2011-12-07 06:33:57 +00:00
2ba61e47a9
64-bit LR8 load should use X11 not R11
...
llvm-svn: 146021
2011-12-07 06:32:37 +00:00
2f0400b780
Eliminate delta argument from AdjustBBOffsetsAfter.
...
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
llvm-svn: 146018
2011-12-07 05:17:30 +00:00
97c857199e
Compute some alignment information for each basic block.
...
These fields are not used for anything yet.
llvm-svn: 146017
2011-12-07 04:17:35 +00:00
2cf294a213
ARM tidy up and remove no longer needed InstAlias definitions.
...
The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
af748e1180
Move common expression into a method.
...
llvm-svn: 146008
2011-12-07 01:22:52 +00:00
585ce30b8b
ARM Implement ARM ARM Table A7-3 via TokenAlias.
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Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
llvm-svn: 146007
2011-12-07 01:17:58 +00:00
e2b3ff2a07
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
...
No functional change is intended.
llvm-svn: 146005
2011-12-07 01:08:25 +00:00
d4b8249434
ARM: NEON SHLL instruction immediate operand range checking.
...
llvm-svn: 146003
2011-12-07 01:07:24 +00:00
61e6d987bf
Add a few moreLocal/Global R_MIPS_GOT related fixups and
...
make the addend fixup code a bit more generic
Patch by Jack Carter.
llvm-svn: 145998
2011-12-07 00:28:57 +00:00
47c24c2084
ARM: Parameterize the immediate operand type for NEON VSHLL.
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No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
llvm-svn: 145994
2011-12-07 00:02:17 +00:00
cc6bfa8e79
Revert r145971: "Use conservative size estimate for tBR_JTr."
...
This caused more offset errors.
llvm-svn: 145980
2011-12-06 22:41:31 +00:00
67a70c995a
Explicitly check for the different SUB instructions.
...
llvm-svn: 145976
2011-12-06 22:14:27 +00:00
2a81dd4a3c
First chunk of MachineInstr bundle support.
...
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
llvm-svn: 145975
2011-12-06 22:12:01 +00:00
33fe130e12
Use conservative size estimate for tBR_JTr.
...
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
llvm-svn: 145971
2011-12-06 21:55:39 +00:00
2fa7448f31
Remove alignment from deserted constant islands.
...
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
llvm-svn: 145970
2011-12-06 21:55:35 +00:00
5a173cd367
Encode the total stack if there isn't a frame.
...
llvm-svn: 145969
2011-12-06 21:34:01 +00:00
a73c0c99ea
* Add a macro to remove a magic number.
...
* Rename variables to reflect what they're actually used for.
llvm-svn: 145968
2011-12-06 21:23:42 +00:00
bde7f8ffe2
add RESTORE_CR and support CR unspills
...
llvm-svn: 145961
2011-12-06 20:55:36 +00:00
4ec02b02ac
remove old FIXME
...
llvm-svn: 145960
2011-12-06 20:52:56 +00:00
87571b6392
Check the correct value for small stack sizes. Also modify some comments.
...
llvm-svn: 145954
2011-12-06 19:16:17 +00:00
a4e87944a8
For a small sized stack, we encode that value directly with no "stack adjust" value.
...
llvm-svn: 145952
2011-12-06 19:09:06 +00:00
04424665c3
PTX: Continue to fix up the register mess.
...
llvm-svn: 145947
2011-12-06 17:39:48 +00:00
3063ac87aa
PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols
...
llvm-svn: 145946
2011-12-06 17:39:46 +00:00
83320e03e6
Add X86ISD::HADD/HSUB to getTargetNodeName
...
llvm-svn: 145929
2011-12-06 09:31:36 +00:00
6572e0f203
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
...
llvm-svn: 145927
2011-12-06 09:04:59 +00:00
8d4ba198d6
Merge floating point and integer UNPCK X86ISD node types.
...
llvm-svn: 145926
2011-12-06 08:21:25 +00:00
3cb802c775
Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.
...
llvm-svn: 145924
2011-12-06 05:31:16 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
bf41eb3a98
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
...
llvm-svn: 145921
2011-12-06 04:59:07 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
0c24d8a406
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
...
llvm-svn: 145912
2011-12-06 03:34:48 +00:00
1b1a122b4c
Add register HWR29 numbering. Patch by Jack Carter
...
llvm-svn: 145910
2011-12-06 03:34:36 +00:00
4e87e850a2
Add a comment.
...
llvm-svn: 145896
2011-12-06 01:57:48 +00:00
425e180ce8
Tidy up value checking.
...
llvm-svn: 145895
2011-12-06 01:53:17 +00:00
d3002490bf
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
...
llvm-svn: 145894
2011-12-06 01:48:32 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
2e05db2fa0
Align ARM constant pool islands via their basic block.
...
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
10e1252269
Use logarithmic units for basic block alignment.
...
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.
CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.
Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.
Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.
llvm-svn: 145889
2011-12-06 01:26:19 +00:00
f7cef7ecad
The compact encoding of the registers are 3-bits each. Make sure we shift the
...
value over that much.
llvm-svn: 145888
2011-12-06 01:26:14 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
...
rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
2608157f79
Use an existing function.
...
llvm-svn: 145883
2011-12-06 00:51:12 +00:00
25b63fa117
Move target-specific logic out of generic MCAssembler.
...
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
llvm-svn: 145881
2011-12-06 00:47:03 +00:00
34a7c6dfd7
Simple branch relaxation for Thumb2 Bcc instructions.
...
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
llvm-svn: 145871
2011-12-05 23:45:46 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
...
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
e489babf9b
Thumb2 prefer ADD register encoding T2 to T3 when possible.
...
rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
...
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
...
them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
...
O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
...
Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
9e90c5cde3
Fix previous commit. Oops.
...
llvm-svn: 145844
2011-12-05 20:12:26 +00:00
2b37e4fc80
Tidy up. No functional change.
...
llvm-svn: 145843
2011-12-05 20:09:44 +00:00
0a978ef715
ARM assmebler parsing for two-operand VMUL instructions.
...
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
...
llvm-svn: 145819
2011-12-05 17:55:17 +00:00
72a26e8b8d
don't include CR bit subregs in callee-saved list
...
llvm-svn: 145818
2011-12-05 17:55:12 +00:00
b544019a60
add register pressure for CR regs
...
llvm-svn: 145816
2011-12-05 17:54:17 +00:00
51bec1a37a
Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions.
...
llvm-svn: 145804
2011-12-05 07:27:14 +00:00
6a55b1dd9f
Clean up and optimizations to the X86 shuffle lowering code. No functional change.
...
llvm-svn: 145803
2011-12-05 06:56:46 +00:00
80381f6cbf
Fix 80-column issues.
...
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
...
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
...
AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
006e43bcc0
Check for stack space more intelligently.
...
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
165ca1d4ba
Fix a bug in the x86-32 code generated for segmented stacks.
...
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
llvm-svn: 145765
2011-12-03 09:21:07 +00:00
8fd1254a0a
Creating multiple JITs on X86 in multiple threads causes multiple writes (of
...
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.
llvm-svn: 145745
2011-12-03 02:45:50 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
...
llvm-svn: 145726
2011-12-02 23:34:39 +00:00
2635f54cb6
ARM VEXT tighten up operand classes a bit.
...
llvm-svn: 145722
2011-12-02 22:57:57 +00:00
eb53822f5a
ARM VST1 single lane assembly parsing.
...
llvm-svn: 145718
2011-12-02 22:34:51 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
dda976b804
ARM VLD1 single lane assembly parsing.
...
llvm-svn: 145712
2011-12-02 22:01:52 +00:00
81c9003695
ARM encoder method needs the physical register number, not the enum.
...
llvm-svn: 145711
2011-12-02 22:01:25 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
1280eb1d06
Add XOP feature flag.
...
llvm-svn: 145682
2011-12-02 15:14:37 +00:00
b67440367f
Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions
...
llvm-svn: 145681
2011-12-02 08:18:41 +00:00
abeb79eee3
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
...
llvm-svn: 145680
2011-12-02 07:16:01 +00:00
f9ce7b60ef
remove unneeded FIXME comment
...
llvm-svn: 145679
2011-12-02 04:58:17 +00:00
58ca360081
update PPC 940 hazard rec. to function in postRA mode
...
llvm-svn: 145676
2011-12-02 04:58:02 +00:00
04945c42c6
ARM start parsing VLD1 single lane instructions.
...
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
f60485c4cf
Dummy commit to check commit access.
...
llvm-svn: 145619
2011-12-01 19:15:08 +00:00
676c093758
Add missing functions.
...
llvm-svn: 145608
2011-12-01 18:26:19 +00:00
10fe1fe39e
Add a few more functions to TargetLibraryInfo. More of rdar://10500969.
...
llvm-svn: 145596
2011-12-01 17:54:37 +00:00
9da7f305a4
For 64-bit the rest of the general regs are ok for the q constraint. Make
...
sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
2011-12-01 08:12:41 +00:00
d61887dd0a
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
...
llvm-svn: 145573
2011-12-01 04:49:21 +00:00
c1870b2633
Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
...
llvm-svn: 145553
2011-12-01 01:43:47 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
...
remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
23c30b90e3
Remove unused variable
...
llvm-svn: 145517
2011-11-30 19:53:11 +00:00
a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
...
llvm-svn: 145510
2011-11-30 19:35:44 +00:00
738da252ab
Add a few functions to TargetLibraryInfo.
...
llvm-svn: 145508
2011-11-30 19:19:00 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
...
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
5feb3dab79
X86: Turns out bulldozer also supports sse42 and lzcnt.
...
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.
llvm-svn: 145494
2011-11-30 15:48:16 +00:00
981f32327d
X86: Add subtargets for AMD's bulldozer.
...
llvm-svn: 145493
2011-11-30 15:27:46 +00:00
96923cc2bb
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
...
llvm-svn: 145488
2011-11-30 10:13:37 +00:00
c4977ba413
Add instruction selection support for AVX2 horizontal add/sub instructions.
...
llvm-svn: 145487
2011-11-30 09:10:50 +00:00
0a672eaf9e
Merge VPERM2F128/VPERM2I128 ISD node types.
...
llvm-svn: 145485
2011-11-30 07:47:51 +00:00
bafd224c8b
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
...
llvm-svn: 145483
2011-11-30 06:25:25 +00:00
abba0947db
Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional
...
change intended.
llvm-svn: 145468
2011-11-30 01:51:49 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
...
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
82e1bd8e94
Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
...
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410
llvm-svn: 145460
2011-11-29 23:57:10 +00:00
182b6a077e
Tidy up a bit.
...
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
ae672f8118
Add comment.
...
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
e1154eef0b
ARM parsing aliases for data-size suffices on VST1.
...
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
dc25f9f38a
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
...
tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
llvm-svn: 145451
2011-11-29 23:08:41 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
648e48d02e
Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.
...
llvm-svn: 145448
2011-11-29 22:48:34 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
...
llvm-svn: 145442
2011-11-29 22:38:04 +00:00
bde32d36bb
Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
...
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.
This also makes the AVX variants redundant.
llvm-svn: 145440
2011-11-29 22:27:25 +00:00
312b97c267
comment.
...
llvm-svn: 145422
2011-11-29 19:33:49 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
...
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
de3a2118db
MC/X86/COFF: Allow quotes in names when targeting MS/Windows,
...
as MC is the only assembler we support.
This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.
llvm-svn: 145409
2011-11-29 18:00:06 +00:00
7a81dea516
Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.
...
Added a test.
Thanks Bruno for reviewing the patch.
llvm-svn: 145403
2011-11-29 15:00:45 +00:00
1d63ae3731
Fix shuffle decoding for memory forms for (V)SHUFPS/D.
...
llvm-svn: 145392
2011-11-29 07:58:09 +00:00
c16db840be
Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD.
...
llvm-svn: 145390
2011-11-29 07:49:05 +00:00
12b72def4e
Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled.
...
llvm-svn: 145376
2011-11-29 05:37:58 +00:00
897a7d4b9c
Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2.
...
llvm-svn: 145370
2011-11-29 03:57:34 +00:00
ae9132207f
Better fix for ARM MOVT relocation encoding of thumb bit.
...
Replaces r145318 with a more targetted fix for the relocation handling.
llvm-svn: 145346
2011-11-29 01:15:25 +00:00
aa93ceb164
Add missing avx pattern.
...
llvm-svn: 145272
2011-11-28 20:27:23 +00:00
12330650f8
Silence wrong warnings from GCC about variables possibly being used
...
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
llvm-svn: 145239
2011-11-28 10:31:27 +00:00
818a983e93
Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar.
...
llvm-svn: 145238
2011-11-28 10:14:51 +00:00
b0456936da
Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled.
...
llvm-svn: 145218
2011-11-28 01:14:24 +00:00
79ee88a511
Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the code was similar for both.
...
llvm-svn: 145199
2011-11-27 21:41:12 +00:00
97b3da5433
Add several new instructions supported by the latest MicroBlaze.
...
These instructions are not generated by the backend yet, this will come in a later commit.
llvm-svn: 145161
2011-11-27 05:16:58 +00:00
d2e2e1782f
Optimize comparison against 0 in conditional instructions.
...
Fix a couple of 80-column violations.
llvm-svn: 145159
2011-11-27 01:36:20 +00:00
7ba71be392
Move code into anonymous namespaces.
...
llvm-svn: 145154
2011-11-26 23:01:57 +00:00
51280d565b
Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created.
...
llvm-svn: 145153
2011-11-26 22:55:48 +00:00
69d5040485
Rename a couple of options and fix some simple typos.
...
llvm-svn: 145152
2011-11-26 21:50:38 +00:00
7704bd7ac3
Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type.
...
llvm-svn: 145148
2011-11-26 20:47:44 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
...
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
989eaf6e3f
ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
...
llvm-svn: 145129
2011-11-25 09:19:57 +00:00
d65a444478
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
...
llvm-svn: 145126
2011-11-24 22:57:10 +00:00
d26466748b
Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish.
...
llvm-svn: 145125
2011-11-24 22:20:08 +00:00
651db37352
X86: alias cqo to cqto.
...
llvm-svn: 145121
2011-11-24 12:02:46 +00:00
049e9e4d22
This patch makes the following changes necessary for MIPS' direct code emission.
...
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).
llvm-svn: 145113
2011-11-23 22:19:28 +00:00
f5ddf13f79
This patch addresses gp relative fixups/relocations for jump tables.
...
llvm-svn: 145112
2011-11-23 22:18:04 +00:00
ebcb451874
X86: Use btq for bit tests if the immediate can't be encoded in 32 bits.
...
Before:
movabsq $4294967296, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
testq %rax, %rdi ## encoding: [0x48,0x85,0xf8]
jne LBB0_2 ## encoding: [0x75,A]
After:
btq $32, %rdi ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
jb LBB0_2 ## encoding: [0x72,A]
btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.
llvm-svn: 145103
2011-11-23 13:54:17 +00:00
779ba6d7b7
I added several lines in X86 code generator that allow to choose
...
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.
The patch was reviewed by Bruno.
llvm-svn: 145099
2011-11-23 10:23:16 +00:00
02845410f9
Fix PR11422.
...
This was a bug in keeping track of the available domains when merging
domain values.
The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.
Also add an assertion to catch future attempts at emitting AVX2
instructions.
llvm-svn: 145096
2011-11-23 04:03:08 +00:00
6f0ae783fe
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
...
llvm-svn: 145065
2011-11-22 16:21:04 +00:00
83c4592619
More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries.
...
llvm-svn: 145063
2011-11-22 14:27:57 +00:00
ccb7097509
Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms.
...
llvm-svn: 145055
2011-11-22 01:57:35 +00:00
f563977795
Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX.
...
llvm-svn: 145053
2011-11-22 00:44:41 +00:00
6270d072c5
Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.
...
llvm-svn: 145028
2011-11-21 08:26:50 +00:00
669199ca94
Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled.
...
llvm-svn: 145026
2011-11-21 06:57:39 +00:00
a065238c6e
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.
...
llvm-svn: 145022
2011-11-21 01:12:36 +00:00
e79761df73
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
...
llvm-svn: 145005
2011-11-20 00:12:05 +00:00
a3a6583694
Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
...
llvm-svn: 145004
2011-11-19 22:34:59 +00:00
bac86038ac
Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns.
...
llvm-svn: 145003
2011-11-19 21:01:54 +00:00
3af6ae089f
Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
...
llvm-svn: 144999
2011-11-19 17:46:46 +00:00
f984efbfce
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
...
llvm-svn: 144989
2011-11-19 09:02:40 +00:00
81390be00f
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
...
llvm-svn: 144988
2011-11-19 07:33:10 +00:00
de6b73bb4d
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
...
llvm-svn: 144987
2011-11-19 07:07:26 +00:00
66e2b5a61e
Remove unused parameters from the AVX maskmov classes.
...
llvm-svn: 144985
2011-11-19 04:49:22 +00:00
1ec141d0f9
Add AVX2 vpbroadcast support
...
llvm-svn: 144967
2011-11-18 02:49:55 +00:00
ee93ff736a
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
...
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
0eff3e5c21
Add TODO comment.
...
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
f41e1d0246
Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.
...
llvm-svn: 144896
2011-11-17 07:49:38 +00:00
15b2498e88
Dead code.
...
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
f17b600577
Remove seemingly unnecessary duplicate VROUND definitions.
...
llvm-svn: 144885
2011-11-17 07:04:00 +00:00
489c0ff4a4
Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
...
names for fwrite and fputs.
Fixes <rdar://problem/9815881>.
llvm-svn: 144876
2011-11-17 01:27:36 +00:00
ce619ddfc5
Don't unconditionally set the kill flag.
...
rdar://10456186
llvm-svn: 144872
2011-11-17 01:16:53 +00:00
20439a42b0
Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
...
llvm-svn: 144867
2011-11-17 00:21:52 +00:00
d3f02cbce9
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
b31abde0f3
Lower 64-bit constant pool node.
...
llvm-svn: 144849
2011-11-16 22:44:38 +00:00
eb42071721
Lower 64-bit block address.
...
llvm-svn: 144847
2011-11-16 22:42:10 +00:00
7ccdb7c0ae
Fix encoding of NOP used for padding in ARM mode .align.
...
llvm-svn: 144842
2011-11-16 22:40:25 +00:00
7b8547c4d0
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
...
nodes.
llvm-svn: 144841
2011-11-16 22:39:56 +00:00
6d617ceca2
64-bit jump register instruction.
...
llvm-svn: 144840
2011-11-16 22:36:01 +00:00
011538dc79
Another missing X86ISD::MOVLPD pattern. rdar://10450317
...
llvm-svn: 144839
2011-11-16 22:24:44 +00:00
bfe5c5c968
ARM assembly parsing for shifted register operands for MOV instruction.
...
llvm-svn: 144837
2011-11-16 21:50:05 +00:00
01e0439240
Clean up debug printing of ARM shifted operands.
...
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
3127ab6d8f
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
...
llvm-svn: 144814
2011-11-16 19:12:24 +00:00
1a2f9ee3c8
ARM assembly parsing for RRX mnemonic.
...
rdar://9704684
llvm-svn: 144812
2011-11-16 19:05:59 +00:00
48784ed5b7
Added missing comment about new custom lowering of DEC64
...
llvm-svn: 144811
2011-11-16 19:03:23 +00:00
80979b6ea6
Check to make sure we can select the instruction before trying to put the
...
operands into a register. Otherwise, we may materialize dead code.
llvm-svn: 144805
2011-11-16 18:39:44 +00:00
abcac56869
ARM mode aliases for bitwise instructions w/ register operands.
...
rdar://9704684
llvm-svn: 144803
2011-11-16 18:31:45 +00:00
0ca7ce389c
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
...
llvm-svn: 144798
2011-11-16 17:09:59 +00:00
b345060a85
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
...
llvm-svn: 144794
2011-11-16 09:18:28 +00:00
ecb2908bf9
Sink codegen optimization level into MCCodeGenInfo along side relocation model
...
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
2011-11-16 08:38:26 +00:00
3ed7d9ee5a
Fix the execution domain on a bunch of SSE/AVX instructions.
...
llvm-svn: 144784
2011-11-16 07:30:46 +00:00
f6d1728d8f
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
...
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
llvm-svn: 144781
2011-11-16 07:11:57 +00:00
07d8b5e2c9
Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.
...
llvm-svn: 144777
2011-11-16 05:02:04 +00:00
af13d767a2
Add FIXME comment.
...
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
653183fd5c
Enable -widen-vmovs by default.
...
This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
llvm-svn: 144734
2011-11-15 23:53:18 +00:00
e891fe8d6c
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
003cea6011
ARM assembly parsing for data type suffices on NEON VMOV aliases.
...
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
37010002f2
AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
...
llvm-svn: 144720
2011-11-15 22:50:37 +00:00
75fb4abcdc
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
a01033709f
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
...
llvm-svn: 144710
2011-11-15 22:15:10 +00:00
8279c1828f
ARM accept an immediate offset in memory operands w/o the '#'.
...
llvm-svn: 144709
2011-11-15 22:14:41 +00:00
7c7ba1baa1
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
...
by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
llvm-svn: 144705
2011-11-15 21:57:53 +00:00
8d579230c6
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
...
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
llvm-svn: 144701
2011-11-15 21:45:55 +00:00
84f0ba5747
ARM size suffix on VFP single-precision 'vmov' is optional.
...
rdar://10435114
llvm-svn: 144698
2011-11-15 21:18:35 +00:00
a92a5d8548
Fix typo.
...
llvm-svn: 144695
2011-11-15 21:01:30 +00:00
131b45e632
ARM alternate size suffices for VTRN instructions.
...
rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
05060f0748
Fix a misplaced paren bug.
...
llvm-svn: 144692
2011-11-15 20:30:41 +00:00
5803f6d5a2
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
c5b1bc561e
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
72dfd20aba
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
efa7e95d06
Thumb2 two-operand 'mul' instruction wide encoding parsing.
...
rdar://10449724
llvm-svn: 144684
2011-11-15 19:55:16 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
...
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
6efa7b9852
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
6ee8fc88c7
Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
...
registers and instructions when ABI is N64.
llvm-svn: 144666
2011-11-15 18:53:55 +00:00
494913270e
Set nomacro before emitting the sequence of instructions that set global pointer
...
register.
llvm-svn: 144665
2011-11-15 18:44:44 +00:00
66a14c0650
Simplify function PassByValArg64.
...
llvm-svn: 144664
2011-11-15 18:42:25 +00:00
b7796ae938
Delete files.
...
llvm-svn: 144655
2011-11-15 18:22:48 +00:00
1c0590c5da
Remove MipsMCSymbolRefExpr.
...
llvm-svn: 144654
2011-11-15 18:20:08 +00:00
2aabaa704a
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144650
2011-11-15 17:49:59 +00:00
e5cbd3c3fb
Fix typo in comment.
...
llvm-svn: 144633
2011-11-15 07:50:05 +00:00
465101bb0e
Make use of MachinePointerInfo::getFixedStack. This removes all mention
...
of PseudoSourceValue from lib/Target/.
llvm-svn: 144632
2011-11-15 07:34:52 +00:00
0745e645e0
Remove some unnecessary includes of PseudoSourceValue.h.
...
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
649d1c5eec
Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.
...
llvm-svn: 144629
2011-11-15 06:39:01 +00:00
05baa85f58
Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.
...
llvm-svn: 144622
2011-11-15 05:55:35 +00:00
7ca4b6eb5c
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
...
integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
29cdcda80d
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144606
2011-11-15 01:46:57 +00:00
f8ad336bc4
Break false dependencies before partial register updates.
...
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.
The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.
The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.
llvm-svn: 144602
2011-11-15 01:15:30 +00:00
a498af2b1d
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
72838a0345
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
750de7a399
Add explanatory comment.
...
llvm-svn: 144589
2011-11-14 23:21:09 +00:00
9c2d9d597b
Split out the plain '.{8|16|32|64}' suffix handling.
...
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
llvm-svn: 144588
2011-11-14 23:20:14 +00:00
3d6c0e0bb2
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
...
rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
057b6d3476
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
...
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
llvm-svn: 144585
2011-11-14 23:04:09 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
ab7223e99a
Add support for inlining small memcpys.
...
rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
45110fdf8d
Fix a performance regression from r144565. Positive offsets were being lowered
...
into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
7996b15724
ARM assembly parsing type suffix options for VLDR/VSTR.
...
rdar://10435076
llvm-svn: 144575
2011-11-14 22:28:39 +00:00
fb13d32b3f
Add a missing pattern for X86ISD::MOVLPD. rdar://10436044
...
llvm-svn: 144566
2011-11-14 20:35:52 +00:00
adfd200bcb
Add support for Thumb load/stores with negative offsets.
...
rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
319904cc7e
Unbreak Release builds.
...
llvm-svn: 144560
2011-11-14 19:51:48 +00:00
890e02e854
Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered
...
Constant idx case is still done in tablegen but other cases are then expanded
Fixes <rdar://problem/10435460>
llvm-svn: 144557
2011-11-14 19:38:42 +00:00
f93b3f46f8
32-to-64-bit extended load.
...
llvm-svn: 144554
2011-11-14 19:06:14 +00:00
0b8bc00424
AnalyzeCallOperands function for N32/64.
...
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.
llvm-svn: 144553
2011-11-14 19:02:54 +00:00
52359363f2
Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.
...
llvm-svn: 144552
2011-11-14 19:01:09 +00:00
33a519021c
PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations.
...
llvm-svn: 144551
2011-11-14 18:58:20 +00:00
d673cfe027
Remove variable that keeps the size of area used to save byval or variable
...
argument registers on the callee's stack frame, along with functions that set
and get it.
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.
llvm-svn: 144549
2011-11-14 18:56:20 +00:00
ee201faeac
Tidy up. 80 column.
...
llvm-svn: 144538
2011-11-14 17:52:47 +00:00
182b00a2e0
Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions.
...
llvm-svn: 144525
2011-11-14 08:07:55 +00:00
a331515c82
Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway.
...
llvm-svn: 144522
2011-11-14 06:46:21 +00:00
2a1df883d0
Add support for ARM halfword load/stores and signed byte loads with negative
...
offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
b8bcb473e2
Add BLSI, BLSMSK, and BLSR to getTargetNodeName.
...
llvm-svn: 144502
2011-11-13 17:31:07 +00:00
1198d894d0
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
...
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
a476e391f1
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
...
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
5196efdf36
Fix comments.
...
llvm-svn: 144490
2011-11-13 04:25:02 +00:00
c8cfd3a8fb
Add support for emitting both signed- and zero-extend loads. Fix
...
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
3dc75f9e3b
Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
...
llvm-svn: 144457
2011-11-12 09:58:49 +00:00
77733535eb
Fix typo.
...
llvm-svn: 144453
2011-11-12 02:38:12 +00:00
19891f843c
Implement Mips64's handling of byval arguments in LowerCall.
...
llvm-svn: 144452
2011-11-12 02:34:50 +00:00
fb9bae34da
Implement Mips64's handling of byval arguments in LowerFormalArguments.
...
llvm-svn: 144449
2011-11-12 02:29:58 +00:00
5ed07c03f4
64-bit arbitrary immediate pattern.
...
llvm-svn: 144448
2011-11-12 02:25:00 +00:00
202f6400ef
Function for handling byval arguments.
...
llvm-svn: 144447
2011-11-12 02:20:46 +00:00
52823cc91c
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
...
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
3a3d8e82bc
ARM refactor simple immediate asm operand render methods.
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These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
llvm-svn: 144439
2011-11-12 00:58:43 +00:00
8ca13deecf
Re-apply 144430, this time with the associated isel and disassmbler bits.
...
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
155763b630
Oops. Missed the isel half of this. revert while I sort that out.
...
llvm-svn: 144431
2011-11-11 23:51:31 +00:00
28f721a2b4
ARM assembly parsing for VST1 two-register encoding.
...
llvm-svn: 144430
2011-11-11 23:45:47 +00:00
609d113874
ARM optional size suffix for VLDR/VSTR syntax.
...
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
a7ebc5617d
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
...
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
7f89f4c91c
CMake: Fix CMake build for new Mips tblgen file.
...
llvm-svn: 144423
2011-11-11 23:12:56 +00:00
12952fef71
ARM vldm and vstm VFP instructions can take a data type suffix.
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It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
llvm-svn: 144422
2011-11-11 23:08:10 +00:00
b8a9c43d07
Target/LLVMBuild: Order components alphabetically.
...
llvm-svn: 144415
2011-11-11 22:59:16 +00:00
c85e3ff334
Mips MC object code emission improvements:
...
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
b68eeb3852
Nuke no longer accurate comment.
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llvm-svn: 144411
2011-11-11 22:30:06 +00:00
28c1d18434
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
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Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
85a2343b01
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
089cc53232
allow non-device function calls in PTX when natively handling device-side printf
...
llvm-svn: 144388
2011-11-11 14:45:12 +00:00
80cd65bfa9
add rules in tabgen for PTX COPY_ADDRESS of frameindex
...
llvm-svn: 144387
2011-11-11 14:45:06 +00:00
48b5bbffed
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
...
llvm-svn: 144384
2011-11-11 12:39:41 +00:00
1cc805c058
Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler.
...
llvm-svn: 144383
2011-11-11 12:39:35 +00:00
ea28a34c43
Add lowering for AVX2 shift instructions.
...
llvm-svn: 144380
2011-11-11 07:39:23 +00:00
e19b0a9eb8
Rename variables to avoid confusion. No functionallity change intended.
...
llvm-svn: 144377
2011-11-11 06:27:41 +00:00
7ddd63ce4e
Add support for using immediates with select instructions.
...
rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
4a63d1c0f0
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
...
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
llvm-svn: 144373
2011-11-11 04:18:21 +00:00
21cbc25bbb
64-bit atomic instructions.
...
llvm-svn: 144372
2011-11-11 04:14:30 +00:00
9189d7127f
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
...
llvm-svn: 144371
2011-11-11 04:11:56 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
...
llvm-svn: 144370
2011-11-11 04:06:38 +00:00
0009dc2088
64-bit versions of jal, jalr and bal.
...
llvm-svn: 144368
2011-11-11 04:03:54 +00:00
11521863da
Emit Mips64's sequence of instructions that set global register in prologue.
...
llvm-svn: 144367
2011-11-11 04:00:29 +00:00
aa1f4c7986
Fix printing of MCSymbolRegExpr. Needs three closing parentheses for
...
VK_Mips_GPOFF_HI/LO.
llvm-svn: 144366
2011-11-11 03:58:36 +00:00
c4a001478c
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
...
llvm-svn: 144361
2011-11-11 03:16:38 +00:00
023ede5649
When loading a value, treat an i1 as an i8.
...
llvm-svn: 144356
2011-11-11 02:38:59 +00:00
8df8204554
If we have to reset the calculation of the compact encoding, then also reset the
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"saved register" index.
<rdar://problem/10430076>
llvm-svn: 144350
2011-11-11 00:59:14 +00:00
2a3503e061
Add support for using MVN to materialize negative constants.
...
rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
6d617b48c7
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
...
llvm-svn: 144344
2011-11-11 00:23:56 +00:00
d9a9be269c
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
...
rdar://10429490
llvm-svn: 144338
2011-11-10 23:58:34 +00:00
afad053141
ARM let processInstruction() tranforms chain.
...
llvm-svn: 144337
2011-11-10 23:42:14 +00:00
9bded9dc24
Thumb2 parsing for push/pop w/ hi registers in the reglist.
...
rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
a113eb0205
Thumb1 diagnostics for reglist on PUSH/POP fix.
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Was not checking the first register in the register list.
llvm-svn: 144329
2011-11-10 23:01:27 +00:00
5a5ce63742
Thumb MUL assembly parsing for 3-operand form.
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Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
085f6f2af1
build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler
...
that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.
llvm-svn: 144321
2011-11-10 22:00:37 +00:00
d1762e00e2
When in ARM mode, LDRH/STRH require special handling of negative offsets.
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For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
42ba6286b6
ARM .thumb_func directive for quoted symbol names.
...
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
llvm-svn: 144315
2011-11-10 20:48:53 +00:00
c14871cc67
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
61db5a59f7
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
b538095011
build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for
...
consistency with other targets.
llvm-svn: 144292
2011-11-10 15:35:14 +00:00
0a2f797dec
AVX2: Add variable shift from memory.
...
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.
llvm-svn: 144266
2011-11-10 06:54:20 +00:00
3fbd094ad9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
807c6e4e5f
build/Make & CMake: Pass the appropriate --native-target and --enable-targets
...
options to llvm-build, so the all-targets etc. components are defined properly.
llvm-svn: 144255
2011-11-10 01:16:48 +00:00
233c9304a8
llvm-build: Add --native-target and --enable-targets options, and add logic to
...
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
1c04e14447
llvm-build: Change CBackend and CppBackend to not use library_name. This will
...
change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).
llvm-svn: 144251
2011-11-10 00:49:55 +00:00
82219ad4dc
llvm-build: Add an explicit component type to represent targets.
...
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
a48485a37f
Tidy up.
...
llvm-svn: 144244
2011-11-10 00:02:33 +00:00
25bc090170
Thumb2 assembly parsing STMDB w/ optional .w suffix.
...
rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
2d4055b683
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
...
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
2f27fab6ed
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
...
rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
1938482bfa
AVX2: Add patterns for variable shift operations
...
llvm-svn: 144212
2011-11-09 21:22:13 +00:00
2f70bcdb94
Remove unnecessary include.
...
llvm-svn: 144211
2011-11-09 21:11:02 +00:00
79135d844d
Add AVX2 support for vselect of v32i8
...
llvm-svn: 144187
2011-11-09 13:21:28 +00:00
f87a2bef51
Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions.
...
llvm-svn: 144179
2011-11-09 09:37:21 +00:00
c9eb09d3b8
Add instruction selection for AVX2 integer comparisons.
...
llvm-svn: 144176
2011-11-09 08:06:13 +00:00
8c8a431057
Add AVX2 instruction lowering for add, sub, and mul.
...
llvm-svn: 144174
2011-11-09 07:28:55 +00:00
595d419427
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
94307f6ba6
Hide cpu name checking in ARMSubtarget.
...
llvm-svn: 144154
2011-11-09 01:57:03 +00:00
d5edb3847a
Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts.
...
Patch by Jack Carter.
llvm-svn: 144139
2011-11-08 22:26:47 +00:00
c3770ac687
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
...
llvm-svn: 144123
2011-11-08 21:21:09 +00:00
0439cfc41f
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
...
No functional change intended.
llvm-svn: 144122
2011-11-08 21:12:00 +00:00
b85fcd07df
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
...
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
llvm-svn: 144102
2011-11-08 18:56:23 +00:00
82cd9e81fc
Added invariant field to the DAG.getLoad method and changed all calls.
...
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
71133fe9c6
This patch handles unaligned loads and stores in Mips JIT. Mips backend
...
implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).
Patch by Petar Jovanovic and Sasa Stankovic.
llvm-svn: 144081
2011-11-08 12:47:11 +00:00
05aa1a42c3
PPCInstrInfo.cpp: Fix one "unused" warning.
...
llvm-svn: 144071
2011-11-08 04:00:07 +00:00
6f84fed675
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
...
llvm-svn: 144057
2011-11-08 01:43:53 +00:00
91b56e0390
Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222
...
llvm-svn: 144052
2011-11-08 00:31:58 +00:00
5de1bea5c9
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
...
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
fa75530ff0
Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well.
...
llvm-svn: 144021
2011-11-07 21:43:40 +00:00
2216f73676
Various Mips64 floating point instruction patterns.
...
llvm-svn: 144019
2011-11-07 21:38:58 +00:00
b2d37760a2
Add definition of the base class for floating point comparison instructions
...
and add Mips64's version too.
llvm-svn: 144018
2011-11-07 21:37:33 +00:00
81c14002dc
Add code needed for copying between 64-bit integer and floating pointer
...
registers.
llvm-svn: 144017
2011-11-07 21:35:45 +00:00
1537e297e1
Add definitions of 64-bit instructions which move data between integer and
...
floating pointer registers.
llvm-svn: 144016
2011-11-07 21:32:58 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
...
As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
03d73e47b4
Simplify code. No functionality change.
...
llvm-svn: 144012
2011-11-07 21:00:43 +00:00
0241308954
Expand V_SET0 to xorps by default.
...
The xorps instruction is smaller than pxor, so prefer that encoding.
The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.
llvm-svn: 143996
2011-11-07 19:15:58 +00:00
2b8d1f163f
Add definition of 64-bit load upper immediate.
...
llvm-svn: 143994
2011-11-07 19:10:49 +00:00
2f4480046b
Include RegSaveAreaSize in the computation of stack size.
...
llvm-svn: 143993
2011-11-07 19:07:35 +00:00
7bcecd486f
Define functions that get or set the size of area on callee's stack frame which
...
is used to save va_arg or byval arguments passed in registers.
llvm-svn: 143992
2011-11-07 19:06:10 +00:00
d9c2e46cfb
Use array_lengthof to compute the number of iterations of a loop.
...
llvm-svn: 143991
2011-11-07 19:03:40 +00:00
cf7e5b0976
Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted
...
when shift amount is larger than 32.
llvm-svn: 143990
2011-11-07 19:01:49 +00:00
770f0646db
Make the type of shift amount i32 in order to reduce the number of shift
...
instruction definitions.
llvm-svn: 143989
2011-11-07 18:59:49 +00:00
d5c1329078
Add 64-bit to 32-bit trunc pattern.
...
llvm-svn: 143988
2011-11-07 18:57:41 +00:00
a6d409d543
Add AVX2 variable shift instructions and intrinsics.
...
llvm-svn: 143915
2011-11-07 08:26:24 +00:00
ff39be0afc
Add AVX2 VPMOVMASK instructions and intrinsics.
...
llvm-svn: 143904
2011-11-07 03:20:35 +00:00
e122dcbf4a
Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects.
...
llvm-svn: 143902
2011-11-07 02:00:04 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
...
llvm-svn: 143895
2011-11-06 23:04:08 +00:00
20baffb257
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
...
llvm-svn: 143891
2011-11-06 20:37:06 +00:00
05d1cb98e7
Add more AVX2 instructions and intrinsics.
...
llvm-svn: 143861
2011-11-06 06:12:20 +00:00
d0191a53c9
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
...
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
f3da529028
Add more PRI.64 macros for MSVC and use them throughout the codebase.
...
llvm-svn: 143799
2011-11-05 08:57:40 +00:00
f0055f61fb
Allow i1 to be promoted to i32 for ARM APCS calling convention.
...
llvm-svn: 143755
2011-11-05 00:02:56 +00:00
8f249600e7
Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes.
...
I'm going to wait for any review comments and perform some additional testing before turning this on by default.
llvm-svn: 143750
2011-11-04 23:46:11 +00:00
5b8fdd7b62
Cannot create a result register for non-legal types.
...
llvm-svn: 143749
2011-11-04 23:45:39 +00:00
e8b8b77307
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
...
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
llvm-svn: 143743
2011-11-04 23:09:49 +00:00
67f96887aa
Enable support for materializing i1, i8, and i16 integers via move immediate.
...
llvm-svn: 143739
2011-11-04 22:29:00 +00:00
4a2eab0dac
build/cmake: Coalesce the configuration time header include fragment generation
...
for target definitions.
llvm-svn: 143731
2011-11-04 19:04:42 +00:00
4a9c6426ff
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
...
added a layer of indirection with no value (not even conciseness).
llvm-svn: 143727
2011-11-04 19:04:23 +00:00
5b693c2fa6
Add missing argument for atomic instructions in c++ backend. PR11268, part 2.
...
llvm-svn: 143712
2011-11-04 17:29:35 +00:00
caba032f48
Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions
...
llvm-svn: 143683
2011-11-04 06:59:49 +00:00
1ddeb167e8
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen.
...
llvm-svn: 143675
2011-11-04 01:48:58 +00:00
8a98ec4d4b
Indentation.
...
llvm-svn: 143670
2011-11-04 00:58:10 +00:00
f3e73ad5da
Add fast-isel support for returning i1, i8, and i16.
...
llvm-svn: 143669
2011-11-04 00:50:21 +00:00
198b7ffc11
Reapply r143206, with fixes. Disallow physical register lifetimes
...
across calls, and only check for nested dependences on the special
call-sequence-resource register.
llvm-svn: 143660
2011-11-03 21:49:52 +00:00
b68515c232
fixed global array handling for ptx to use the correct bit widths
...
llvm-svn: 143640
2011-11-03 19:24:46 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
...
llvm-svn: 143634
2011-11-03 18:53:17 +00:00
0e7cbbabea
Add new X86 AVX2 VBROADCAST instructions.
...
llvm-svn: 143612
2011-11-03 07:35:53 +00:00
bf5f4bec1a
Add support for sign-extending non-legal types in SelectSIToFP().
...
llvm-svn: 143603
2011-11-03 02:04:59 +00:00
1f4603d498
Fixed parameter name.
...
llvm-svn: 143594
2011-11-02 23:37:04 +00:00
9929c423a1
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
...
llvm-svn: 143582
2011-11-02 22:52:45 +00:00
9cf803c4bf
Add support for comparing integer non-legal types.
...
llvm-svn: 143559
2011-11-02 18:08:25 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
...
llvm-svn: 143557
2011-11-02 18:03:14 +00:00
ec5c5f7008
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
...
llvm-svn: 143553
2011-11-02 17:46:18 +00:00
fad59dab62
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
...
llvm-svn: 143552
2011-11-02 17:41:23 +00:00
4489f948a7
Factor out an EmitIntExt function. No functionality change intended.
...
llvm-svn: 143547
2011-11-02 17:20:24 +00:00
a47b05c7f3
More AVX2 instructions and intrinsics.
...
llvm-svn: 143536
2011-11-02 06:54:17 +00:00
682b850602
Add a bunch more X86 AVX2 instructions and their corresponding intrinsics.
...
llvm-svn: 143529
2011-11-02 04:42:13 +00:00
ee7e452571
Factor out a SelectTrunc function. No functionality change intended.
...
llvm-svn: 143523
2011-11-02 00:18:48 +00:00
5c6b6346bc
ARM label operands can be quoted.
...
For example, labels from Objective-C sources.
llvm-svn: 143511
2011-11-01 22:38:31 +00:00
7f1f3bd868
ARM label operands can have an optional '#' before them.
...
llvm-svn: 143510
2011-11-01 22:37:37 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
...
llvm-svn: 143507
2011-11-01 22:18:13 +00:00
94441fbad7
rename getHostTriple into getDefaultTargetTriple
...
llvm-svn: 143502
2011-11-01 21:32:20 +00:00
3f5eccbe7a
Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289.
...
llvm-svn: 143498
2011-11-01 21:18:39 +00:00
56ce0932db
Don't fold negative offsets into cp / dp accesses to avoid relocation errors.
...
This can happen if the address + addend is less than the start of the cp / dp.
llvm-svn: 143459
2011-11-01 11:31:53 +00:00
fb2f1d61f4
ARM VLD/VST assembly parsing for symbolic address operands.
...
llvm-svn: 143413
2011-11-01 01:24:45 +00:00
d28ddbff8d
Add support for new atomics to cpp backend. Misc other fixes while I'm here. PR11268.
...
llvm-svn: 143406
2011-10-31 23:59:22 +00:00
05df460269
ARM VST1 w/ writeback assembly parsing and encoding.
...
llvm-svn: 143369
2011-10-31 21:50:31 +00:00
e4c8e692f2
ARM writeback vs. stride operands for VST/VLD.
...
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.
llvm-svn: 143356
2011-10-31 19:11:23 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
...
llvm-svn: 143351
2011-10-31 17:17:32 +00:00
cfcfdf2aab
Begin adding AVX2 instructions. No selection support yet other than intrinsics.
...
llvm-svn: 143331
2011-10-31 02:15:10 +00:00
aab6169ef6
Switch new .file directive emission off by default, change llc's flag for it to
...
-enable-dwarf-directory.
llvm-svn: 143326
2011-10-31 01:06:02 +00:00
228d9131aa
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
...
llvm-svn: 143319
2011-10-30 19:57:21 +00:00
7402ee6ec2
X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.
...
llvm-svn: 143315
2011-10-30 17:31:21 +00:00
c602b2c4de
Fix pr11266.
...
On x86: (shl V, 1) -> add V,V
Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.
llvm-svn: 143311
2011-10-30 13:24:22 +00:00
ff91dd9f07
PPC: Disable moves for all CR subregisters.
...
Should fix assertion failures on ppc buildbots.
llvm-svn: 143290
2011-10-29 19:43:38 +00:00
9b9c970148
Revert r143206, as there are still some failing tests.
...
llvm-svn: 143262
2011-10-29 00:41:52 +00:00
3d785edee2
ARM mode 'mov' to 'mvn' assembler alias.
...
llvm-svn: 143237
2011-10-28 22:50:54 +00:00
b009a872d7
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
...
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
llvm-svn: 143235
2011-10-28 22:36:30 +00:00
409b694c6c
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
...
llvm-svn: 143220
2011-10-28 20:43:24 +00:00
104b7e3f2c
Make changes necessary in LowerFormalArguments to support Mips64.
...
llvm-svn: 143218
2011-10-28 19:55:48 +00:00
b20a325baf
Make changes necessary in LowerCall to support Mips64.
...
llvm-svn: 143217
2011-10-28 19:49:00 +00:00
7989f15d37
Add variable IsO32 to MipsTargetLowering.
...
llvm-svn: 143213
2011-10-28 18:47:24 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
...
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
73057ad24f
Reapply r143177 and r143179 (reverting r143188), with scheduler
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fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
llvm-svn: 143206
2011-10-28 17:55:38 +00:00
effd094438
Revert r143202.
...
llvm-svn: 143203
2011-10-28 17:38:30 +00:00
df53d4fd61
Specify fixed bits on CPS instructions to enable roundtripping.
...
llvm-svn: 143202
2011-10-28 17:29:39 +00:00
7a49575d7f
Thumb2 ADD/SUB instructions encoding selection outside IT block.
...
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
llvm-svn: 143201
2011-10-28 16:57:07 +00:00
225a7037d6
Speculatively disable Dan's commits 143177 and 143179 to see if
...
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
llvm-svn: 143188
2011-10-28 09:55:57 +00:00
4db3f7dd83
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
...
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
llvm-svn: 143177
2011-10-28 01:29:32 +00:00
080a499ee0
ARM Allow 'q' registers in VLD/VST vector lists.
...
Just treat it as if the constituent D registers where specified.
rdar://10348896
llvm-svn: 143167
2011-10-28 00:06:50 +00:00
4c9fca99c9
Remove the Alpha backend.
...
llvm-svn: 143164
2011-10-27 22:56:32 +00:00
8a6ebd085a
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
...
llvm-svn: 143162
2011-10-27 22:53:10 +00:00
e5a6adceac
Also set addrmode6 alignment when align==size.
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Previously, we were only setting the alignment bits on over-aligned
loads and stores.
llvm-svn: 143160
2011-10-27 22:39:16 +00:00
12a39540bb
ARM isel for vld1, opcode selection for register stride post-index pseudos.
...
llvm-svn: 143158
2011-10-27 22:25:42 +00:00
f4807a19e8
Avoid partial CPSR dependency from loop backedges. rdar://10357570
...
llvm-svn: 143145
2011-10-27 21:21:05 +00:00
49e6a0da7e
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
...
not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
llvm-svn: 143112
2011-10-27 17:40:41 +00:00
6ed3845530
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
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rdar://10348844
llvm-svn: 143110
2011-10-27 17:33:59 +00:00
ba7f90c7df
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
...
rdar://10348584
llvm-svn: 143108
2011-10-27 17:16:55 +00:00
d24e7e1d9b
A branch predicated on a constant can just FastEmit an unconditional branch.
...
llvm-svn: 143086
2011-10-27 00:21:16 +00:00
58dba012b6
Rename NonScalarIntSafe to something more appropriate.
...
llvm-svn: 143080
2011-10-26 23:50:43 +00:00
a486f44733
Add a TODO comment. FastISel works by parsing each basic block from the bottom
...
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
llvm-svn: 143079
2011-10-26 23:34:37 +00:00
78127d31f3
Factor a little more code into EmitCmp, which should have been done in the first
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place. No functional change intended.
llvm-svn: 143078
2011-10-26 23:25:44 +00:00
eafbf3faa9
Use EmitCmp in SelectBranch. No functional change intended.
...
llvm-svn: 143076
2011-10-26 23:17:28 +00:00
59a201950b
Factor out an EmitCmp function that can be used by both SelectCmp and
...
SelectBranch. No functional change intended.
llvm-svn: 143072
2011-10-26 22:47:55 +00:00
61fdba048f
Thumb2 ldr pc-relative encoding fixes.
...
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
llvm-svn: 143068
2011-10-26 22:22:01 +00:00
b3285224cd
Fixes an issue reported by -verify-machineinstrs.
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Patch by Sanjoy Das.
llvm-svn: 143064
2011-10-26 21:16:41 +00:00
4e380354a9
ARM parse parenthesized expressions for label references.
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Partial fix for rdar://10348687.
llvm-svn: 143063
2011-10-26 21:14:08 +00:00
66393c127d
This commit introduces two fake instructions MORESTACK_RET and
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MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively. Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV). It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.
Patch by Sanjoy Das.
llvm-svn: 143062
2011-10-26 21:12:27 +00:00
c47e283430
Make sure short memsets on ARM lower to stores, even when optimizing for size.
...
llvm-svn: 143055
2011-10-26 20:56:52 +00:00
25d4707c4d
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
...
llvm-svn: 143034
2011-10-26 17:28:15 +00:00
dd9137aa56
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
...
llvm-svn: 143023
2011-10-26 08:53:19 +00:00
1414bc5a14
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
...
llvm-svn: 143018
2011-10-26 07:16:18 +00:00
043c9d3f7a
Revert part of r142530. The patch potentially hurts performance especially
...
on Darwin platforms where -Os means optimize for size without hurting
performance.
llvm-svn: 143002
2011-10-26 01:17:44 +00:00
c0ecd1f7ed
Corrects previously incorrect $sp change in MipsCompilationCallback.
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The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned
Patch by Petar Jovanovic.
llvm-svn: 142930
2011-10-25 17:30:47 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
b43c36f391
Remove the Blackfin backend.
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llvm-svn: 142880
2011-10-25 00:05:42 +00:00
dfc96aea90
Remove the SystemZ backend.
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llvm-svn: 142878
2011-10-24 23:48:32 +00:00
30c39c8bf2
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
...
llvm-svn: 142877
2011-10-24 23:40:46 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
a5e244c08d
Don't crash on variable insertelement on ARM. PR10258.
...
llvm-svn: 142871
2011-10-24 23:08:52 +00:00
f33bfbbace
ARMConstantPoolMBB::print should print BB number.
...
llvm-svn: 142867
2011-10-24 23:01:03 +00:00
3ea0657d54
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
2098cb1e6f
ARM refactor am6offset usage for VLD1.
...
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
b72d55353a
Add support to the old JIT for acquire/release loads and stores on x86. PR11207.
...
llvm-svn: 142841
2011-10-24 20:24:21 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
...
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
4ed1afa51d
Change this overloaded use of Sched::Latency to be an overloaded
...
use of Sched::ILP instead, as Sched::Latency is going away.
llvm-svn: 142813
2011-10-24 17:55:11 +00:00
2c9bda1512
Remove the explicit request for "Latency" scheduling from MSP430,
...
as the Latency scheduler is going away.
llvm-svn: 142811
2011-10-24 17:53:16 +00:00
1b5e49a35a
Thumb2 LDM instructions can target PC. Make sure to encode it.
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PR11220
llvm-svn: 142801
2011-10-24 17:16:24 +00:00
b05d9e9bea
Add X86 SARX, SHRX, and SHLX instructions.
...
llvm-svn: 142779
2011-10-23 22:18:24 +00:00
980d59832a
Add X86 RORX instruction
...
llvm-svn: 142741
2011-10-23 07:34:00 +00:00
e94d277db8
Add X86 MULX instruction for disassembler.
...
llvm-svn: 142738
2011-10-23 00:33:32 +00:00
7412aa9886
Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions.
...
llvm-svn: 142737
2011-10-22 23:13:53 +00:00
0d6d098841
Move various generated tables into read-only memory, fixing up const correctness along the way.
...
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
e649d66552
Fix pr11193.
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SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.
llvm-svn: 142724
2011-10-22 12:39:25 +00:00
94e6643fce
The different flavors of ARM have different valid subsets of registers. Check
...
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
llvm-svn: 142706
2011-10-22 00:29:28 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
...
llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
...
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
...
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
...
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
...
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
03a173eb71
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
...
llvm-svn: 142669
2011-10-21 18:43:28 +00:00
e6d88c9a51
Nuke an #if0 that got accidentally left in.
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llvm-svn: 142658
2011-10-21 16:59:08 +00:00
20cb505e2f
whitespace.
...
llvm-svn: 142657
2011-10-21 16:56:40 +00:00
e3013dd62d
Remove some outdated comments.
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llvm-svn: 142653
2011-10-21 16:14:12 +00:00
039a79067a
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
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llvm-svn: 142642
2011-10-21 06:55:01 +00:00
c842c2ffe2
Fix unused variable warning.
...
llvm-svn: 142630
2011-10-21 01:22:04 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
...
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
000e2add18
Disable the PPC hazard recognizer. It currently only supports
...
top-down scheduling and top-down scheduling is going away.
llvm-svn: 142621
2011-10-20 21:45:36 +00:00
3acac94b60
Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
...
llvm-svn: 142618
2011-10-20 21:24:38 +00:00
cf7bdf4438
Add missing operand. <rdar://problem/10313323>
...
llvm-svn: 142615
2011-10-20 20:37:11 +00:00
aaf379027d
Haven't yet found a nice way to handle TargetData verification in the
...
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.
llvm-svn: 142605
2011-10-20 19:24:44 +00:00
79ebc51c45
Tidy up. Trailing whitespace.
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llvm-svn: 142591
2011-10-20 17:28:20 +00:00
9036c5cf2b
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
...
llvm-svn: 142583
2011-10-20 15:04:25 +00:00
8db25984a9
ARM VTBX (one register) assembly parsing and encoding.
...
llvm-svn: 142581
2011-10-20 14:48:50 +00:00
add38c12b8
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
...
llvm-svn: 142557
2011-10-20 00:07:12 +00:00
54d678fff4
Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355
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llvm-svn: 142550
2011-10-19 22:22:54 +00:00
2d768fd379
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
...
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
llvm-svn: 142530
2011-10-19 14:11:07 +00:00
2977a15ab1
Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.
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llvm-svn: 142485
2011-10-19 09:24:02 +00:00
7c1634556d
Remove some dead code.
...
llvm-svn: 142484
2011-10-19 09:04:11 +00:00
ef309c3384
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
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llvm-svn: 142480
2011-10-19 07:48:35 +00:00
94f60018e0
Emit the MOVT instruction only if the # LPads is > 64K.
...
llvm-svn: 142460
2011-10-18 23:19:55 +00:00
64e6bfc16c
For Thumb mode, we need to use a constant pool if the value is too large to be
...
used with the CMP instruction.
llvm-svn: 142458
2011-10-18 23:11:05 +00:00
16ec8c103a
Revert "Turn on the vzeroupper pass by default."
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This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.
llvm-svn: 142455
2011-10-18 23:10:11 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
4969dcdef9
Use the integer compare when the value is small enough. Use the "move into a
...
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
llvm-svn: 142440
2011-10-18 22:52:20 +00:00
9bede2dd92
Turn on the vzeroupper pass by default.
...
I'll remove/rename the option in a few days.
llvm-svn: 142439
2011-10-18 22:50:17 +00:00
85833f71c6
Use the integer compare when the value is small enough. Use the "move into a
...
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
llvm-svn: 142437
2011-10-18 22:49:07 +00:00
7d2f7b5a33
Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>.
...
llvm-svn: 142432
2011-10-18 22:11:33 +00:00
973c817cde
The value we're comparing against may be too large for the ARM CMP
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instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>
llvm-svn: 142431
2011-10-18 22:11:18 +00:00
b2a703d352
The immediate may be too large for the CMP instruction. Move it into a register
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and use that in the CMP.
<rdar://problem/10305266>
llvm-svn: 142429
2011-10-18 21:55:58 +00:00
6918617e32
Yet more ARM NEON assembly parsing for the lane index operand.
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llvm-svn: 142416
2011-10-18 20:21:17 +00:00
e9f204c197
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142413
2011-10-18 20:14:56 +00:00
712f3670fd
ARM vmov assembly parsing for the lane index operand.
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llvm-svn: 142412
2011-10-18 20:10:47 +00:00
88b2450adc
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
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Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
llvm-svn: 142397
2011-10-18 19:18:52 +00:00
93b0f7b319
Use isIntN and isUIntN to check for valid signed/unsigned numbers.
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llvm-svn: 142395
2011-10-18 18:46:49 +00:00
3f07c429b5
whitespace
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llvm-svn: 142394
2011-10-18 18:40:53 +00:00
617075fcf6
A landing pad could have more than one predecessor. In that case, we want that
...
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>
llvm-svn: 142390
2011-10-18 18:30:49 +00:00
611450071c
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142389
2011-10-18 18:27:07 +00:00
c8eff0327a
ARM vqdmulh assembly parsing for the lane index operand.
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llvm-svn: 142386
2011-10-18 18:12:09 +00:00
e6fbca3a61
ARM vmul assembly parsing for the lane index operand.
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llvm-svn: 142381
2011-10-18 18:01:52 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
...
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
9258b76d8d
Fix incorrect check for sign-extended constant BUILD_VECTOR.
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<rdar://problem/10298332>
llvm-svn: 142371
2011-10-18 17:34:51 +00:00
af26d7e280
ARM vqdmlal assembly parsing for the lane index operand.
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llvm-svn: 142365
2011-10-18 17:16:30 +00:00
dfa7fb8fe6
Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
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llvm-svn: 142363
2011-10-18 17:09:35 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
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llvm-svn: 142356
2011-10-18 16:18:11 +00:00
1fb5bb126e
PTX: Fix disabling of MAD instruction selection
...
llvm-svn: 142352
2011-10-18 13:39:20 +00:00
d278d35b13
Fix a bunch of unused variable warnings when doing a release
...
build with gcc-4.6.
llvm-svn: 142350
2011-10-18 12:44:00 +00:00
2b7a1ff77f
Coding style cleanups. No functionality change.
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llvm-svn: 142341
2011-10-18 07:40:22 +00:00
49045ddb4c
Remove NaClMode
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llvm-svn: 142338
2011-10-18 05:29:23 +00:00
0ffe593a16
Add support for dynamic stack realignment when in thumb1 mode.
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rdar://10288916
llvm-svn: 142337
2011-10-18 05:28:00 +00:00
1c192774b6
Commit test, capitalizing store... keep it simple.
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llvm-svn: 142336
2011-10-18 04:44:36 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
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llvm-svn: 142332
2011-10-18 03:17:34 +00:00
22d3adf6aa
Backing out patch. Will refactor to remove the AsmParser dependency on Target.
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llvm-svn: 142323
2011-10-18 00:23:49 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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llvm-svn: 142321
2011-10-18 00:22:00 +00:00
Jia Liu