2ca79b9d4b
Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.
...
llvm-svn: 147360
2011-12-30 01:49:53 +00:00
692d1fb355
Cleanup stack/frame register define/kill states. This fixes two bugs:
...
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
llvm-svn: 147359
2011-12-30 00:34:00 +00:00
d773607eee
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
...
llvm-svn: 147353
2011-12-29 20:43:40 +00:00
8cab06a214
Expose FMA3 instructions to the disassembler.
...
llvm-svn: 147351
2011-12-29 20:03:14 +00:00
e1bd05128e
Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled.
...
llvm-svn: 147349
2011-12-29 19:46:19 +00:00
dd286a5201
Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.
...
llvm-svn: 147348
2011-12-29 19:25:56 +00:00
a060afb5ba
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339.
...
llvm-svn: 147347
2011-12-29 18:47:31 +00:00
97f05c5768
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.
...
llvm-svn: 147345
2011-12-29 18:08:36 +00:00
1559123c77
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.
...
llvm-svn: 147344
2011-12-29 18:00:08 +00:00
9e61291bf5
Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns.
...
llvm-svn: 147342
2011-12-29 17:41:56 +00:00
7bd3305f3e
Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A.
...
llvm-svn: 147339
2011-12-29 15:51:45 +00:00
0fdf720ded
Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8.
...
llvm-svn: 147337
2011-12-29 03:34:54 +00:00
862c9b65be
Remove some elses after returns.
...
llvm-svn: 147336
2011-12-29 03:20:51 +00:00
274e20a499
Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path.
...
llvm-svn: 147335
2011-12-29 03:09:33 +00:00
3a01ddb7e9
Fix type-checking for load transformation which is not legal on floating-point types. PR11674.
...
llvm-svn: 147323
2011-12-28 21:24:44 +00:00
b3515a8d4b
Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.
...
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.
llvm-svn: 147308
2011-12-28 08:14:01 +00:00
b668401b2e
Clean up some Release build warnings.
...
llvm-svn: 147289
2011-12-27 11:41:05 +00:00
df34d152bd
Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't.
...
llvm-svn: 147287
2011-12-27 06:27:23 +00:00
1fc8263b4d
Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks.
...
llvm-svn: 147269
2011-12-25 18:50:24 +00:00
a56ab0ede7
Section relative fixups are a coff concept, not a x86 one. Replace the
...
x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.
llvm-svn: 147252
2011-12-24 14:47:52 +00:00
a3d54fe0ae
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the
...
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type
We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]
llvm-svn: 147251
2011-12-24 12:12:34 +00:00
38ce24455d
Add systematic testing for cttz as well, and fix the bug I spotted by
...
inspection earlier.
llvm-svn: 147250
2011-12-24 11:46:10 +00:00
767bbe48c1
Chandler fixed this.
...
llvm-svn: 147247
2011-12-24 11:23:32 +00:00
c9fcde2347
Expand more when we have a nice 'tzcnt' instruction, to avoid generating
...
'bsf' instructions here.
This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.
llvm-svn: 147246
2011-12-24 11:11:38 +00:00
7e9453e916
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the
...
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:
(sizeof(x)*8 - 1) ^ __builtin_clz(x)
Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.
The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.
Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.
These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.
llvm-svn: 147244
2011-12-24 10:55:54 +00:00
103318e9ea
Fix Comments.
...
llvm-svn: 147238
2011-12-24 04:17:01 +00:00
1cf7576707
Add MachineMemOperands to instructions generated in storeRegToStackSlot or
...
loadRegFromStackSlot.
llvm-svn: 147235
2011-12-24 03:11:18 +00:00
6f54a46133
Detect unaligned loads/stores that have been added for Mips64 support.
...
llvm-svn: 147234
2011-12-24 03:07:37 +00:00
695d113adc
If target ABI is N64, LEA should be daddiu.
...
llvm-svn: 147232
2011-12-24 02:59:27 +00:00
908d2ed14e
Move x86 specific bits of the COFF writer to lib/Target/X86.
...
llvm-svn: 147231
2011-12-24 02:14:02 +00:00
0965585cb1
Experimental support for aligned NEON spills.
...
ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.
Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.
This feature is off by default, controlled by an -align-neon-spills
command line option.
llvm-svn: 147211
2011-12-23 00:36:18 +00:00
1a74de9504
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
...
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
llvm-svn: 147204
2011-12-22 23:39:48 +00:00
00bbedff03
Fix 80-column violations.
...
llvm-svn: 147192
2011-12-22 22:35:21 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
...
rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
268d2599e0
Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.
...
Noticed by inspection; I don't have a testcase for this.
llvm-svn: 147188
2011-12-22 22:12:44 +00:00
c4d8d2f155
Tidy up. Use predicate function a bit more liberally.
...
llvm-svn: 147184
2011-12-22 22:02:35 +00:00
6ca42c5be3
Fix incorrect relocation generation. Patch by Kristof Beyls.
...
Fixes PR11214.
llvm-svn: 147180
2011-12-22 21:36:43 +00:00
f0d25117c6
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
...
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
llvm-svn: 147170
2011-12-22 19:55:21 +00:00
b65dd04923
Remove some bogus comments.
...
llvm-svn: 147169
2011-12-22 19:45:01 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
...
llvm-svn: 147158
2011-12-22 19:20:45 +00:00
250096233b
Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting
...
it. It does need some some tests...
llvm-svn: 147154
2011-12-22 18:38:06 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
...
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
21488b8839
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
...
llvm-svn: 147152
2011-12-22 17:37:00 +00:00
3794d82af5
Tidy up. Trailing whitespace.
...
llvm-svn: 147151
2011-12-22 17:17:10 +00:00
62bffd8827
Nuke invalid comment from copy/paste.
...
llvm-svn: 147150
2011-12-22 17:04:50 +00:00
1dc45d8df4
Move the Mips only bits of the ELF writer to lib/Target/Mips.
...
llvm-svn: 147133
2011-12-22 03:03:17 +00:00
84d00f11cd
Make the virtual methods in ARMELFObjectWriter public.
...
llvm-svn: 147132
2011-12-22 02:58:12 +00:00
cc369ac0a2
Move the MBlaze ELF writer bits to lib/Target/MBlaze.
...
llvm-svn: 147129
2011-12-22 02:28:24 +00:00
428b9ee036
Fix cmake.
...
llvm-svn: 147126
2011-12-22 02:06:17 +00:00
38a400df3b
Move PPC bits to lib/Target/PowerPC.
...
llvm-svn: 147124
2011-12-22 01:57:09 +00:00
2da9777cef
Hopefully fix the cmake build.
...
llvm-svn: 147121
2011-12-22 01:11:01 +00:00
4449b21294
Fix name in comments.
...
llvm-svn: 147119
2011-12-22 01:06:53 +00:00
e2eed9649e
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
...
ELF relocations.
Patch by Jack Carter.
llvm-svn: 147118
2011-12-22 01:05:17 +00:00
32a756b7ce
Unbreak cmake build after r147115.
...
llvm-svn: 147117
2011-12-22 01:03:35 +00:00
a0124055b1
Move the ARM specific parts of the ELF writer to Target/ARM.
...
llvm-svn: 147115
2011-12-22 00:37:50 +00:00
2b80dad572
ARM NEON mnemonic aliase for vrecpeq.
...
llvm-svn: 147109
2011-12-21 23:52:37 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
...
llvm-svn: 147104
2011-12-21 23:24:15 +00:00
260b4b336a
ARM NEON optional data type on VSWP instructions.
...
llvm-svn: 147103
2011-12-21 23:09:28 +00:00
a50e24fcb3
ARM NEON mnemonic aliases for vzipq and vswpq.
...
llvm-svn: 147102
2011-12-21 23:04:33 +00:00
1152cc0cad
ARM asm parser should be more lenient w/ .thumb_func directive.
...
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
3172488cc0
Fix 80-column violations.
...
llvm-svn: 147095
2011-12-21 20:59:09 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
3588a43e3a
Move common code into an MRI function.
...
llvm-svn: 147071
2011-12-21 19:50:05 +00:00
c80a264386
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
...
llvm-svn: 147069
2011-12-21 19:40:55 +00:00
3ede414127
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
...
necessary. Please chime in if I'm mistaken.
llvm-svn: 147065
2011-12-21 19:14:52 +00:00
7248bda595
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
...
llvm-svn: 147064
2011-12-21 18:56:22 +00:00
b264d33854
Move the X86 specific bits of the ELF writer to the Target/X86 directory.
...
Other targets will follow shortly.
llvm-svn: 147060
2011-12-21 17:30:17 +00:00
1ad4095d6b
Reduce the exposure of Triple::OSType in the ELF object writer. This will
...
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
2011-12-21 17:00:36 +00:00
b8b1b4c1de
Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.
...
llvm-svn: 147046
2011-12-21 08:06:52 +00:00
f30188418b
Fix typo in a couple comments
...
llvm-svn: 147045
2011-12-21 06:30:53 +00:00
dc8a1aaea6
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
...
llvm-svn: 147032
2011-12-21 03:04:10 +00:00
7de7ab83fa
ARM assembly parsing allows constant expressions for lane indices.
...
llvm-svn: 147028
2011-12-21 01:19:23 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
...
The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
1d8efaba7e
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
...
case for DCLO and DCLZ.
llvm-svn: 147022
2011-12-21 00:20:27 +00:00
410ce9cb44
Expand 64-bit CTPOP and CTTZ.
...
llvm-svn: 147021
2011-12-21 00:14:05 +00:00
91c052c4d8
Expand 64-bit atomic load and store.
...
llvm-svn: 147019
2011-12-21 00:02:58 +00:00
4706ac9715
Add definition of DSBH (Double Swap Bytes within Halfwords) and
...
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
llvm-svn: 147017
2011-12-20 23:56:43 +00:00
43c1ff4db3
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
...
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
llvm-svn: 147015
2011-12-20 23:47:44 +00:00
79aed157e7
64-bit uint-fp conversion nodes are expanded.
...
llvm-svn: 147014
2011-12-20 23:40:56 +00:00
2bb8d068f5
Enable custom lowering DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 147013
2011-12-20 23:35:46 +00:00
8e2c02e2d6
Set the correct stack pointer register that should be saved or restored.
...
llvm-svn: 147012
2011-12-20 23:28:36 +00:00
cd22e4a81e
ARM .req register name aliases are case insensitive, just like regnames.
...
llvm-svn: 147009
2011-12-20 23:11:00 +00:00
cb2a85bc22
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
...
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
llvm-svn: 147008
2011-12-20 23:10:57 +00:00
2c8d1734f8
Fix indentation.
...
llvm-svn: 147007
2011-12-20 22:58:01 +00:00
cf10f08825
64-bit data directive.
...
llvm-svn: 147005
2011-12-20 22:52:19 +00:00
494fdf1499
32-to-64-bit sext_inreg pattern.
...
llvm-svn: 147004
2011-12-20 22:40:40 +00:00
8756816e6f
Add 64-bit extload patterns.
...
llvm-svn: 147003
2011-12-20 22:36:08 +00:00
0cee2045c9
Add patterns for matching extloads with 64-bit address. The patterns are enabled
...
only when the target ABI is N64.
llvm-svn: 147001
2011-12-20 22:33:53 +00:00
4eda145c7f
Move comment to appropriate place.
...
llvm-svn: 147000
2011-12-20 22:26:38 +00:00
dac1d48d8d
Add code in MipsDAGToDAGISel for selecting constant +0.0.
...
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
llvm-svn: 146999
2011-12-20 22:25:50 +00:00
b95c102c2f
Heed spill slot alignment on ARM.
...
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
llvm-svn: 146997
2011-12-20 22:15:04 +00:00
14468c6cb6
Revert part of r146995 that was accidentally commmitted.
...
llvm-svn: 146996
2011-12-20 22:09:36 +00:00
4e210691c0
32-to-64-bit sign extension pattern.
...
llvm-svn: 146995
2011-12-20 22:06:20 +00:00
9b9bd1cc15
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
...
only when the target ABI is N64.
llvm-svn: 146992
2011-12-20 21:50:49 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
...
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
135d244b56
First steps in ARM AsmParser support for .eabi_attribute and .arch
...
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
ec7e6e0946
This is the second fix related to VZEXT_MOVL node.
...
The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
llvm-svn: 146975
2011-12-20 13:34:28 +00:00
24680c24d8
Begin teaching the X86 target how to efficiently codegen patterns that
...
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
llvm-svn: 146974
2011-12-20 11:19:37 +00:00
e805b16e3d
Fix up the CMake build for the new files added in r146960, they're
...
likely to stay either way that discussion ends up resolving itself.
llvm-svn: 146966
2011-12-20 08:42:11 +00:00
a379b18173
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
...
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
75f12cc3fe
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
...
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
llvm-svn: 146949
2011-12-20 01:29:27 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
94580ab375
Add basic generic CodeGen support for half.
...
llvm-svn: 146927
2011-12-20 00:02:33 +00:00
045b6c71a6
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
...
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
...
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
...
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
64f4de29e0
ARM NEON two-operand aliases for VPADD.
...
rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
2a232d81f6
Remove definitions of double word shift plus 32 instructions. Assembler or
...
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
llvm-svn: 146893
2011-12-19 19:44:09 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
...
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
c4db30e358
Remove unused predicate.
...
llvm-svn: 146889
2011-12-19 19:32:20 +00:00
3c9f336361
Remove the restriction on the first operand of the add node in SelectAddr.
...
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
llvm-svn: 146888
2011-12-19 19:28:37 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
...
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
9ae4fc035b
ARM NEON implied destination aliases for VMAX/VMIN.
...
llvm-svn: 146885
2011-12-19 18:57:38 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
a7d2421603
Tidy up.
...
llvm-svn: 146882
2011-12-19 18:11:17 +00:00
24159e346d
Remove a register class that can just as well be synthesized.
...
Add the new TableGen register class synthesizer feature to the release
notes.
llvm-svn: 146875
2011-12-19 16:53:40 +00:00
c7b437ae34
Emit a getMatchingSuperRegClass() implementation for every target.
...
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
llvm-svn: 146873
2011-12-19 16:53:34 +00:00
1b54835a10
Another variadics tweak.
...
llvm-svn: 146852
2011-12-18 20:51:31 +00:00
530b820500
Use the fancy new VariadicFunction template instead of a plain variadic function.
...
Some compilers were complaining about passing StringRef to it.
llvm-svn: 146850
2011-12-18 19:59:20 +00:00
32481916eb
Hexagon: Remove unused variables.
...
llvm-svn: 146846
2011-12-18 12:00:09 +00:00
a913dde0ef
Remove an unused X86ISD node type.
...
llvm-svn: 146833
2011-12-17 19:16:44 +00:00
792edd3c75
X86: Factor the bswap asm matching to be slightly less horrible to read.
...
llvm-svn: 146831
2011-12-17 14:36:05 +00:00
903231bc58
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
...
llvm-svn: 146805
2011-12-17 01:25:34 +00:00
d3df3d3527
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
...
asm parsing and testcase.
llvm-svn: 146801
2011-12-17 01:14:52 +00:00
da07b3ad42
Make sure that the lower bits on the VSELECT condition are properly set.
...
llvm-svn: 146800
2011-12-17 01:08:46 +00:00
465cdf3ba4
Preserve more memory operands in ARMExpandPseudo.
...
I don't think this affects anything but verbose assembly.
llvm-svn: 146787
2011-12-17 00:07:02 +00:00
9790187b6c
Fix off-by-one error in bucket sort.
...
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
llvm-svn: 146767
2011-12-16 23:00:05 +00:00
5af144809e
Don't adjust for alignment padding in OffsetIsInRange.
...
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.
When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.
llvm-svn: 146751
2011-12-16 19:10:00 +00:00
9ca2e7293b
Hexagon: Fix a nasty order-of-initialization bug.
...
Reenable the tests.
llvm-svn: 146750
2011-12-16 19:08:59 +00:00
2a05f691ab
Note ARM constant island alignment in the release notes.
...
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.
llvm-svn: 146739
2011-12-16 16:07:41 +00:00
a4d411cb1b
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
...
llvm-svn: 146726
2011-12-16 08:06:31 +00:00
93d990bd61
Target/Hexagon: Fix CMake build.
...
llvm-svn: 146724
2011-12-16 06:21:02 +00:00
4a29971f02
ARM NEON aliases for vmovq.f*
...
llvm-svn: 146714
2011-12-16 00:12:22 +00:00
66886253a7
Thumb2 ADR assembly parsing w/o the .w suffix.
...
llvm-svn: 146710
2011-12-15 23:52:17 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
...
llvm-svn: 146709
2011-12-15 23:46:18 +00:00
c9e935c7e2
Move parts of lib/Target that use CodeGen into lib/CodeGen.
...
llvm-svn: 146702
2011-12-15 22:58:58 +00:00
c9bf1b1bff
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
...
llvm-svn: 146700
2011-12-15 22:56:53 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
...
llvm-svn: 146699
2011-12-15 22:56:33 +00:00
b3705e0b9e
Add MCTargetDesc library to Hexagon target
...
llvm-svn: 146692
2011-12-15 22:29:08 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
...
llvm-svn: 146691
2011-12-15 22:27:11 +00:00
cba8e8c3e0
Enable proper constant island alignment by default.
...
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.
llvm-svn: 146690
2011-12-15 22:14:45 +00:00
41dbf59e12
Add missing zmovl AVX patterns which were causing crashes.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146689
2011-12-15 22:11:31 +00:00
c2f16a3499
Silence warning.
...
llvm-svn: 146686
2011-12-15 21:54:55 +00:00
2f50e92f40
ARM NEON two-register double spaced register list parsing support.
...
llvm-svn: 146685
2011-12-15 21:44:33 +00:00
75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
c44b5e469b
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
...
llvm-svn: 146671
2011-12-15 18:57:27 +00:00
9dd3f62b38
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
...
llvm-svn: 146664
2011-12-15 17:54:01 +00:00
275e874c67
Pass optLevel to XCoreDAGToDAGISel.
...
Patch by Kyriakos Georgiou.
llvm-svn: 146656
2011-12-15 15:18:35 +00:00
b7a0b89ff0
Use SmallVector/assign(), rather than std::vector/push_back().
...
llvm-svn: 146627
2011-12-15 01:16:09 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
...
rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
ae94fb4009
The saved registers weren't being processed in the correct order. This lead to
...
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
llvm-svn: 146612
2011-12-14 23:53:24 +00:00
9efd7ebf0a
Consider CPE alignment in CreateNewWater().
...
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
llvm-svn: 146609
2011-12-14 23:48:54 +00:00
da51104282
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
...
Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
8e987f5e25
Nuke old code. Missed in last commit.
...
llvm-svn: 146590
2011-12-14 21:41:32 +00:00
88ac761aa4
ARM NEON refactor VST2 w/ writeback instructions.
...
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
llvm-svn: 146588
2011-12-14 21:32:11 +00:00
b7ec06c5c9
ARM NEON improve factoring a bit. No functional change.
...
llvm-svn: 146585
2011-12-14 20:59:15 +00:00
da103bf9ec
Model ARM predicated write as read-mod-write. e.g.
...
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
llvm-svn: 146583
2011-12-14 20:00:08 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
e5585e8fed
Fix speling and 80-col.
...
llvm-svn: 146575
2011-12-14 18:49:13 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
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emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
4288b9786f
Fix copy/pasto that skipped the 'modify' step.
...
llvm-svn: 146571
2011-12-14 18:12:37 +00:00
1bb6e066f6
ARM/Thumb2 mov vs. mvn alias goes both ways.
...
llvm-svn: 146570
2011-12-14 17:56:51 +00:00
ded6160473
VFP2 is required for FP loads. Noticed by inspection.
...
llvm-svn: 146569
2011-12-14 17:55:03 +00:00
fce28914ea
Tidy up.
...
llvm-svn: 146568
2011-12-14 17:32:02 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
a26979be29
Fix 80-column violation and extraneous brackets.
...
llvm-svn: 146566
2011-12-14 17:26:05 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
6eb142a616
Thumb2 pre/post indexed stores can be from any non-PC GPR.
...
rdar://10549786
llvm-svn: 146518
2011-12-13 21:10:25 +00:00
5ac89675a0
Thumb2 tweak for ccout handling in RSB parsing.
...
llvm-svn: 146516
2011-12-13 21:06:41 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
...
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
...
llvm-svn: 146507
2011-12-13 20:08:32 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
5e9d16cb53
Expand .cprestore directive to multiple instructions if the offset does not fit
...
in a 16-bit field.
llvm-svn: 146469
2011-12-13 03:09:05 +00:00
637cc6a8aa
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
...
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
llvm-svn: 146466
2011-12-13 01:56:10 +00:00
bfa576fe8e
Account for CPE alignment when searching for new water.
...
Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.
Also take the extra padding into account when the water is above the
use.
llvm-svn: 146458
2011-12-13 00:44:30 +00:00
4ea3c8f54a
Target/Hexagon: Fix CMake build. We don't use add_llvm_library_dependencies().
...
llvm-svn: 146457
2011-12-13 00:36:04 +00:00
8889bb08b8
LLVMBuild: Introduce a common section which currently has a list of the
...
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
llvm-svn: 146436
2011-12-12 22:45:54 +00:00
5d5e0d819d
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
...
-relocation-model=static.
llvm-svn: 146432
2011-12-12 22:39:35 +00:00
faa88c0add
Fix indentation.
...
llvm-svn: 146431
2011-12-12 22:38:19 +00:00
36e0519ca2
fix warning
...
llvm-svn: 146420
2011-12-12 21:52:59 +00:00
fadc2c83e5
Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
...
These modifiers simply select either the low or high D subregister of a Neon
Q register. I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.
llvm-svn: 146417
2011-12-12 21:45:15 +00:00
1213a7a57f
Hexagon backend support
...
llvm-svn: 146412
2011-12-12 21:14:40 +00:00
27a7489a03
LLVMBuild: Remove trailing newline, which irked me.
...
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
7c0face455
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
91a7bcbb9b
Add a postOffset() alignment argument.
...
This computes the offset of the layout sucessor block, considering its
alignment as well.
llvm-svn: 146401
2011-12-12 19:25:54 +00:00
0863de458d
Fix typo.
...
llvm-svn: 146400
2011-12-12 19:25:51 +00:00
6dd2488383
XOP encoding bits and logic.
...
llvm-svn: 146397
2011-12-12 19:12:26 +00:00
17c27a8898
Also set the proper alignment on inner islands and the function itself.
...
Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.
This is all gated by -arm-align-constant-islands.
llvm-svn: 146391
2011-12-12 18:45:45 +00:00
2a75997858
Make MF a class member instead of passing it around everywhere.
...
Also add an MCP member pointing to the machine constant pool.
No functional change intended.
llvm-svn: 146382
2011-12-12 18:16:53 +00:00
b5f52aad22
Add a -arm-align-constant-islands flag, default off.
...
Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment. When the command line
flag is set, also align the basic block containing the constant pool
entries.
This is only a partial implementation of constant island alignment. More
to come.
llvm-svn: 146375
2011-12-12 16:49:37 +00:00
1fdfec63a4
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
...
llvm-svn: 146344
2011-12-11 19:12:35 +00:00
4683740967
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
...
llvm-svn: 146341
2011-12-11 14:35:48 +00:00
64ba50a972
Mips: Don't create a dangling IR function just to get the address of a symbol.
...
llvm-svn: 146340
2011-12-11 12:21:34 +00:00
a6c59b8fc8
Also remove unnecessary includes from this file, which was supposed to be part
...
of r146334!
llvm-svn: 146338
2011-12-11 00:45:13 +00:00
a461c1c069
Minimize #include's and forward-declares in Target.
...
llvm-svn: 146335
2011-12-10 22:35:47 +00:00
b9cda978ab
Refactor the implementation of the TargetOptions out of TargetMachine, taking
...
the only parts of TM that depends on CodeGen headers with it.
llvm-svn: 146334
2011-12-10 22:34:41 +00:00
6641294e3b
Revert r146322 to appease buildbots. Original commit message:
...
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
llvm-svn: 146328
2011-12-10 19:55:03 +00:00
df0b779e9f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
...
llvm-svn: 146322
2011-12-10 08:42:24 +00:00
67a7f18faf
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
...
llvm-svn: 146318
2011-12-10 04:50:53 +00:00
146ac7b609
Try to align the point where a large basic block is split.
...
The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.
This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.
<rdar://problem/10550705>
There is still an issue with correctly packing differently aligned
entries in the island.
llvm-svn: 146314
2011-12-10 02:55:10 +00:00
b3734522fa
More debug output formatting.
...
llvm-svn: 146313
2011-12-10 02:55:06 +00:00
c7f355b8e1
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
...
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
llvm-svn: 146311
2011-12-10 02:28:43 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146300
2011-12-10 00:01:02 +00:00
4e36a934dc
Splats can contain undef's; make sure to handle them correctly. PR11526.
...
llvm-svn: 146299
2011-12-09 23:54:42 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
ef70e9b704
ARM allows '' syntax, not just '#imm' for assembly.
...
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
6192b6570d
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
llvm-svn: 146283
2011-12-09 22:02:17 +00:00
ea1b353e67
ARM NEON data type aliases for VBIC(register).
...
llvm-svn: 146281
2011-12-09 21:46:04 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
f85723626c
User a helper overload for a common pattern.
...
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
8a4009dab2
Tidy up. Better base class factoring.
...
llvm-svn: 146267
2011-12-09 19:07:20 +00:00
b076e6f3d5
Tidy up. Better base class factoring.
...
llvm-svn: 146266
2011-12-09 18:54:11 +00:00
5f5fa12413
Tweak debugging output.
...
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
863683c590
This is now implemented.
...
llvm-svn: 146258
2011-12-09 15:45:57 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
...
llvm-svn: 146257
2011-12-09 15:44:03 +00:00
2dc5dec41d
X86: Split (v)rounds[sd] into a normal and an intrinsic version.
...
llvm-svn: 146256
2011-12-09 15:43:55 +00:00
feb9f27de1
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
...
llvm-svn: 146247
2011-12-09 06:41:08 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
...
llvm-svn: 146246
2011-12-09 06:32:46 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
...
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
...
llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
bb15fec2b8
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
...
llvm-svn: 146193
2011-12-08 22:15:21 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
...
code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
98bc797b4d
ARM asm parser, just issue a warning for a duplicate reg in a list.
...
For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
f10ee84956
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
...
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
llvm-svn: 146183
2011-12-08 21:05:38 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
...
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
57a7f41d5d
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
...
Fixes failures caused by r146171.
llvm-svn: 146180
2011-12-08 20:51:38 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
...
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
...
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
...
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
...
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
4edc7360c7
ARM assembler support for register name aliases.
...
rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
...
if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
...
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
d19760a40c
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
...
llvm-svn: 146151
2011-12-08 14:43:19 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
528ff4bee0
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
...
llvm-svn: 146137
2011-12-08 04:36:44 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
14e024dff7
Drop the HasInlineAsm flag.
...
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
llvm-svn: 146124
2011-12-08 01:22:39 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
bd97f5d753
Simplify offset verification.
...
llvm-svn: 146121
2011-12-08 01:10:05 +00:00
0dd1bc9c79
Fix copy/past-o.
...
llvm-svn: 146120
2011-12-08 01:02:26 +00:00
31a462c02c
ARM NEON two-operand aliases for VMUL.
...
llvm-svn: 146119
2011-12-08 00:59:47 +00:00
2a82333f54
Don't include alignment padding in BBInfo.Size.
...
Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
llvm-svn: 146118
2011-12-08 00:55:02 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
...
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
086d013e56
ARM VFP support 'flds/fldd' aliases for 'vldr'
...
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
66232aa19d
Add newline.
...
llvm-svn: 146100
2011-12-07 23:26:03 +00:00
36d2198dae
Add 64-bit HWR29 register.
...
llvm-svn: 146099
2011-12-07 23:23:52 +00:00
9778e7a67c
32 to 64-bit anyext pattern.
...
llvm-svn: 146097
2011-12-07 23:21:19 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
...
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
56b70de01b
Variable cleanup. Based on past patch submittals variable names have
...
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
llvm-svn: 146088
2011-12-07 22:35:30 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
...
llvm-svn: 146086
2011-12-07 22:11:43 +00:00
6820eebde1
Define base class for WrapperPICPat.
...
llvm-svn: 146081
2011-12-07 21:54:54 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4f864b78e6
Fix comment.
...
llvm-svn: 146063
2011-12-07 20:15:01 +00:00
d16e926a6b
Fix comment.
...
llvm-svn: 146062
2011-12-07 20:13:53 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d633c2f120
Nuke inadvertant debugging commit.
...
llvm-svn: 146057
2011-12-07 19:56:16 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
...
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
...
rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
...
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
...
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
1d578e8835
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
...
llvm-svn: 146031
2011-12-07 08:30:53 +00:00
302cf8d5d0
Adjust the stack by one pointer size for all frameless stacks.
...
llvm-svn: 146030
2011-12-07 07:58:55 +00:00
3c86459997
Fix off-by-one error when encoding the stack size for a frameless stack.
...
llvm-svn: 146029
2011-12-07 07:49:49 +00:00
7f8e563a69
Add bundle aware API for querying instruction properties and switch the code
...
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
ac9df3d411
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
...
llvm-svn: 146024
2011-12-07 06:34:06 +00:00
16c744180d
make base register selection used in eliminateFrameIndex 64-bit clean
...
llvm-svn: 146023
2011-12-07 06:34:02 +00:00
abbc2529c1
set mayStore and mayLoad on CR pseudos
...
llvm-svn: 146022
2011-12-07 06:33:57 +00:00
2ba61e47a9
64-bit LR8 load should use X11 not R11
...
llvm-svn: 146021
2011-12-07 06:32:37 +00:00
2f0400b780
Eliminate delta argument from AdjustBBOffsetsAfter.
...
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
llvm-svn: 146018
2011-12-07 05:17:30 +00:00
97c857199e
Compute some alignment information for each basic block.
...
These fields are not used for anything yet.
llvm-svn: 146017
2011-12-07 04:17:35 +00:00
2cf294a213
ARM tidy up and remove no longer needed InstAlias definitions.
...
The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
af748e1180
Move common expression into a method.
...
llvm-svn: 146008
2011-12-07 01:22:52 +00:00
585ce30b8b
ARM Implement ARM ARM Table A7-3 via TokenAlias.
...
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
llvm-svn: 146007
2011-12-07 01:17:58 +00:00
e2b3ff2a07
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
...
No functional change is intended.
llvm-svn: 146005
2011-12-07 01:08:25 +00:00
d4b8249434
ARM: NEON SHLL instruction immediate operand range checking.
...
llvm-svn: 146003
2011-12-07 01:07:24 +00:00
61e6d987bf
Add a few moreLocal/Global R_MIPS_GOT related fixups and
...
make the addend fixup code a bit more generic
Patch by Jack Carter.
llvm-svn: 145998
2011-12-07 00:28:57 +00:00
47c24c2084
ARM: Parameterize the immediate operand type for NEON VSHLL.
...
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
llvm-svn: 145994
2011-12-07 00:02:17 +00:00
cc6bfa8e79
Revert r145971: "Use conservative size estimate for tBR_JTr."
...
This caused more offset errors.
llvm-svn: 145980
2011-12-06 22:41:31 +00:00
67a70c995a
Explicitly check for the different SUB instructions.
...
llvm-svn: 145976
2011-12-06 22:14:27 +00:00
2a81dd4a3c
First chunk of MachineInstr bundle support.
...
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
llvm-svn: 145975
2011-12-06 22:12:01 +00:00
33fe130e12
Use conservative size estimate for tBR_JTr.
...
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
llvm-svn: 145971
2011-12-06 21:55:39 +00:00
2fa7448f31
Remove alignment from deserted constant islands.
...
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
llvm-svn: 145970
2011-12-06 21:55:35 +00:00
5a173cd367
Encode the total stack if there isn't a frame.
...
llvm-svn: 145969
2011-12-06 21:34:01 +00:00
a73c0c99ea
* Add a macro to remove a magic number.
...
* Rename variables to reflect what they're actually used for.
llvm-svn: 145968
2011-12-06 21:23:42 +00:00
bde7f8ffe2
add RESTORE_CR and support CR unspills
...
llvm-svn: 145961
2011-12-06 20:55:36 +00:00
4ec02b02ac
remove old FIXME
...
llvm-svn: 145960
2011-12-06 20:52:56 +00:00
87571b6392
Check the correct value for small stack sizes. Also modify some comments.
...
llvm-svn: 145954
2011-12-06 19:16:17 +00:00
a4e87944a8
For a small sized stack, we encode that value directly with no "stack adjust" value.
...
llvm-svn: 145952
2011-12-06 19:09:06 +00:00
04424665c3
PTX: Continue to fix up the register mess.
...
llvm-svn: 145947
2011-12-06 17:39:48 +00:00
3063ac87aa
PTX: Encode registers as unsigned values in the MC asm printer instead of using external symbols
...
llvm-svn: 145946
2011-12-06 17:39:46 +00:00
83320e03e6
Add X86ISD::HADD/HSUB to getTargetNodeName
...
llvm-svn: 145929
2011-12-06 09:31:36 +00:00
6572e0f203
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
...
llvm-svn: 145927
2011-12-06 09:04:59 +00:00
8d4ba198d6
Merge floating point and integer UNPCK X86ISD node types.
...
llvm-svn: 145926
2011-12-06 08:21:25 +00:00
3cb802c775
Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.
...
llvm-svn: 145924
2011-12-06 05:31:16 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
bf41eb3a98
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
...
llvm-svn: 145921
2011-12-06 04:59:07 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
0c24d8a406
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
...
llvm-svn: 145912
2011-12-06 03:34:48 +00:00
1b1a122b4c
Add register HWR29 numbering. Patch by Jack Carter
...
llvm-svn: 145910
2011-12-06 03:34:36 +00:00
4e87e850a2
Add a comment.
...
llvm-svn: 145896
2011-12-06 01:57:48 +00:00
425e180ce8
Tidy up value checking.
...
llvm-svn: 145895
2011-12-06 01:53:17 +00:00
d3002490bf
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
...
llvm-svn: 145894
2011-12-06 01:48:32 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
2e05db2fa0
Align ARM constant pool islands via their basic block.
...
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
10e1252269
Use logarithmic units for basic block alignment.
...
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.
CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.
Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.
Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.
llvm-svn: 145889
2011-12-06 01:26:19 +00:00
f7cef7ecad
The compact encoding of the registers are 3-bits each. Make sure we shift the
...
value over that much.
llvm-svn: 145888
2011-12-06 01:26:14 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
...
rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
2608157f79
Use an existing function.
...
llvm-svn: 145883
2011-12-06 00:51:12 +00:00
25b63fa117
Move target-specific logic out of generic MCAssembler.
...
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
llvm-svn: 145881
2011-12-06 00:47:03 +00:00
34a7c6dfd7
Simple branch relaxation for Thumb2 Bcc instructions.
...
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
llvm-svn: 145871
2011-12-05 23:45:46 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
...
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
e489babf9b
Thumb2 prefer ADD register encoding T2 to T3 when possible.
...
rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
...
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
...
them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
...
O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
...
Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
9e90c5cde3
Fix previous commit. Oops.
...
llvm-svn: 145844
2011-12-05 20:12:26 +00:00
2b37e4fc80
Tidy up. No functional change.
...
llvm-svn: 145843
2011-12-05 20:09:44 +00:00
0a978ef715
ARM assmebler parsing for two-operand VMUL instructions.
...
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
...
llvm-svn: 145819
2011-12-05 17:55:17 +00:00
72a26e8b8d
don't include CR bit subregs in callee-saved list
...
llvm-svn: 145818
2011-12-05 17:55:12 +00:00
b544019a60
add register pressure for CR regs
...
llvm-svn: 145816
2011-12-05 17:54:17 +00:00
51bec1a37a
Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions.
...
llvm-svn: 145804
2011-12-05 07:27:14 +00:00
6a55b1dd9f
Clean up and optimizations to the X86 shuffle lowering code. No functional change.
...
llvm-svn: 145803
2011-12-05 06:56:46 +00:00
80381f6cbf
Fix 80-column issues.
...
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
...
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
...
AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
006e43bcc0
Check for stack space more intelligently.
...
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
165ca1d4ba
Fix a bug in the x86-32 code generated for segmented stacks.
...
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
llvm-svn: 145765
2011-12-03 09:21:07 +00:00
8fd1254a0a
Creating multiple JITs on X86 in multiple threads causes multiple writes (of
...
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.
llvm-svn: 145745
2011-12-03 02:45:50 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
...
llvm-svn: 145726
2011-12-02 23:34:39 +00:00
2635f54cb6
ARM VEXT tighten up operand classes a bit.
...
llvm-svn: 145722
2011-12-02 22:57:57 +00:00
eb53822f5a
ARM VST1 single lane assembly parsing.
...
llvm-svn: 145718
2011-12-02 22:34:51 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
dda976b804
ARM VLD1 single lane assembly parsing.
...
llvm-svn: 145712
2011-12-02 22:01:52 +00:00
81c9003695
ARM encoder method needs the physical register number, not the enum.
...
llvm-svn: 145711
2011-12-02 22:01:25 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
1280eb1d06
Add XOP feature flag.
...
llvm-svn: 145682
2011-12-02 15:14:37 +00:00
b67440367f
Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions
...
llvm-svn: 145681
2011-12-02 08:18:41 +00:00
abeb79eee3
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
...
llvm-svn: 145680
2011-12-02 07:16:01 +00:00
f9ce7b60ef
remove unneeded FIXME comment
...
llvm-svn: 145679
2011-12-02 04:58:17 +00:00
58ca360081
update PPC 940 hazard rec. to function in postRA mode
...
llvm-svn: 145676
2011-12-02 04:58:02 +00:00
04945c42c6
ARM start parsing VLD1 single lane instructions.
...
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
f60485c4cf
Dummy commit to check commit access.
...
llvm-svn: 145619
2011-12-01 19:15:08 +00:00
676c093758
Add missing functions.
...
llvm-svn: 145608
2011-12-01 18:26:19 +00:00
10fe1fe39e
Add a few more functions to TargetLibraryInfo. More of rdar://10500969.
...
llvm-svn: 145596
2011-12-01 17:54:37 +00:00
9da7f305a4
For 64-bit the rest of the general regs are ok for the q constraint. Make
...
sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
2011-12-01 08:12:41 +00:00
d61887dd0a
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
...
llvm-svn: 145573
2011-12-01 04:49:21 +00:00
c1870b2633
Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
...
llvm-svn: 145553
2011-12-01 01:43:47 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
...
remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
23c30b90e3
Remove unused variable
...
llvm-svn: 145517
2011-11-30 19:53:11 +00:00
a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
...
llvm-svn: 145510
2011-11-30 19:35:44 +00:00
738da252ab
Add a few functions to TargetLibraryInfo.
...
llvm-svn: 145508
2011-11-30 19:19:00 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
...
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
5feb3dab79
X86: Turns out bulldozer also supports sse42 and lzcnt.
...
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.
llvm-svn: 145494
2011-11-30 15:48:16 +00:00
981f32327d
X86: Add subtargets for AMD's bulldozer.
...
llvm-svn: 145493
2011-11-30 15:27:46 +00:00
96923cc2bb
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
...
llvm-svn: 145488
2011-11-30 10:13:37 +00:00
c4977ba413
Add instruction selection support for AVX2 horizontal add/sub instructions.
...
llvm-svn: 145487
2011-11-30 09:10:50 +00:00
0a672eaf9e
Merge VPERM2F128/VPERM2I128 ISD node types.
...
llvm-svn: 145485
2011-11-30 07:47:51 +00:00
bafd224c8b
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
...
llvm-svn: 145483
2011-11-30 06:25:25 +00:00
abba0947db
Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional
...
change intended.
llvm-svn: 145468
2011-11-30 01:51:49 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
...
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
82e1bd8e94
Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
...
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410
llvm-svn: 145460
2011-11-29 23:57:10 +00:00
182b6a077e
Tidy up a bit.
...
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
ae672f8118
Add comment.
...
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
e1154eef0b
ARM parsing aliases for data-size suffices on VST1.
...
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
dc25f9f38a
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
...
tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
llvm-svn: 145451
2011-11-29 23:08:41 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
648e48d02e
Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.
...
llvm-svn: 145448
2011-11-29 22:48:34 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
...
llvm-svn: 145442
2011-11-29 22:38:04 +00:00
bde32d36bb
Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
...
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.
This also makes the AVX variants redundant.
llvm-svn: 145440
2011-11-29 22:27:25 +00:00
312b97c267
comment.
...
llvm-svn: 145422
2011-11-29 19:33:49 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
...
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
de3a2118db
MC/X86/COFF: Allow quotes in names when targeting MS/Windows,
...
as MC is the only assembler we support.
This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.
llvm-svn: 145409
2011-11-29 18:00:06 +00:00
7a81dea516
Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.
...
Added a test.
Thanks Bruno for reviewing the patch.
llvm-svn: 145403
2011-11-29 15:00:45 +00:00
1d63ae3731
Fix shuffle decoding for memory forms for (V)SHUFPS/D.
...
llvm-svn: 145392
2011-11-29 07:58:09 +00:00
c16db840be
Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD.
...
llvm-svn: 145390
2011-11-29 07:49:05 +00:00
12b72def4e
Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled.
...
llvm-svn: 145376
2011-11-29 05:37:58 +00:00
897a7d4b9c
Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2.
...
llvm-svn: 145370
2011-11-29 03:57:34 +00:00
ae9132207f
Better fix for ARM MOVT relocation encoding of thumb bit.
...
Replaces r145318 with a more targetted fix for the relocation handling.
llvm-svn: 145346
2011-11-29 01:15:25 +00:00
aa93ceb164
Add missing avx pattern.
...
llvm-svn: 145272
2011-11-28 20:27:23 +00:00
12330650f8
Silence wrong warnings from GCC about variables possibly being used
...
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
llvm-svn: 145239
2011-11-28 10:31:27 +00:00
818a983e93
Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar.
...
llvm-svn: 145238
2011-11-28 10:14:51 +00:00
b0456936da
Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled.
...
llvm-svn: 145218
2011-11-28 01:14:24 +00:00
79ee88a511
Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the code was similar for both.
...
llvm-svn: 145199
2011-11-27 21:41:12 +00:00
97b3da5433
Add several new instructions supported by the latest MicroBlaze.
...
These instructions are not generated by the backend yet, this will come in a later commit.
llvm-svn: 145161
2011-11-27 05:16:58 +00:00
d2e2e1782f
Optimize comparison against 0 in conditional instructions.
...
Fix a couple of 80-column violations.
llvm-svn: 145159
2011-11-27 01:36:20 +00:00
7ba71be392
Move code into anonymous namespaces.
...
llvm-svn: 145154
2011-11-26 23:01:57 +00:00
51280d565b
Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created.
...
llvm-svn: 145153
2011-11-26 22:55:48 +00:00
69d5040485
Rename a couple of options and fix some simple typos.
...
llvm-svn: 145152
2011-11-26 21:50:38 +00:00
7704bd7ac3
Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type.
...
llvm-svn: 145148
2011-11-26 20:47:44 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
...
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
989eaf6e3f
ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
...
llvm-svn: 145129
2011-11-25 09:19:57 +00:00
d65a444478
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
...
llvm-svn: 145126
2011-11-24 22:57:10 +00:00
d26466748b
Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish.
...
llvm-svn: 145125
2011-11-24 22:20:08 +00:00
651db37352
X86: alias cqo to cqto.
...
llvm-svn: 145121
2011-11-24 12:02:46 +00:00
049e9e4d22
This patch makes the following changes necessary for MIPS' direct code emission.
...
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).
llvm-svn: 145113
2011-11-23 22:19:28 +00:00
f5ddf13f79
This patch addresses gp relative fixups/relocations for jump tables.
...
llvm-svn: 145112
2011-11-23 22:18:04 +00:00
ebcb451874
X86: Use btq for bit tests if the immediate can't be encoded in 32 bits.
...
Before:
movabsq $4294967296, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
testq %rax, %rdi ## encoding: [0x48,0x85,0xf8]
jne LBB0_2 ## encoding: [0x75,A]
After:
btq $32, %rdi ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
jb LBB0_2 ## encoding: [0x72,A]
btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.
llvm-svn: 145103
2011-11-23 13:54:17 +00:00
779ba6d7b7
I added several lines in X86 code generator that allow to choose
...
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.
The patch was reviewed by Bruno.
llvm-svn: 145099
2011-11-23 10:23:16 +00:00
02845410f9
Fix PR11422.
...
This was a bug in keeping track of the available domains when merging
domain values.
The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.
Also add an assertion to catch future attempts at emitting AVX2
instructions.
llvm-svn: 145096
2011-11-23 04:03:08 +00:00
6f0ae783fe
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
...
llvm-svn: 145065
2011-11-22 16:21:04 +00:00
83c4592619
More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries.
...
llvm-svn: 145063
2011-11-22 14:27:57 +00:00
ccb7097509
Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms.
...
llvm-svn: 145055
2011-11-22 01:57:35 +00:00
f563977795
Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX.
...
llvm-svn: 145053
2011-11-22 00:44:41 +00:00
6270d072c5
Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.
...
llvm-svn: 145028
2011-11-21 08:26:50 +00:00
669199ca94
Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled.
...
llvm-svn: 145026
2011-11-21 06:57:39 +00:00
a065238c6e
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.
...
llvm-svn: 145022
2011-11-21 01:12:36 +00:00
e79761df73
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
...
llvm-svn: 145005
2011-11-20 00:12:05 +00:00
a3a6583694
Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
...
llvm-svn: 145004
2011-11-19 22:34:59 +00:00
bac86038ac
Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns.
...
llvm-svn: 145003
2011-11-19 21:01:54 +00:00
3af6ae089f
Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
...
llvm-svn: 144999
2011-11-19 17:46:46 +00:00
f984efbfce
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
...
llvm-svn: 144989
2011-11-19 09:02:40 +00:00
81390be00f
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
...
llvm-svn: 144988
2011-11-19 07:33:10 +00:00
de6b73bb4d
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
...
llvm-svn: 144987
2011-11-19 07:07:26 +00:00
66e2b5a61e
Remove unused parameters from the AVX maskmov classes.
...
llvm-svn: 144985
2011-11-19 04:49:22 +00:00
1ec141d0f9
Add AVX2 vpbroadcast support
...
llvm-svn: 144967
2011-11-18 02:49:55 +00:00
ee93ff736a
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
...
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
0eff3e5c21
Add TODO comment.
...
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
f41e1d0246
Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.
...
llvm-svn: 144896
2011-11-17 07:49:38 +00:00
15b2498e88
Dead code.
...
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
f17b600577
Remove seemingly unnecessary duplicate VROUND definitions.
...
llvm-svn: 144885
2011-11-17 07:04:00 +00:00
489c0ff4a4
Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
...
names for fwrite and fputs.
Fixes <rdar://problem/9815881>.
llvm-svn: 144876
2011-11-17 01:27:36 +00:00
ce619ddfc5
Don't unconditionally set the kill flag.
...
rdar://10456186
llvm-svn: 144872
2011-11-17 01:16:53 +00:00
20439a42b0
Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
...
llvm-svn: 144867
2011-11-17 00:21:52 +00:00
d3f02cbce9
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
b31abde0f3
Lower 64-bit constant pool node.
...
llvm-svn: 144849
2011-11-16 22:44:38 +00:00
eb42071721
Lower 64-bit block address.
...
llvm-svn: 144847
2011-11-16 22:42:10 +00:00
7ccdb7c0ae
Fix encoding of NOP used for padding in ARM mode .align.
...
llvm-svn: 144842
2011-11-16 22:40:25 +00:00
7b8547c4d0
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
...
nodes.
llvm-svn: 144841
2011-11-16 22:39:56 +00:00
6d617ceca2
64-bit jump register instruction.
...
llvm-svn: 144840
2011-11-16 22:36:01 +00:00
011538dc79
Another missing X86ISD::MOVLPD pattern. rdar://10450317
...
llvm-svn: 144839
2011-11-16 22:24:44 +00:00
bfe5c5c968
ARM assembly parsing for shifted register operands for MOV instruction.
...
llvm-svn: 144837
2011-11-16 21:50:05 +00:00
01e0439240
Clean up debug printing of ARM shifted operands.
...
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
3127ab6d8f
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
...
llvm-svn: 144814
2011-11-16 19:12:24 +00:00
1a2f9ee3c8
ARM assembly parsing for RRX mnemonic.
...
rdar://9704684
llvm-svn: 144812
2011-11-16 19:05:59 +00:00
48784ed5b7
Added missing comment about new custom lowering of DEC64
...
llvm-svn: 144811
2011-11-16 19:03:23 +00:00
80979b6ea6
Check to make sure we can select the instruction before trying to put the
...
operands into a register. Otherwise, we may materialize dead code.
llvm-svn: 144805
2011-11-16 18:39:44 +00:00
abcac56869
ARM mode aliases for bitwise instructions w/ register operands.
...
rdar://9704684
llvm-svn: 144803
2011-11-16 18:31:45 +00:00
0ca7ce389c
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
...
llvm-svn: 144798
2011-11-16 17:09:59 +00:00
b345060a85
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
...
llvm-svn: 144794
2011-11-16 09:18:28 +00:00
ecb2908bf9
Sink codegen optimization level into MCCodeGenInfo along side relocation model
...
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
2011-11-16 08:38:26 +00:00
3ed7d9ee5a
Fix the execution domain on a bunch of SSE/AVX instructions.
...
llvm-svn: 144784
2011-11-16 07:30:46 +00:00
f6d1728d8f
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
...
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal. The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block. The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op. The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.
Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.
llvm-svn: 144781
2011-11-16 07:11:57 +00:00
07d8b5e2c9
Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.
...
llvm-svn: 144777
2011-11-16 05:02:04 +00:00
af13d767a2
Add FIXME comment.
...
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
653183fd5c
Enable -widen-vmovs by default.
...
This will widen 32-bit register vmov instructions to 64-bit when
possible. The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.
The copies are only widened if they are marked as clobbering the whole
D-register.
llvm-svn: 144734
2011-11-15 23:53:18 +00:00
e891fe8d6c
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
003cea6011
ARM assembly parsing for data type suffices on NEON VMOV aliases.
...
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
37010002f2
AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
...
llvm-svn: 144720
2011-11-15 22:50:37 +00:00
75fb4abcdc
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
a01033709f
ARM VFP assembly parsing for VADD and VSUB two-operand forms.
...
llvm-svn: 144710
2011-11-15 22:15:10 +00:00
8279c1828f
ARM accept an immediate offset in memory operands w/o the '#'.
...
llvm-svn: 144709
2011-11-15 22:14:41 +00:00
7c7ba1baa1
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
...
by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
llvm-svn: 144705
2011-11-15 21:57:53 +00:00
8d579230c6
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
...
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
llvm-svn: 144701
2011-11-15 21:45:55 +00:00
84f0ba5747
ARM size suffix on VFP single-precision 'vmov' is optional.
...
rdar://10435114
llvm-svn: 144698
2011-11-15 21:18:35 +00:00
a92a5d8548
Fix typo.
...
llvm-svn: 144695
2011-11-15 21:01:30 +00:00
131b45e632
ARM alternate size suffices for VTRN instructions.
...
rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
05060f0748
Fix a misplaced paren bug.
...
llvm-svn: 144692
2011-11-15 20:30:41 +00:00
5803f6d5a2
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
c5b1bc561e
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
72dfd20aba
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
efa7e95d06
Thumb2 two-operand 'mul' instruction wide encoding parsing.
...
rdar://10449724
llvm-svn: 144684
2011-11-15 19:55:16 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
...
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
6efa7b9852
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
6ee8fc88c7
Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
...
registers and instructions when ABI is N64.
llvm-svn: 144666
2011-11-15 18:53:55 +00:00
494913270e
Set nomacro before emitting the sequence of instructions that set global pointer
...
register.
llvm-svn: 144665
2011-11-15 18:44:44 +00:00
66a14c0650
Simplify function PassByValArg64.
...
llvm-svn: 144664
2011-11-15 18:42:25 +00:00
b7796ae938
Delete files.
...
llvm-svn: 144655
2011-11-15 18:22:48 +00:00
1c0590c5da
Remove MipsMCSymbolRefExpr.
...
llvm-svn: 144654
2011-11-15 18:20:08 +00:00
2aabaa704a
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144650
2011-11-15 17:49:59 +00:00
e5cbd3c3fb
Fix typo in comment.
...
llvm-svn: 144633
2011-11-15 07:50:05 +00:00
465101bb0e
Make use of MachinePointerInfo::getFixedStack. This removes all mention
...
of PseudoSourceValue from lib/Target/.
llvm-svn: 144632
2011-11-15 07:34:52 +00:00
0745e645e0
Remove some unnecessary includes of PseudoSourceValue.h.
...
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
649d1c5eec
Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.
...
llvm-svn: 144629
2011-11-15 06:39:01 +00:00
05baa85f58
Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.
...
llvm-svn: 144622
2011-11-15 05:55:35 +00:00
7ca4b6eb5c
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
...
integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
29cdcda80d
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
...
rdar://10435076
llvm-svn: 144606
2011-11-15 01:46:57 +00:00
f8ad336bc4
Break false dependencies before partial register updates.
...
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.
The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.
The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.
llvm-svn: 144602
2011-11-15 01:15:30 +00:00
a498af2b1d
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
72838a0345
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
750de7a399
Add explanatory comment.
...
llvm-svn: 144589
2011-11-14 23:21:09 +00:00
9c2d9d597b
Split out the plain '.{8|16|32|64}' suffix handling.
...
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
llvm-svn: 144588
2011-11-14 23:20:14 +00:00
3d6c0e0bb2
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
...
rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
057b6d3476
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
...
violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
llvm-svn: 144585
2011-11-14 23:04:09 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
ab7223e99a
Add support for inlining small memcpys.
...
rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
45110fdf8d
Fix a performance regression from r144565. Positive offsets were being lowered
...
into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
7996b15724
ARM assembly parsing type suffix options for VLDR/VSTR.
...
rdar://10435076
llvm-svn: 144575
2011-11-14 22:28:39 +00:00
fb13d32b3f
Add a missing pattern for X86ISD::MOVLPD. rdar://10436044
...
llvm-svn: 144566
2011-11-14 20:35:52 +00:00
adfd200bcb
Add support for Thumb load/stores with negative offsets.
...
rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
319904cc7e
Unbreak Release builds.
...
llvm-svn: 144560
2011-11-14 19:51:48 +00:00
890e02e854
Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered
...
Constant idx case is still done in tablegen but other cases are then expanded
Fixes <rdar://problem/10435460>
llvm-svn: 144557
2011-11-14 19:38:42 +00:00
f93b3f46f8
32-to-64-bit extended load.
...
llvm-svn: 144554
2011-11-14 19:06:14 +00:00
0b8bc00424
AnalyzeCallOperands function for N32/64.
...
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.
llvm-svn: 144553
2011-11-14 19:02:54 +00:00
52359363f2
Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.
...
llvm-svn: 144552
2011-11-14 19:01:09 +00:00
33a519021c
PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations.
...
llvm-svn: 144551
2011-11-14 18:58:20 +00:00
d673cfe027
Remove variable that keeps the size of area used to save byval or variable
...
argument registers on the callee's stack frame, along with functions that set
and get it.
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.
llvm-svn: 144549
2011-11-14 18:56:20 +00:00
ee201faeac
Tidy up. 80 column.
...
llvm-svn: 144538
2011-11-14 17:52:47 +00:00
182b00a2e0
Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions.
...
llvm-svn: 144525
2011-11-14 08:07:55 +00:00
a331515c82
Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway.
...
llvm-svn: 144522
2011-11-14 06:46:21 +00:00
2a1df883d0
Add support for ARM halfword load/stores and signed byte loads with negative
...
offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
b8bcb473e2
Add BLSI, BLSMSK, and BLSR to getTargetNodeName.
...
llvm-svn: 144502
2011-11-13 17:31:07 +00:00
1198d894d0
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
...
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
a476e391f1
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
...
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
5196efdf36
Fix comments.
...
llvm-svn: 144490
2011-11-13 04:25:02 +00:00
c8cfd3a8fb
Add support for emitting both signed- and zero-extend loads. Fix
...
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
3dc75f9e3b
Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
...
llvm-svn: 144457
2011-11-12 09:58:49 +00:00
77733535eb
Fix typo.
...
llvm-svn: 144453
2011-11-12 02:38:12 +00:00
19891f843c
Implement Mips64's handling of byval arguments in LowerCall.
...
llvm-svn: 144452
2011-11-12 02:34:50 +00:00
fb9bae34da
Implement Mips64's handling of byval arguments in LowerFormalArguments.
...
llvm-svn: 144449
2011-11-12 02:29:58 +00:00
5ed07c03f4
64-bit arbitrary immediate pattern.
...
llvm-svn: 144448
2011-11-12 02:25:00 +00:00
202f6400ef
Function for handling byval arguments.
...
llvm-svn: 144447
2011-11-12 02:20:46 +00:00
52823cc91c
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
...
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
3a3d8e82bc
ARM refactor simple immediate asm operand render methods.
...
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
llvm-svn: 144439
2011-11-12 00:58:43 +00:00
8ca13deecf
Re-apply 144430, this time with the associated isel and disassmbler bits.
...
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
155763b630
Oops. Missed the isel half of this. revert while I sort that out.
...
llvm-svn: 144431
2011-11-11 23:51:31 +00:00
28f721a2b4
ARM assembly parsing for VST1 two-register encoding.
...
llvm-svn: 144430
2011-11-11 23:45:47 +00:00
609d113874
ARM optional size suffix for VLDR/VSTR syntax.
...
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
a7ebc5617d
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
...
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
7f89f4c91c
CMake: Fix CMake build for new Mips tblgen file.
...
llvm-svn: 144423
2011-11-11 23:12:56 +00:00
12952fef71
ARM vldm and vstm VFP instructions can take a data type suffix.
...
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
llvm-svn: 144422
2011-11-11 23:08:10 +00:00
b8a9c43d07
Target/LLVMBuild: Order components alphabetically.
...
llvm-svn: 144415
2011-11-11 22:59:16 +00:00
c85e3ff334
Mips MC object code emission improvements:
...
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
b68eeb3852
Nuke no longer accurate comment.
...
llvm-svn: 144411
2011-11-11 22:30:06 +00:00
28c1d18434
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
...
Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
85a2343b01
ARM allow Q registers in vldm/vstm register lists.
...
rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
089cc53232
allow non-device function calls in PTX when natively handling device-side printf
...
llvm-svn: 144388
2011-11-11 14:45:12 +00:00
80cd65bfa9
add rules in tabgen for PTX COPY_ADDRESS of frameindex
...
llvm-svn: 144387
2011-11-11 14:45:06 +00:00
48b5bbffed
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
...
llvm-svn: 144384
2011-11-11 12:39:41 +00:00
1cc805c058
Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler.
...
llvm-svn: 144383
2011-11-11 12:39:35 +00:00
ea28a34c43
Add lowering for AVX2 shift instructions.
...
llvm-svn: 144380
2011-11-11 07:39:23 +00:00
e19b0a9eb8
Rename variables to avoid confusion. No functionallity change intended.
...
llvm-svn: 144377
2011-11-11 06:27:41 +00:00
7ddd63ce4e
Add support for using immediates with select instructions.
...
rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
4a63d1c0f0
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
...
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
llvm-svn: 144373
2011-11-11 04:18:21 +00:00
21cbc25bbb
64-bit atomic instructions.
...
llvm-svn: 144372
2011-11-11 04:14:30 +00:00
9189d7127f
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
...
llvm-svn: 144371
2011-11-11 04:11:56 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
...
llvm-svn: 144370
2011-11-11 04:06:38 +00:00
0009dc2088
64-bit versions of jal, jalr and bal.
...
llvm-svn: 144368
2011-11-11 04:03:54 +00:00
11521863da
Emit Mips64's sequence of instructions that set global register in prologue.
...
llvm-svn: 144367
2011-11-11 04:00:29 +00:00
aa1f4c7986
Fix printing of MCSymbolRegExpr. Needs three closing parentheses for
...
VK_Mips_GPOFF_HI/LO.
llvm-svn: 144366
2011-11-11 03:58:36 +00:00
c4a001478c
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
...
llvm-svn: 144361
2011-11-11 03:16:38 +00:00
023ede5649
When loading a value, treat an i1 as an i8.
...
llvm-svn: 144356
2011-11-11 02:38:59 +00:00
8df8204554
If we have to reset the calculation of the compact encoding, then also reset the
...
"saved register" index.
<rdar://problem/10430076>
llvm-svn: 144350
2011-11-11 00:59:14 +00:00
2a3503e061
Add support for using MVN to materialize negative constants.
...
rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
6d617b48c7
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
...
llvm-svn: 144344
2011-11-11 00:23:56 +00:00
d9a9be269c
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
...
rdar://10429490
llvm-svn: 144338
2011-11-10 23:58:34 +00:00
afad053141
ARM let processInstruction() tranforms chain.
...
llvm-svn: 144337
2011-11-10 23:42:14 +00:00
9bded9dc24
Thumb2 parsing for push/pop w/ hi registers in the reglist.
...
rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
a113eb0205
Thumb1 diagnostics for reglist on PUSH/POP fix.
...
Was not checking the first register in the register list.
llvm-svn: 144329
2011-11-10 23:01:27 +00:00
5a5ce63742
Thumb MUL assembly parsing for 3-operand form.
...
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
085f6f2af1
build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler
...
that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.
llvm-svn: 144321
2011-11-10 22:00:37 +00:00
d1762e00e2
When in ARM mode, LDRH/STRH require special handling of negative offsets.
...
For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
42ba6286b6
ARM .thumb_func directive for quoted symbol names.
...
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
llvm-svn: 144315
2011-11-10 20:48:53 +00:00
c14871cc67
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
61db5a59f7
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
b538095011
build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for
...
consistency with other targets.
llvm-svn: 144292
2011-11-10 15:35:14 +00:00
0a2f797dec
AVX2: Add variable shift from memory.
...
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.
llvm-svn: 144266
2011-11-10 06:54:20 +00:00
3fbd094ad9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
807c6e4e5f
build/Make & CMake: Pass the appropriate --native-target and --enable-targets
...
options to llvm-build, so the all-targets etc. components are defined properly.
llvm-svn: 144255
2011-11-10 01:16:48 +00:00
233c9304a8
llvm-build: Add --native-target and --enable-targets options, and add logic to
...
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
1c04e14447
llvm-build: Change CBackend and CppBackend to not use library_name. This will
...
change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).
llvm-svn: 144251
2011-11-10 00:49:55 +00:00
82219ad4dc
llvm-build: Add an explicit component type to represent targets.
...
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
a48485a37f
Tidy up.
...
llvm-svn: 144244
2011-11-10 00:02:33 +00:00
25bc090170
Thumb2 assembly parsing STMDB w/ optional .w suffix.
...
rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
2d4055b683
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
...
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
2f27fab6ed
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
...
rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
1938482bfa
AVX2: Add patterns for variable shift operations
...
llvm-svn: 144212
2011-11-09 21:22:13 +00:00
2f70bcdb94
Remove unnecessary include.
...
llvm-svn: 144211
2011-11-09 21:11:02 +00:00
79135d844d
Add AVX2 support for vselect of v32i8
...
llvm-svn: 144187
2011-11-09 13:21:28 +00:00
f87a2bef51
Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions.
...
llvm-svn: 144179
2011-11-09 09:37:21 +00:00
c9eb09d3b8
Add instruction selection for AVX2 integer comparisons.
...
llvm-svn: 144176
2011-11-09 08:06:13 +00:00
8c8a431057
Add AVX2 instruction lowering for add, sub, and mul.
...
llvm-svn: 144174
2011-11-09 07:28:55 +00:00
595d419427
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
94307f6ba6
Hide cpu name checking in ARMSubtarget.
...
llvm-svn: 144154
2011-11-09 01:57:03 +00:00
d5edb3847a
Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts.
...
Patch by Jack Carter.
llvm-svn: 144139
2011-11-08 22:26:47 +00:00
c3770ac687
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
...
llvm-svn: 144123
2011-11-08 21:21:09 +00:00
0439cfc41f
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
...
No functional change intended.
llvm-svn: 144122
2011-11-08 21:12:00 +00:00
b85fcd07df
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
...
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
llvm-svn: 144102
2011-11-08 18:56:23 +00:00
82cd9e81fc
Added invariant field to the DAG.getLoad method and changed all calls.
...
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
71133fe9c6
This patch handles unaligned loads and stores in Mips JIT. Mips backend
...
implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).
Patch by Petar Jovanovic and Sasa Stankovic.
llvm-svn: 144081
2011-11-08 12:47:11 +00:00
05aa1a42c3
PPCInstrInfo.cpp: Fix one "unused" warning.
...
llvm-svn: 144071
2011-11-08 04:00:07 +00:00
6f84fed675
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
...
llvm-svn: 144057
2011-11-08 01:43:53 +00:00
91b56e0390
Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222
...
llvm-svn: 144052
2011-11-08 00:31:58 +00:00
5de1bea5c9
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
...
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
fa75530ff0
Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well.
...
llvm-svn: 144021
2011-11-07 21:43:40 +00:00
2216f73676
Various Mips64 floating point instruction patterns.
...
llvm-svn: 144019
2011-11-07 21:38:58 +00:00
b2d37760a2
Add definition of the base class for floating point comparison instructions
...
and add Mips64's version too.
llvm-svn: 144018
2011-11-07 21:37:33 +00:00
81c14002dc
Add code needed for copying between 64-bit integer and floating pointer
...
registers.
llvm-svn: 144017
2011-11-07 21:35:45 +00:00
1537e297e1
Add definitions of 64-bit instructions which move data between integer and
...
floating pointer registers.
llvm-svn: 144016
2011-11-07 21:32:58 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
...
As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
03d73e47b4
Simplify code. No functionality change.
...
llvm-svn: 144012
2011-11-07 21:00:43 +00:00
0241308954
Expand V_SET0 to xorps by default.
...
The xorps instruction is smaller than pxor, so prefer that encoding.
The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.
llvm-svn: 143996
2011-11-07 19:15:58 +00:00
2b8d1f163f
Add definition of 64-bit load upper immediate.
...
llvm-svn: 143994
2011-11-07 19:10:49 +00:00
2f4480046b
Include RegSaveAreaSize in the computation of stack size.
...
llvm-svn: 143993
2011-11-07 19:07:35 +00:00
7bcecd486f
Define functions that get or set the size of area on callee's stack frame which
...
is used to save va_arg or byval arguments passed in registers.
llvm-svn: 143992
2011-11-07 19:06:10 +00:00
d9c2e46cfb
Use array_lengthof to compute the number of iterations of a loop.
...
llvm-svn: 143991
2011-11-07 19:03:40 +00:00
cf7e5b0976
Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted
...
when shift amount is larger than 32.
llvm-svn: 143990
2011-11-07 19:01:49 +00:00
770f0646db
Make the type of shift amount i32 in order to reduce the number of shift
...
instruction definitions.
llvm-svn: 143989
2011-11-07 18:59:49 +00:00
d5c1329078
Add 64-bit to 32-bit trunc pattern.
...
llvm-svn: 143988
2011-11-07 18:57:41 +00:00
a6d409d543
Add AVX2 variable shift instructions and intrinsics.
...
llvm-svn: 143915
2011-11-07 08:26:24 +00:00
ff39be0afc
Add AVX2 VPMOVMASK instructions and intrinsics.
...
llvm-svn: 143904
2011-11-07 03:20:35 +00:00
e122dcbf4a
Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects.
...
llvm-svn: 143902
2011-11-07 02:00:04 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
...
llvm-svn: 143895
2011-11-06 23:04:08 +00:00
20baffb257
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
...
llvm-svn: 143891
2011-11-06 20:37:06 +00:00
05d1cb98e7
Add more AVX2 instructions and intrinsics.
...
llvm-svn: 143861
2011-11-06 06:12:20 +00:00
d0191a53c9
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
...
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
f3da529028
Add more PRI.64 macros for MSVC and use them throughout the codebase.
...
llvm-svn: 143799
2011-11-05 08:57:40 +00:00
f0055f61fb
Allow i1 to be promoted to i32 for ARM APCS calling convention.
...
llvm-svn: 143755
2011-11-05 00:02:56 +00:00
8f249600e7
Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes.
...
I'm going to wait for any review comments and perform some additional testing before turning this on by default.
llvm-svn: 143750
2011-11-04 23:46:11 +00:00
5b8fdd7b62
Cannot create a result register for non-legal types.
...
llvm-svn: 143749
2011-11-04 23:45:39 +00:00
e8b8b77307
When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
...
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend. This prevents us from materializing things
such as 'true' (i.e., i1 1).
llvm-svn: 143743
2011-11-04 23:09:49 +00:00
67f96887aa
Enable support for materializing i1, i8, and i16 integers via move immediate.
...
llvm-svn: 143739
2011-11-04 22:29:00 +00:00
4a2eab0dac
build/cmake: Coalesce the configuration time header include fragment generation
...
for target definitions.
llvm-svn: 143731
2011-11-04 19:04:42 +00:00
4a9c6426ff
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
...
added a layer of indirection with no value (not even conciseness).
llvm-svn: 143727
2011-11-04 19:04:23 +00:00
5b693c2fa6
Add missing argument for atomic instructions in c++ backend. PR11268, part 2.
...
llvm-svn: 143712
2011-11-04 17:29:35 +00:00
caba032f48
Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions
...
llvm-svn: 143683
2011-11-04 06:59:49 +00:00
1ddeb167e8
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen.
...
llvm-svn: 143675
2011-11-04 01:48:58 +00:00
8a98ec4d4b
Indentation.
...
llvm-svn: 143670
2011-11-04 00:58:10 +00:00
f3e73ad5da
Add fast-isel support for returning i1, i8, and i16.
...
llvm-svn: 143669
2011-11-04 00:50:21 +00:00
198b7ffc11
Reapply r143206, with fixes. Disallow physical register lifetimes
...
across calls, and only check for nested dependences on the special
call-sequence-resource register.
llvm-svn: 143660
2011-11-03 21:49:52 +00:00
b68515c232
fixed global array handling for ptx to use the correct bit widths
...
llvm-svn: 143640
2011-11-03 19:24:46 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
...
llvm-svn: 143634
2011-11-03 18:53:17 +00:00
0e7cbbabea
Add new X86 AVX2 VBROADCAST instructions.
...
llvm-svn: 143612
2011-11-03 07:35:53 +00:00
bf5f4bec1a
Add support for sign-extending non-legal types in SelectSIToFP().
...
llvm-svn: 143603
2011-11-03 02:04:59 +00:00
1f4603d498
Fixed parameter name.
...
llvm-svn: 143594
2011-11-02 23:37:04 +00:00
9929c423a1
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
...
llvm-svn: 143582
2011-11-02 22:52:45 +00:00
9cf803c4bf
Add support for comparing integer non-legal types.
...
llvm-svn: 143559
2011-11-02 18:08:25 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
...
llvm-svn: 143557
2011-11-02 18:03:14 +00:00
ec5c5f7008
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
...
llvm-svn: 143553
2011-11-02 17:46:18 +00:00
fad59dab62
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
...
llvm-svn: 143552
2011-11-02 17:41:23 +00:00
4489f948a7
Factor out an EmitIntExt function. No functionality change intended.
...
llvm-svn: 143547
2011-11-02 17:20:24 +00:00
a47b05c7f3
More AVX2 instructions and intrinsics.
...
llvm-svn: 143536
2011-11-02 06:54:17 +00:00
682b850602
Add a bunch more X86 AVX2 instructions and their corresponding intrinsics.
...
llvm-svn: 143529
2011-11-02 04:42:13 +00:00
ee7e452571
Factor out a SelectTrunc function. No functionality change intended.
...
llvm-svn: 143523
2011-11-02 00:18:48 +00:00
5c6b6346bc
ARM label operands can be quoted.
...
For example, labels from Objective-C sources.
llvm-svn: 143511
2011-11-01 22:38:31 +00:00
7f1f3bd868
ARM label operands can have an optional '#' before them.
...
llvm-svn: 143510
2011-11-01 22:37:37 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
...
llvm-svn: 143507
2011-11-01 22:18:13 +00:00
94441fbad7
rename getHostTriple into getDefaultTargetTriple
...
llvm-svn: 143502
2011-11-01 21:32:20 +00:00
3f5eccbe7a
Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289.
...
llvm-svn: 143498
2011-11-01 21:18:39 +00:00
56ce0932db
Don't fold negative offsets into cp / dp accesses to avoid relocation errors.
...
This can happen if the address + addend is less than the start of the cp / dp.
llvm-svn: 143459
2011-11-01 11:31:53 +00:00
fb2f1d61f4
ARM VLD/VST assembly parsing for symbolic address operands.
...
llvm-svn: 143413
2011-11-01 01:24:45 +00:00
d28ddbff8d
Add support for new atomics to cpp backend. Misc other fixes while I'm here. PR11268.
...
llvm-svn: 143406
2011-10-31 23:59:22 +00:00
05df460269
ARM VST1 w/ writeback assembly parsing and encoding.
...
llvm-svn: 143369
2011-10-31 21:50:31 +00:00
e4c8e692f2
ARM writeback vs. stride operands for VST/VLD.
...
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.
llvm-svn: 143356
2011-10-31 19:11:23 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
...
llvm-svn: 143351
2011-10-31 17:17:32 +00:00
cfcfdf2aab
Begin adding AVX2 instructions. No selection support yet other than intrinsics.
...
llvm-svn: 143331
2011-10-31 02:15:10 +00:00
aab6169ef6
Switch new .file directive emission off by default, change llc's flag for it to
...
-enable-dwarf-directory.
llvm-svn: 143326
2011-10-31 01:06:02 +00:00
228d9131aa
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
...
llvm-svn: 143319
2011-10-30 19:57:21 +00:00
7402ee6ec2
X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.
...
llvm-svn: 143315
2011-10-30 17:31:21 +00:00
c602b2c4de
Fix pr11266.
...
On x86: (shl V, 1) -> add V,V
Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.
llvm-svn: 143311
2011-10-30 13:24:22 +00:00
ff91dd9f07
PPC: Disable moves for all CR subregisters.
...
Should fix assertion failures on ppc buildbots.
llvm-svn: 143290
2011-10-29 19:43:38 +00:00
9b9c970148
Revert r143206, as there are still some failing tests.
...
llvm-svn: 143262
2011-10-29 00:41:52 +00:00
3d785edee2
ARM mode 'mov' to 'mvn' assembler alias.
...
llvm-svn: 143237
2011-10-28 22:50:54 +00:00
b009a872d7
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
...
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
llvm-svn: 143235
2011-10-28 22:36:30 +00:00
409b694c6c
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
...
llvm-svn: 143220
2011-10-28 20:43:24 +00:00
104b7e3f2c
Make changes necessary in LowerFormalArguments to support Mips64.
...
llvm-svn: 143218
2011-10-28 19:55:48 +00:00
b20a325baf
Make changes necessary in LowerCall to support Mips64.
...
llvm-svn: 143217
2011-10-28 19:49:00 +00:00
7989f15d37
Add variable IsO32 to MipsTargetLowering.
...
llvm-svn: 143213
2011-10-28 18:47:24 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
...
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
73057ad24f
Reapply r143177 and r143179 (reverting r143188), with scheduler
...
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
llvm-svn: 143206
2011-10-28 17:55:38 +00:00
effd094438
Revert r143202.
...
llvm-svn: 143203
2011-10-28 17:38:30 +00:00
df53d4fd61
Specify fixed bits on CPS instructions to enable roundtripping.
...
llvm-svn: 143202
2011-10-28 17:29:39 +00:00
7a49575d7f
Thumb2 ADD/SUB instructions encoding selection outside IT block.
...
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
llvm-svn: 143201
2011-10-28 16:57:07 +00:00
225a7037d6
Speculatively disable Dan's commits 143177 and 143179 to see if
...
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
llvm-svn: 143188
2011-10-28 09:55:57 +00:00
4db3f7dd83
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
...
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
llvm-svn: 143177
2011-10-28 01:29:32 +00:00
080a499ee0
ARM Allow 'q' registers in VLD/VST vector lists.
...
Just treat it as if the constituent D registers where specified.
rdar://10348896
llvm-svn: 143167
2011-10-28 00:06:50 +00:00
4c9fca99c9
Remove the Alpha backend.
...
llvm-svn: 143164
2011-10-27 22:56:32 +00:00
8a6ebd085a
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
...
llvm-svn: 143162
2011-10-27 22:53:10 +00:00
e5a6adceac
Also set addrmode6 alignment when align==size.
...
Previously, we were only setting the alignment bits on over-aligned
loads and stores.
llvm-svn: 143160
2011-10-27 22:39:16 +00:00
12a39540bb
ARM isel for vld1, opcode selection for register stride post-index pseudos.
...
llvm-svn: 143158
2011-10-27 22:25:42 +00:00
f4807a19e8
Avoid partial CPSR dependency from loop backedges. rdar://10357570
...
llvm-svn: 143145
2011-10-27 21:21:05 +00:00
49e6a0da7e
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
...
not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
llvm-svn: 143112
2011-10-27 17:40:41 +00:00
6ed3845530
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
...
rdar://10348844
llvm-svn: 143110
2011-10-27 17:33:59 +00:00
ba7f90c7df
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
...
rdar://10348584
llvm-svn: 143108
2011-10-27 17:16:55 +00:00
d24e7e1d9b
A branch predicated on a constant can just FastEmit an unconditional branch.
...
llvm-svn: 143086
2011-10-27 00:21:16 +00:00
58dba012b6
Rename NonScalarIntSafe to something more appropriate.
...
llvm-svn: 143080
2011-10-26 23:50:43 +00:00
a486f44733
Add a TODO comment. FastISel works by parsing each basic block from the bottom
...
up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
llvm-svn: 143079
2011-10-26 23:34:37 +00:00
78127d31f3
Factor a little more code into EmitCmp, which should have been done in the first
...
place. No functional change intended.
llvm-svn: 143078
2011-10-26 23:25:44 +00:00
eafbf3faa9
Use EmitCmp in SelectBranch. No functional change intended.
...
llvm-svn: 143076
2011-10-26 23:17:28 +00:00
59a201950b
Factor out an EmitCmp function that can be used by both SelectCmp and
...
SelectBranch. No functional change intended.
llvm-svn: 143072
2011-10-26 22:47:55 +00:00
61fdba048f
Thumb2 ldr pc-relative encoding fixes.
...
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
llvm-svn: 143068
2011-10-26 22:22:01 +00:00
b3285224cd
Fixes an issue reported by -verify-machineinstrs.
...
Patch by Sanjoy Das.
llvm-svn: 143064
2011-10-26 21:16:41 +00:00
4e380354a9
ARM parse parenthesized expressions for label references.
...
Partial fix for rdar://10348687.
llvm-svn: 143063
2011-10-26 21:14:08 +00:00
66393c127d
This commit introduces two fake instructions MORESTACK_RET and
...
MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively. Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV). It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.
Patch by Sanjoy Das.
llvm-svn: 143062
2011-10-26 21:12:27 +00:00
c47e283430
Make sure short memsets on ARM lower to stores, even when optimizing for size.
...
llvm-svn: 143055
2011-10-26 20:56:52 +00:00
25d4707c4d
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
...
llvm-svn: 143034
2011-10-26 17:28:15 +00:00
dd9137aa56
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
...
llvm-svn: 143023
2011-10-26 08:53:19 +00:00
1414bc5a14
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
...
llvm-svn: 143018
2011-10-26 07:16:18 +00:00
043c9d3f7a
Revert part of r142530. The patch potentially hurts performance especially
...
on Darwin platforms where -Os means optimize for size without hurting
performance.
llvm-svn: 143002
2011-10-26 01:17:44 +00:00
c0ecd1f7ed
Corrects previously incorrect $sp change in MipsCompilationCallback.
...
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned
Patch by Petar Jovanovic.
llvm-svn: 142930
2011-10-25 17:30:47 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
...
Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
b43c36f391
Remove the Blackfin backend.
...
llvm-svn: 142880
2011-10-25 00:05:42 +00:00
dfc96aea90
Remove the SystemZ backend.
...
llvm-svn: 142878
2011-10-24 23:48:32 +00:00
30c39c8bf2
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
...
llvm-svn: 142877
2011-10-24 23:40:46 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
...
Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
a5e244c08d
Don't crash on variable insertelement on ARM. PR10258.
...
llvm-svn: 142871
2011-10-24 23:08:52 +00:00
f33bfbbace
ARMConstantPoolMBB::print should print BB number.
...
llvm-svn: 142867
2011-10-24 23:01:03 +00:00
3ea0657d54
ARM assembly parsing and encoding for VLD1 w/ writeback.
...
One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
2098cb1e6f
ARM refactor am6offset usage for VLD1.
...
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
b72d55353a
Add support to the old JIT for acquire/release loads and stores on x86. PR11207.
...
llvm-svn: 142841
2011-10-24 20:24:21 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
...
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
4ed1afa51d
Change this overloaded use of Sched::Latency to be an overloaded
...
use of Sched::ILP instead, as Sched::Latency is going away.
llvm-svn: 142813
2011-10-24 17:55:11 +00:00
2c9bda1512
Remove the explicit request for "Latency" scheduling from MSP430,
...
as the Latency scheduler is going away.
llvm-svn: 142811
2011-10-24 17:53:16 +00:00
1b5e49a35a
Thumb2 LDM instructions can target PC. Make sure to encode it.
...
PR11220
llvm-svn: 142801
2011-10-24 17:16:24 +00:00
b05d9e9bea
Add X86 SARX, SHRX, and SHLX instructions.
...
llvm-svn: 142779
2011-10-23 22:18:24 +00:00
980d59832a
Add X86 RORX instruction
...
llvm-svn: 142741
2011-10-23 07:34:00 +00:00
e94d277db8
Add X86 MULX instruction for disassembler.
...
llvm-svn: 142738
2011-10-23 00:33:32 +00:00
7412aa9886
Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions.
...
llvm-svn: 142737
2011-10-22 23:13:53 +00:00
0d6d098841
Move various generated tables into read-only memory, fixing up const correctness along the way.
...
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
e649d66552
Fix pr11193.
...
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.
llvm-svn: 142724
2011-10-22 12:39:25 +00:00
94e6643fce
The different flavors of ARM have different valid subsets of registers. Check
...
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
llvm-svn: 142706
2011-10-22 00:29:28 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
...
llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
...
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
...
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
...
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
...
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
03a173eb71
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
...
llvm-svn: 142669
2011-10-21 18:43:28 +00:00
e6d88c9a51
Nuke an #if0 that got accidentally left in.
...
llvm-svn: 142658
2011-10-21 16:59:08 +00:00
20cb505e2f
whitespace.
...
llvm-svn: 142657
2011-10-21 16:56:40 +00:00
e3013dd62d
Remove some outdated comments.
...
llvm-svn: 142653
2011-10-21 16:14:12 +00:00
039a79067a
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
...
llvm-svn: 142642
2011-10-21 06:55:01 +00:00
c842c2ffe2
Fix unused variable warning.
...
llvm-svn: 142630
2011-10-21 01:22:04 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
...
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
000e2add18
Disable the PPC hazard recognizer. It currently only supports
...
top-down scheduling and top-down scheduling is going away.
llvm-svn: 142621
2011-10-20 21:45:36 +00:00
3acac94b60
Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
...
llvm-svn: 142618
2011-10-20 21:24:38 +00:00
cf7bdf4438
Add missing operand. <rdar://problem/10313323>
...
llvm-svn: 142615
2011-10-20 20:37:11 +00:00
aaf379027d
Haven't yet found a nice way to handle TargetData verification in the
...
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.
llvm-svn: 142605
2011-10-20 19:24:44 +00:00
79ebc51c45
Tidy up. Trailing whitespace.
...
llvm-svn: 142591
2011-10-20 17:28:20 +00:00
9036c5cf2b
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
...
llvm-svn: 142583
2011-10-20 15:04:25 +00:00
8db25984a9
ARM VTBX (one register) assembly parsing and encoding.
...
llvm-svn: 142581
2011-10-20 14:48:50 +00:00
add38c12b8
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
...
llvm-svn: 142557
2011-10-20 00:07:12 +00:00
54d678fff4
Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355
...
llvm-svn: 142550
2011-10-19 22:22:54 +00:00
2d768fd379
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
...
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
llvm-svn: 142530
2011-10-19 14:11:07 +00:00
2977a15ab1
Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.
...
llvm-svn: 142485
2011-10-19 09:24:02 +00:00
7c1634556d
Remove some dead code.
...
llvm-svn: 142484
2011-10-19 09:04:11 +00:00
ef309c3384
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
...
llvm-svn: 142480
2011-10-19 07:48:35 +00:00
94f60018e0
Emit the MOVT instruction only if the # LPads is > 64K.
...
llvm-svn: 142460
2011-10-18 23:19:55 +00:00
64e6bfc16c
For Thumb mode, we need to use a constant pool if the value is too large to be
...
used with the CMP instruction.
llvm-svn: 142458
2011-10-18 23:11:05 +00:00
16ec8c103a
Revert "Turn on the vzeroupper pass by default."
...
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.
llvm-svn: 142455
2011-10-18 23:10:11 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
...
llvm-svn: 142441
2011-10-18 23:02:30 +00:00
4969dcdef9
Use the integer compare when the value is small enough. Use the "move into a
...
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
llvm-svn: 142440
2011-10-18 22:52:20 +00:00
9bede2dd92
Turn on the vzeroupper pass by default.
...
I'll remove/rename the option in a few days.
llvm-svn: 142439
2011-10-18 22:50:17 +00:00
85833f71c6
Use the integer compare when the value is small enough. Use the "move into a
...
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.
llvm-svn: 142437
2011-10-18 22:49:07 +00:00
7d2f7b5a33
Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>.
...
llvm-svn: 142432
2011-10-18 22:11:33 +00:00
973c817cde
The value we're comparing against may be too large for the ARM CMP
...
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>
llvm-svn: 142431
2011-10-18 22:11:18 +00:00
b2a703d352
The immediate may be too large for the CMP instruction. Move it into a register
...
and use that in the CMP.
<rdar://problem/10305266>
llvm-svn: 142429
2011-10-18 21:55:58 +00:00
6918617e32
Yet more ARM NEON assembly parsing for the lane index operand.
...
llvm-svn: 142416
2011-10-18 20:21:17 +00:00
e9f204c197
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142413
2011-10-18 20:14:56 +00:00
712f3670fd
ARM vmov assembly parsing for the lane index operand.
...
llvm-svn: 142412
2011-10-18 20:10:47 +00:00
88b2450adc
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
...
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
llvm-svn: 142397
2011-10-18 19:18:52 +00:00
93b0f7b319
Use isIntN and isUIntN to check for valid signed/unsigned numbers.
...
llvm-svn: 142395
2011-10-18 18:46:49 +00:00
3f07c429b5
whitespace
...
llvm-svn: 142394
2011-10-18 18:40:53 +00:00
617075fcf6
A landing pad could have more than one predecessor. In that case, we want that
...
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>
llvm-svn: 142390
2011-10-18 18:30:49 +00:00
611450071c
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142389
2011-10-18 18:27:07 +00:00
c8eff0327a
ARM vqdmulh assembly parsing for the lane index operand.
...
llvm-svn: 142386
2011-10-18 18:12:09 +00:00
e6fbca3a61
ARM vmul assembly parsing for the lane index operand.
...
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
...
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
9258b76d8d
Fix incorrect check for sign-extended constant BUILD_VECTOR.
...
<rdar://problem/10298332>
llvm-svn: 142371
2011-10-18 17:34:51 +00:00
af26d7e280
ARM vqdmlal assembly parsing for the lane index operand.
...
llvm-svn: 142365
2011-10-18 17:16:30 +00:00
dfa7fb8fe6
Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
...
llvm-svn: 142363
2011-10-18 17:09:35 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
...
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
1fb5bb126e
PTX: Fix disabling of MAD instruction selection
...
llvm-svn: 142352
2011-10-18 13:39:20 +00:00
d278d35b13
Fix a bunch of unused variable warnings when doing a release
...
build with gcc-4.6.
llvm-svn: 142350
2011-10-18 12:44:00 +00:00
2b7a1ff77f
Coding style cleanups. No functionality change.
...
llvm-svn: 142341
2011-10-18 07:40:22 +00:00
49045ddb4c
Remove NaClMode
...
llvm-svn: 142338
2011-10-18 05:29:23 +00:00
0ffe593a16
Add support for dynamic stack realignment when in thumb1 mode.
...
rdar://10288916
llvm-svn: 142337
2011-10-18 05:28:00 +00:00
1c192774b6
Commit test, capitalizing store... keep it simple.
...
llvm-svn: 142336
2011-10-18 04:44:36 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
...
llvm-svn: 142332
2011-10-18 03:17:34 +00:00
22d3adf6aa
Backing out patch. Will refactor to remove the AsmParser dependency on Target.
...
llvm-svn: 142323
2011-10-18 00:23:49 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
...
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
6f1ccffc8e
Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies.
...
Thanks to Raphael Espindola for tracking down the CMake issues.
llvm-svn: 142306
2011-10-17 23:24:48 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
...
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
40f8f2ff24
Add support for a new extension to the .file directive:
...
.file filenumber "directory" "filename"
This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.
llvm-svn: 142300
2011-10-17 23:05:28 +00:00
b522550ce5
Add a few FIXME comments.
...
llvm-svn: 142299
2011-10-17 22:54:23 +00:00
f18eec158c
Tidy up.
...
llvm-svn: 142297
2011-10-17 22:41:42 +00:00
d2d0acdc04
142288 broke the build:
...
Linking CXX executable ../../bin/llvm-as
../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)'
clang-3: error: linker command failed with exit code 1 (use -v to see invocation)
Revert "Validate target data layout strings."
This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e.
llvm-svn: 142296
2011-10-17 22:37:51 +00:00
aa9047d3f5
Now Igor, throw the switch...give my creation life!
...
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.
It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.
Neat, huh?
<rdar://problem/10116753>
llvm-svn: 142294
2011-10-17 22:26:23 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
...
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
0533a9508b
Validate target data layout strings.
...
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion.
llvm-svn: 142288
2011-10-17 22:05:34 +00:00
0dfb159250
Use a SmallVector for intrinsic argument types.
...
llvm-svn: 142259
2011-10-17 21:33:26 +00:00
510fbcd440
Don't renumber the blocks here. This could cause problems later on if another
...
pass renumbers the blocks again.
llvm-svn: 142258
2011-10-17 21:32:56 +00:00
4373c21205
Pseudoinstructions should not be less constrained than the instruction they are
...
lowered to. This fixes a lot of verifier failures on the test suite.
llvm-svn: 142254
2011-10-17 21:20:13 +00:00
2ad0dee309
Tidy up organization.
...
llvm-svn: 142248
2011-10-17 21:00:11 +00:00
f7f223f69e
Add a call to EmitSjLjDispatchBlock.
...
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.
llvm-svn: 142245
2011-10-17 20:37:20 +00:00
2fbdcedbb1
Fix improperly formed assert() call.
...
llvm-svn: 142239
2011-10-17 20:22:59 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
652985764e
Revert change to function alignment b/c existing logic was fine
...
llvm-svn: 142224
2011-10-17 18:53:03 +00:00
34957911e7
Removed set, but unused variables.
...
Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142223
2011-10-17 18:48:30 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
...
llvm-svn: 142220
2011-10-17 18:43:19 +00:00
3634f34659
Revert change made in r142205.
...
llvm-svn: 142217
2011-10-17 18:33:24 +00:00
33fe8f908c
Redefine count-leading 0s and 1s instructions.
...
llvm-svn: 142216
2011-10-17 18:26:37 +00:00
8c446be204
Redefine mfhi/lo and mthi/lo instructions.
...
llvm-svn: 142214
2011-10-17 18:24:15 +00:00
0317b65367
Redefine multiply and divide instructions.
...
llvm-svn: 142211
2011-10-17 18:21:24 +00:00
2736bbc09e
Add definition of a base class for logical shift/rotate instructions with two
...
source registers and redefine 32-bit and 64-bit instructions.
llvm-svn: 142210
2011-10-17 18:17:58 +00:00
afa70aa272
Remove >80-col line and unicode
...
llvm-svn: 142209
2011-10-17 18:10:08 +00:00
73081309c3
Add definition of a base class for logical shift/rotate immediate instructions
...
and have 32-bit and 64-bit instructions derive from it.
llvm-svn: 142207
2011-10-17 18:06:56 +00:00
e3f27b79dc
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
...
llvm-svn: 142205
2011-10-17 18:01:00 +00:00
0050f59665
Fix CMake build.
...
llvm-svn: 142204
2011-10-17 17:50:39 +00:00
76c8563239
svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp
...
There is no reason to have simple IR level pass in lib/Target.
llvm-svn: 142200
2011-10-17 17:17:43 +00:00
0ade47acd0
Instructions for Book E PPC should be word aligned, set function alignment to reflect this
...
llvm-svn: 142194
2011-10-17 17:01:41 +00:00
e20793a4f1
Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147.
...
llvm-svn: 142177
2011-10-17 05:33:10 +00:00
26d2780d07
Add comment explaining that the order of processing doesn't matter here.
...
llvm-svn: 142176
2011-10-17 05:25:09 +00:00
ad677b64db
Add PPC 440 scheduler and some associated tests (new files)
...
llvm-svn: 142171
2011-10-17 04:03:55 +00:00
6fa5697af0
Add PPC 440 scheduler and some associated tests
...
llvm-svn: 142170
2011-10-17 04:03:49 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
1930b003fe
Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.
...
<stdin>:1:12: error: register %rax is only available in 64-bit mode
incl %rax
^~~~
llvm-svn: 142137
2011-10-16 12:10:27 +00:00
d416bae5f2
X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands.
...
<stdin>:1:4: error: invalid instruction mnemonic 'abc'
abc incl %edi
^~~
llvm-svn: 142135
2011-10-16 11:28:29 +00:00
bc25b6eb67
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
...
no pattern.
llvm-svn: 142130
2011-10-16 10:02:06 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
...
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
434b3bff44
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
...
These missing flags show up as errors when running -verify-coalescing on
test-suite.
llvm-svn: 142111
2011-10-16 06:38:10 +00:00
08ca5d35bd
Fix an obvious typo found when looking at nearby code.
...
llvm-svn: 142110
2011-10-16 06:38:06 +00:00
a3a0681083
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
...
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
6c8879e3ab
Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.
...
llvm-svn: 142089
2011-10-16 00:21:51 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
45f0f87af5
The CELL backend cannot select patterns for vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements.
...
llvm-svn: 142081
2011-10-15 20:05:17 +00:00
097106b77a
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
...
llvm-svn: 142080
2011-10-15 20:03:12 +00:00
5fb5e3b384
SmallVector -> array
...
llvm-svn: 142073
2011-10-15 13:28:31 +00:00
dd2b39d989
Mark tADDrSPi as having side effects again.
...
It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations. I am guessing that it got
moved across a stack pointer update.
Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.
llvm-svn: 142030
2011-10-15 00:57:13 +00:00
1809d6c0d5
Thumb1 does not support dynamic stack realignment.
...
rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
llvm-svn: 142028
2011-10-15 00:28:24 +00:00
9c1019c6c7
Mark registers as DEAD because they're really just clobbers.
...
llvm-svn: 142027
2011-10-15 00:27:44 +00:00
74d1da5a05
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
...
llvm-svn: 142022
2011-10-14 23:58:49 +00:00
9e0cd1ee17
Make sure that the register is in the register class before adding it as a machine op.
...
llvm-svn: 142021
2011-10-14 23:55:44 +00:00
6f3f9a391e
Mark the invoke call instruction as implicitly defining the callee-saved registers.
...
The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
llvm-svn: 142018
2011-10-14 23:34:37 +00:00
8b478360ef
Fix a non-firing assert. Change:
...
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
llvm-svn: 142000
2011-10-14 20:50:26 +00:00
06fdaeb5d9
A few 80-col violations.
...
llvm-svn: 141988
2011-10-14 20:36:23 +00:00
450128a68c
Add an implementation of the CanLowerReturn function to the PPC backend
...
llvm-svn: 141981
2011-10-14 19:51:36 +00:00
44419bfd54
Add f128 to datalayout string.
...
llvm-svn: 141978
2011-10-14 19:14:50 +00:00
4903379088
initial test commit (remove whitespace)
...
llvm-svn: 141972
2011-10-14 18:54:13 +00:00
62b34a65f9
Revert r141932, r141936 and r141937.
...
llvm-svn: 141959
2011-10-14 17:16:39 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
...
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
d9ea7c8c31
Definition of function getMipsRegisterNumbering.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141938
2011-10-14 03:04:24 +00:00
1742a2c093
Add definition of class MipsELFWriterInfo.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141937
2011-10-14 02:55:47 +00:00
0fc7d7af5a
Add missing relocation types.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141936
2011-10-14 02:47:50 +00:00
769fc971b4
Fixup enumerations.
...
Patch by Jack Carter at Mips.
llvm-svn: 141934
2011-10-14 02:38:56 +00:00
4e2bfe0770
Add more Mips relocation types.
...
Patch by Jack Carter at Mips.
llvm-svn: 141932
2011-10-14 02:17:30 +00:00
d9444d455e
Ban rematerializable instructions with side effects.
...
TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
llvm-svn: 141929
2011-10-14 01:00:49 +00:00
eafa9d50c2
V_SET0 has no side effects.
...
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.
This was part of the cause for PR11125, but the real bug was fixed
in r141923.
llvm-svn: 141924
2011-10-14 00:39:50 +00:00
a7ad9f3932
Fix undefined shift. Patch by Ahmed Charles.
...
llvm-svn: 141914
2011-10-13 23:36:06 +00:00
a5abd03a8d
Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles.
...
llvm-svn: 141912
2011-10-13 23:27:48 +00:00
92734d6f46
Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles.
...
llvm-svn: 141909
2011-10-13 23:13:35 +00:00
aa6ec39056
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
...
llvm-svn: 141903
2011-10-13 22:40:23 +00:00
44f76eafae
SETEND is not allowed in an IT block.
...
llvm-svn: 141874
2011-10-13 17:58:39 +00:00
3815de8d50
Mark 'branch indirect' instruction as an indirect branch.
...
Not having it confused assembly printing of jumptables.
llvm-svn: 141862
2011-10-13 11:40:03 +00:00
25f6d3e321
More closely follow libgcc, which has code after the `ret' instruction to
...
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.
llvm-svn: 141859
2011-10-13 08:24:19 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
...
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
22a690e3db
Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
...
llvm-svn: 141856
2011-10-13 07:42:32 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
2fdcb1f045
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt
...
llvm-svn: 141853
2011-10-13 06:18:52 +00:00
a098a891ab
ARM addrmode5 represents the 'U' bit of the encoding backwards.
...
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
llvm-svn: 141819
2011-10-12 21:59:02 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
...
llvm-svn: 141811
2011-10-12 20:54:17 +00:00
8007320902
addrmode2 is gone from these, so no need for the reg0 operand.
...
llvm-svn: 141794
2011-10-12 18:11:24 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
d74c0e7c14
80 columns.
...
llvm-svn: 141781
2011-10-12 16:36:01 +00:00
6966411f45
Tidy up. Formatting.
...
llvm-svn: 141780
2011-10-12 16:34:37 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
...
llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
...
Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
064c1c0e77
Fix indent in comment.
...
llvm-svn: 141749
2011-10-12 00:14:12 +00:00
39c31a77b8
Fix -widen-vmovs liveness issues.
...
When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
llvm-svn: 141746
2011-10-12 00:06:23 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
...
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
...
instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
8d4f74a6b1
Fix comment.
...
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
1c18465859
Fix function isUnalignedLoadStore.
...
llvm-svn: 141722
2011-10-11 22:04:01 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
453ac88b56
Change the names of 64-bit logical instructions so that they match the names of
...
the real instructions.
llvm-svn: 141718
2011-10-11 21:48:01 +00:00
265328baf6
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
12b2889989
ARM addressing mode cleanup for LDC/STC.
...
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
llvm-svn: 141704
2011-10-11 20:17:35 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
a95ec99a96
ARM parse alignment specifier for NEON load/store instructions.
...
llvm-svn: 141682
2011-10-11 17:29:55 +00:00
871dff76df
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
...
llvm-svn: 141671
2011-10-11 15:59:20 +00:00
e8ae98a8d9
Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.
...
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).
llvm-svn: 141666
2011-10-11 12:55:35 +00:00
68591286bc
Fix a iterator out of bounds error, that triggers rarely.
...
llvm-svn: 141665
2011-10-11 12:55:18 +00:00
63bc541196
Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS.
...
llvm-svn: 141656
2011-10-11 07:13:09 +00:00
0fbca75c17
Make Ivy Bridge 16-bit floating point conversion instructions require AVX.
...
llvm-svn: 141654
2011-10-11 07:01:37 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
da7c0f8f7d
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
...
The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
llvm-svn: 141619
2011-10-11 00:59:06 +00:00
09b23eb7bc
Modify lowering of GlobalAddress so that correct code is emitted when target is
...
Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
f22f46bf25
Fixed natural stack alignment for Linux x86-32. Thanks Eli.
...
llvm-svn: 141616
2011-10-11 00:51:36 +00:00
fa55bc27cb
Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.
...
llvm-svn: 141615
2011-10-11 00:44:20 +00:00
e6ced5b3d5
Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.
...
llvm-svn: 141613
2011-10-11 00:37:28 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
...
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
98703350d0
Simplify check that optional def is there and is CPSR.
...
llvm-svn: 141602
2011-10-11 00:10:41 +00:00
de7ab801cc
Add a natural stack alignment field to TargetData, and prevent InstCombine from
...
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
llvm-svn: 141599
2011-10-10 23:42:08 +00:00
c11b7c3805
Simplify operand Kind checks a bit.
...
llvm-svn: 141592
2011-10-10 23:06:42 +00:00
a7d697e4a6
Reapply r141365 now that PR11107 is fixed.
...
llvm-svn: 141591
2011-10-10 22:59:55 +00:00
2957c88c0a
Add a name to sub-operand for clarity.
...
llvm-svn: 141590
2011-10-10 22:55:05 +00:00
0a10cdc704
If the CPSR is defined by a copy, then we don't want to merge it into an IT
...
block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
llvm-svn: 141589
2011-10-10 22:52:53 +00:00
8ec0897db6
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
...
llvm-svn: 141585
2011-10-10 22:28:47 +00:00
874c519337
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
...
llvm-svn: 141571
2011-10-10 19:35:07 +00:00
814598563f
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
...
instruction set has no 64-bit SRA support.
llvm-svn: 141570
2011-10-10 19:31:45 +00:00
42c0330a79
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
...
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
47aac51043
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
...
hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
ea662bb32f
When getting the number of bits necessary for addressing mode
...
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
llvm-svn: 141529
2011-10-10 07:24:23 +00:00
a14c5723eb
Put a bunch of calls to ToggleFeature behind proper if statements.
...
llvm-svn: 141527
2011-10-10 05:34:02 +00:00
b60187ae74
Fix a regression from r138445. If we're loading from the frame/base pointer
...
the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
llvm-svn: 141523
2011-10-10 01:03:35 +00:00
dd40b0d792
PTX: Print .ptr kernel attributes if PTX version >= 2.2
...
llvm-svn: 141508
2011-10-09 15:42:02 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
...
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
513d1213cc
Prevent potential NOREX bug.
...
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:
%vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2
If such a live range is ever split, its register class must not be
inflated to GR8. The sub-register copy can only target GR8_NOREX.
I dont have a test case for this theoretical bug.
llvm-svn: 141500
2011-10-08 20:20:03 +00:00
729abd360e
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
...
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.
TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.
This fixes PR11088.
llvm-svn: 141499
2011-10-08 18:28:28 +00:00
a0263e7aca
Always check if a method or a type exist before trying to create it.
...
llvm-svn: 141490
2011-10-08 11:56:36 +00:00
e45373520d
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
...
llvm-svn: 141481
2011-10-08 08:38:45 +00:00
6be7d6c976
Simplify definition of FP move instructions.
...
llvm-svn: 141476
2011-10-08 03:50:18 +00:00
2365f90676
Define classes and multiclasses for FP binary instructions.
...
llvm-svn: 141475
2011-10-08 03:38:41 +00:00
c7548dec7d
Define multiclasses for FP-to-FP instructions.
...
llvm-svn: 141474
2011-10-08 03:29:22 +00:00
13ae13bdc2
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
...
conversion instructions.
llvm-svn: 141473
2011-10-08 03:19:38 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
...
instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
6e5778f7b1
ARM prefix asmparser operand kind enums for readability.
...
llvm-svn: 141438
2011-10-07 23:24:09 +00:00
883ec97115
Take all of the invoke basic blocks and make the dispatch basic block their new
...
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
llvm-svn: 141436
2011-10-07 23:18:02 +00:00
f9f5e455d4
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
...
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
llvm-svn: 141419
2011-10-07 22:08:37 +00:00
7ecfbd90ef
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
...
do. This will be useful later on with the new SJLJ stuff.
llvm-svn: 141416
2011-10-07 21:25:38 +00:00
464fcc0035
Constrain both operands on MOVZX32_NOREXrr8.
...
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.
Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.
This fixes a miscompilation in 20040709-2 in the gcc test suite.
llvm-svn: 141410
2011-10-07 20:15:54 +00:00
b8d9f51e4c
Improve ARM assembly parser diagnostic for unexpected tokens.
...
Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
llvm-svn: 141380
2011-10-07 18:27:04 +00:00
74db300f37
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
...
llvm-svn: 141371
2011-10-07 17:21:44 +00:00
8decdc472f
Reenable tail calls for iOS 5.0 and later.
...
llvm-svn: 141370
2011-10-07 17:17:49 +00:00
bc1589945d
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
...
llvm-svn: 141368
2011-10-07 16:59:21 +00:00
318d6bae80
Peephole optimization for ABS on ARM.
...
Patch by Ana Pazos!
llvm-svn: 141365
2011-10-07 16:15:08 +00:00
d9cfddc5cd
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
...
llvm-svn: 141358
2011-10-07 07:02:24 +00:00
bf136764ae
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
...
llvm-svn: 141354
2011-10-07 05:53:50 +00:00
5aebebe18d
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
...
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
8d50ea0f82
Use the correct vreg here.
...
llvm-svn: 141342
2011-10-06 23:41:14 +00:00
b3d4678877
Generate the dispatch code for a 'thumb' function. This is very similar to the
...
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
llvm-svn: 141341
2011-10-06 23:37:36 +00:00
6a5c150e9c
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
...
llvm-svn: 141339
2011-10-06 23:33:11 +00:00
1456cd20b4
Remove the old atomic instrinsics. autoupgrade functionality is included with this patch.
...
llvm-svn: 141333
2011-10-06 23:20:49 +00:00
5626c66a89
Generate the dispatch table for ARM mode.
...
llvm-svn: 141327
2011-10-06 22:53:00 +00:00
030b58e5c9
Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
...
llvm-svn: 141323
2011-10-06 22:18:16 +00:00
31d973cde6
Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
...
Place the immediate to OR into a register so that it works.
llvm-svn: 141319
2011-10-06 21:51:21 +00:00
362c1b01cc
* Set the low bit of the return address when we are in thumb mode.
...
* Some code cleanup.
llvm-svn: 141317
2011-10-06 21:29:56 +00:00
c8ab2c1d99
PTX: Implement signed division
...
llvm-svn: 141306
2011-10-06 20:00:33 +00:00
23eb468b1f
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
...
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
fb3d935649
Build system infrastructure for multiple tblgens.
...
llvm-svn: 141266
2011-10-06 01:51:51 +00:00
6134655f08
Add the MBBs before inserting the instructions. Doing it afterwards could lead
...
to an infinite loop because of the def-use chains.
Also use a frame load instead of store for the LD instruction.
llvm-svn: 141263
2011-10-06 00:53:33 +00:00
842f99a6ee
Always merge profitable shifts on A9, not just when they have a single use.
...
llvm-svn: 141248
2011-10-05 23:39:02 +00:00
87aa18378e
Remove a check from ARM shifted operand isel helper methods, which were blocking
...
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
llvm-svn: 141247
2011-10-05 23:38:50 +00:00
f793e7ed5c
Get the proper call site numbers for the landing pads. Also remove a magic
...
number (18) for the proper addressing mode.
llvm-svn: 141245
2011-10-05 23:28:57 +00:00
ee9b576a2a
Override TRI::getSubClassWithSubReg for X86.
...
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.
llvm-svn: 141206
2011-10-05 20:26:33 +00:00
664e9f55bf
PTX: Fixup a case where getRegClassFor() should be used instead of custom code.
...
llvm-svn: 141199
2011-10-05 18:32:25 +00:00
c6b742f98a
Fix assertion string.
...
llvm-svn: 141197
2011-10-05 18:17:49 +00:00
426a804825
Make sure candidate for delay slot filler is not a return instruction.
...
llvm-svn: 141196
2011-10-05 18:16:09 +00:00
14e4149f4e
Add RA to the set of registers that are defined if instruction is a call.
...
llvm-svn: 141194
2011-10-05 18:11:44 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
6e8129e127
Ensure OpCode is not used uninitialized.
...
llvm-svn: 141184
2011-10-05 15:13:13 +00:00
36ffaa809f
Comment out a variable that is only used in commented out code.
...
llvm-svn: 141183
2011-10-05 15:12:44 +00:00
b0e6d04a00
Remove a bunch of unused variables in the PTX backend (warned about by gcc-4.6).
...
llvm-svn: 141182
2011-10-05 15:11:08 +00:00
9ebdf46b5a
MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly.
...
llvm-svn: 141174
2011-10-05 10:11:02 +00:00
2226b4be09
Add braces around something that throws me for a loop.
...
llvm-svn: 141173
2011-10-05 08:59:10 +00:00
6a7aa237cc
There is no point in setting out-parameters for a ComplexPattern function when
...
it returns false, at least as far as I could tell by reading the code.
llvm-svn: 141172
2011-10-05 08:59:05 +00:00
b58a9665bd
Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey.
...
llvm-svn: 141162
2011-10-05 03:29:32 +00:00
02e760add3
Insert space.
...
llvm-svn: 141158
2011-10-05 02:22:49 +00:00
8e532eb92f
Do not examine variadic or implicit operands if instruction is a return (jr).
...
llvm-svn: 141157
2011-10-05 02:21:58 +00:00
0d7dfc0b1f
Clean up function Filler::delayHasHazard.
...
llvm-svn: 141156
2011-10-05 02:18:58 +00:00
7b204688e7
Remove function Filler::insertCallUses.
...
Record the registers used and defined by a call in Filler::insertDefsUses.
llvm-svn: 141154
2011-10-05 02:04:17 +00:00
d9c8aab894
Clean up Filler::findDelayInstr.
...
llvm-svn: 141152
2011-10-05 01:57:46 +00:00
e7b0697412
Remove function Filler::isDelayFiller. Check if I is the same instruction that
...
filled the last delay slot visited.
llvm-svn: 141151
2011-10-05 01:30:09 +00:00
5d4e4ea3d5
Clean up Filler::runOnMachineBasicBlock. Change interface of
...
Filler::findDelayInstr.
llvm-svn: 141150
2011-10-05 01:23:39 +00:00
9e6034444a
Define a statistic for the number of slots that were filled with useful
...
instructions (instructions that are not NOP).
llvm-svn: 141149
2011-10-05 01:19:13 +00:00
8b3666af1b
Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before
...
I->getDesc().hasDelaySlot() does.
llvm-svn: 141148
2011-10-05 01:15:31 +00:00
7d398636a2
Add comments and move assignment statement. If sawStore is true, sawLoad does
...
not have to be set.
llvm-svn: 141147
2011-10-05 01:09:37 +00:00
b345b5c424
Correct description string of enable-mips-delay-filler.
...
llvm-svn: 141146
2011-10-05 01:06:57 +00:00
324be98a3c
Look at the number of entries in the jump table and jump to a 'trap' block if
...
the value exceeds that number.
llvm-svn: 141143
2011-10-05 00:39:32 +00:00
202803e39c
Checkpoint for SJLJ EH code.
...
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
llvm-svn: 141140
2011-10-05 00:02:33 +00:00
0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
...
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
e25602696e
Teach PPCInstrInfo to handle sub-classes.
...
This has already been done for most other targets.
llvm-svn: 141083
2011-10-04 15:28:47 +00:00
3b309efe38
Set operation actions to legal types only.
...
llvm-svn: 141075
2011-10-04 12:05:35 +00:00
04001625e4
Operations should be custom lowered only if their type is legal.
...
Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074
2011-10-04 10:03:32 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
69e6f90eb2
Tidy up. 80 columns.
...
llvm-svn: 141043
2011-10-03 23:03:26 +00:00
1eab54f8ba
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
...
llvm-svn: 141042
2011-10-03 22:44:15 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
374ee194f2
Check-pointing the new SjLj EH lowering.
...
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
llvm-svn: 141031
2011-10-03 21:25:38 +00:00
c3a6357ee3
Add support for 64-bit logical NOR.
...
llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
...
llvm-svn: 141028
2011-10-03 21:16:50 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
5dd3425b77
Thumb2 ADD/SUB can take SP as a destination register.
...
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
3caf8cb310
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
...
registers.
llvm-svn: 141019
2011-10-03 20:38:08 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
...
llvm-svn: 141017
2011-10-03 20:01:11 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
...
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
...
llvm-svn: 141007
2011-10-03 17:28:23 +00:00
cc349c8dd8
Add the returns_twice attribute to LLVM.
...
llvm-svn: 141001
2011-10-03 14:45:37 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
...
llvm-svn: 140997
2011-10-03 08:14:29 +00:00
31854ba017
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
...
llvm-svn: 140993
2011-10-03 07:51:09 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
...
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
...
llvm-svn: 140971
2011-10-02 16:56:09 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
a88cb23da7
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
...
to appease nightly testers. Not quite there yet.
llvm-svn: 140953
2011-10-01 19:30:36 +00:00
d072b73d78
No one should be using the method directly. Assert if they do.
...
llvm-svn: 140947
2011-10-01 12:47:34 +00:00
f977ff5fb5
Add a convenience method to tell if two things are equal.
...
llvm-svn: 140946
2011-10-01 12:44:28 +00:00
4a4772fae2
Use the ARMConstantPoolMBB class to handle the MBB values.
...
llvm-svn: 140943
2011-10-01 09:30:42 +00:00
6dbc9fe82b
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
...
llvm-svn: 140942
2011-10-01 09:19:10 +00:00
c5a86069ca
Remove dead code.
...
llvm-svn: 140941
2011-10-01 09:05:12 +00:00
9ff05f740f
Remove now dead methods and ivar.
...
llvm-svn: 140940
2011-10-01 09:04:18 +00:00
c214cb055d
Use the new ARMConstantPoolSymbol class to handle external symbols.
...
llvm-svn: 140939
2011-10-01 08:58:29 +00:00
d7fa016720
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
...
llvm-svn: 140938
2011-10-01 08:36:59 +00:00
d115c4d300
Remove now dead methods and ivar from ARMConstantPoolValue.
...
llvm-svn: 140937
2011-10-01 08:02:05 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
f117a35de0
Some more refactoring.
...
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
llvm-svn: 140935
2011-10-01 07:52:37 +00:00
6722556380
Add a Create method that accepts 'kind' and 'pcadj' arguments.
...
llvm-svn: 140934
2011-10-01 06:44:24 +00:00
396c211ae1
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
...
pool value.
It's not used right now, but will be soon.
llvm-svn: 140933
2011-10-01 06:40:33 +00:00
21360a4949
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
...
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
llvm-svn: 140924
2011-10-01 02:03:18 +00:00
237dceff90
Store sub-class lists as a bit vector.
...
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
1352be2bd3
Move getCommonSubClass() into TRI.
...
It will soon need the context.
llvm-svn: 140896
2011-09-30 22:18:51 +00:00
d76f43e18c
Correct for my over-eager delete finger.
...
llvm-svn: 140892
2011-09-30 22:02:45 +00:00
ee09394644
Register the MC object streamer.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
587fe6cd52
Add MCELFObjectTargetWriter and MCAsmBackend classes.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140885
2011-09-30 21:04:02 +00:00
3bad73a900
Update CMake build.
...
llvm-svn: 140879
2011-09-30 20:44:33 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
e8e4dbf468
Constify 'isLSDA' and move a method out-of-line.
...
llvm-svn: 140868
2011-09-30 18:42:06 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
9727af7657
isCommutable should be 0 for DSUBu.
...
llvm-svn: 140862
2011-09-30 17:26:36 +00:00
d2222c386c
ARM Fixup valus for movt/movw are for the whole value.
...
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
ea3f90ae40
PTX: Various stylistic and code readability changes recommended by Jim Grosbach.
...
llvm-svn: 140855
2011-09-30 14:36:36 +00:00
957a6d5c51
PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
...
Also take this opportunity to clean up the rounding mode pass.
llvm-svn: 140854
2011-09-30 13:46:52 +00:00
3111d11f23
PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires
...
us to manually provide Pat<> definitions for all FP instruction patterns.
llvm-svn: 140849
2011-09-30 12:54:43 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
95031ed837
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
...
llvm-svn: 140803
2011-09-29 20:21:17 +00:00
abcc57669d
PTX: Fix broken shared library build
...
llvm-svn: 140783
2011-09-29 14:25:48 +00:00
dd1904e7a6
Expand the x86 V_SET0* pseudos right after register allocation.
...
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
llvm-svn: 140776
2011-09-29 05:10:54 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
...
llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
...
llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
a0d5f268a9
Move to ISelLowering.
...
llvm-svn: 140754
2011-09-29 01:13:55 +00:00
fd47d8af8b
PTX: Add new patterns for bitconvert and any_extend
...
llvm-svn: 140753
2011-09-29 01:13:12 +00:00
6728958279
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
...
It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
8156376aa9
Tighten a ARM dag combine condition to avoid an identity transformation, which
...
ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
5a1b4a80c3
Define classes for unary and binary FP instructions and use them to define
...
multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
2fb357a5b0
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
...
llvm-svn: 140723
2011-09-28 21:00:25 +00:00
315b9573c6
Perform the lowering only if there are invokes.
...
llvm-svn: 140719
2011-09-28 20:29:45 +00:00
dfe5acd34e
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
...
llvm-svn: 140718
2011-09-28 20:29:28 +00:00
933d51682f
PTX: Fix alignment logic
...
llvm-svn: 140709
2011-09-28 18:24:58 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
...
llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
...
llvm-svn: 140704
2011-09-28 17:56:55 +00:00
c117967b19
Mips64 predicate definitions. Patch by Liu.
...
llvm-svn: 140703
2011-09-28 17:50:27 +00:00
f3d1d4eb4b
PTX: MC-ize the PTX backend (patch 2 of N)
...
Get rid of some of the no-longer-needed parts of PTXAsmPrinter.
llvm-svn: 140698
2011-09-28 14:32:06 +00:00
5e18b14ee2
PTX: MC-ize the PTX back-end (patch 1 of N)
...
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
llvm-svn: 140697
2011-09-28 14:32:04 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
8747e3e7ea
PTX: Simplify code. No functionality change.
...
llvm-svn: 140680
2011-09-28 04:32:36 +00:00
5d7a73fa8c
PTX: Pass param name strings per const reference.
...
The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)
llvm-svn: 140679
2011-09-28 04:08:02 +00:00
934b7d7645
Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.
...
I'll clean up the source in the next commit.
llvm-svn: 140663
2011-09-28 00:01:54 +00:00
ae40dc735d
Remove MipsFPRound. Mips1 is no longer supported.
...
llvm-svn: 140661
2011-09-27 23:55:37 +00:00
30c811246f
Remove X86-dependent stuff from SSEDomainFix.
...
This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
llvm-svn: 140659
2011-09-27 23:50:46 +00:00
e3e36f80f5
Unbreak CMake build.
...
llvm-svn: 140655
2011-09-27 23:29:59 +00:00
f9b71a2e01
Implement TII::get/setExecutionDomain() for ARM.
...
llvm-svn: 140653
2011-09-27 22:57:21 +00:00
b48c994cc0
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
...
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
llvm-svn: 140652
2011-09-27 22:57:18 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
354ff9e348
This is the start of the new SjLj EH preparation pass, which will replace the
...
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
...
of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
af136f71ec
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
...
Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
4f7054e56e
PTX: Fix case where printed alignment could be 0
...
llvm-svn: 140624
2011-09-27 19:25:49 +00:00
e074593498
PTX: Use external symbols to keep track of params and locals. This also fixes
...
a couple of outstanding issues with frame objects occuring as instruction
operands.
llvm-svn: 140616
2011-09-27 18:12:55 +00:00
1c7597693c
Use existing function.
...
llvm-svn: 140615
2011-09-27 17:55:08 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
...
Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
...
llvm-svn: 140607
2011-09-27 16:58:43 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
...
llvm-svn: 140598
2011-09-27 04:57:54 +00:00
9f01f89386
PTX: Add support for sitofp in backend
...
llvm-svn: 140593
2011-09-27 01:04:47 +00:00
b1a9f65487
Remove extraneous commit garbage.
...
llvm-svn: 140581
2011-09-26 23:14:02 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
...
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
da2919dbd8
PTX: Fix memcpy intrinsic to handle 64-bit pointers
...
llvm-svn: 140556
2011-09-26 19:19:48 +00:00
b40da7f956
PTX: Implement PTXSelectionDAGInfo
...
llvm-svn: 140549
2011-09-26 18:57:27 +00:00
c3edaddfea
PTX: Implement ISD::ANY_EXTEND
...
llvm-svn: 140548
2011-09-26 18:57:24 +00:00
1395cf8423
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
...
printing of local offsets
llvm-svn: 140547
2011-09-26 18:57:22 +00:00
f8dd701bf9
PTX: SM > 2.0 implies +double
...
llvm-svn: 140536
2011-09-26 16:20:36 +00:00
14defde057
PTX: Fix some lingering issues with stack allocation
...
llvm-svn: 140535
2011-09-26 16:20:34 +00:00
37fd87675f
PTX: Split up the TableGen instruction definitions into logical units
...
llvm-svn: 140534
2011-09-26 16:20:31 +00:00
d40f5ababf
PTX: Unify handling of loads/stores
...
llvm-svn: 140533
2011-09-26 16:20:28 +00:00
8c80019352
PTX: Handle FrameIndex nodes
...
llvm-svn: 140532
2011-09-26 16:20:25 +00:00
b1fbf9ff26
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
...
llvm-svn: 140516
2011-09-26 06:13:20 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
...
llvm-svn: 140515
2011-09-26 05:12:43 +00:00
fd719d184e
Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.
...
No functional change intended.
llvm-svn: 140470
2011-09-25 16:46:08 +00:00
7d7ee0c3ac
Add .td file.
...
llvm-svn: 140446
2011-09-24 01:40:18 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
55cf2ed148
Only run MF.verify() with EXPENSIVE_CHECKS=1.
...
llvm-svn: 140441
2011-09-24 01:11:19 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
2056d15bd9
Also match negative offsets for addrmode3 and addrmode5.
...
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
b0b865d658
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
...
llvm-svn: 140422
2011-09-23 21:57:50 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
...
llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
...
llvm-svn: 140412
2011-09-23 21:00:32 +00:00
d6af2c62b4
Implement N32/64 calling convention. Patch by Liu.
...
llvm-svn: 140401
2011-09-23 19:08:15 +00:00
ceb55e72de
Make FGR64RegisterClass available if target is Mips64.
...
llvm-svn: 140397
2011-09-23 18:28:39 +00:00
77709a6793
Add definitions of 64-bit register files. Add code for returning Mips64's sets of
...
callee-saved registers and reserved registers.
llvm-svn: 140395
2011-09-23 18:11:56 +00:00
71d32c980d
PTX: Fix parameter order bug
...
llvm-svn: 140394
2011-09-23 17:59:11 +00:00
24e45cabbc
Fix a couple of 80 column violations.
...
patch contributed by Jia Liu!
llvm-svn: 140391
2011-09-23 17:24:41 +00:00
6e84a68023
PTX: Cleanup unused code in PTXMachineFunctionInfo
...
llvm-svn: 140390
2011-09-23 17:15:53 +00:00
0f1af22183
PTX: Fix another 80-column violation
...
llvm-svn: 140387
2011-09-23 16:50:35 +00:00
37f35f0083
PTX: Handle function call return values
...
llvm-svn: 140386
2011-09-23 16:48:41 +00:00
ae191ef63b
Fix 80 column violations.
...
Original patch by Liu.
llvm-svn: 140385
2011-09-23 16:28:10 +00:00
a54fd541c2
Implement Chris's suggestion of legalizing the various SSE and AVX
...
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.
llvm-svn: 140383
2011-09-23 16:10:22 +00:00
6c23d2ee55
PTX: Start fixing function calls
...
llvm-svn: 140378
2011-09-23 14:31:12 +00:00
edc6bf474d
PTX: Remove PTX calling convention files
...
llvm-svn: 140377
2011-09-23 14:18:27 +00:00
f2b540e815
[PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns
...
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
lib/Target/PTX/PTXInstrInfo.td | 165 ++++++++++++++++++++----------
lib/Target/PTX/PTXIntrinsicInstrInfo.td | 88 +++++++++++------
2 files changed, 167 insertions(+), 86 deletions(-)
llvm-svn: 140376
2011-09-23 14:18:24 +00:00
b823e41bf4
PTX: Generalize handling of .param types
...
llvm-svn: 140375
2011-09-23 14:18:22 +00:00
2f82cc61af
PTX: Cleanup unused code in the PTXMFInfoExtract pass
...
llvm-svn: 140374
2011-09-23 14:18:19 +00:00
42fe6bd5f2
Add definitions of 64-bit int registers.
...
llvm-svn: 140366
2011-09-23 02:33:15 +00:00
61bbcce84a
Do not rely on the enum values of argument registers A0-A3 being consecutive.
...
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
87c844cdf8
PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)
...
llvm-svn: 140355
2011-09-22 23:41:28 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
f05864ad7d
Add support for GR32 <-> FR32 cross class copies.
...
We already support GR64 <-> VR128 copies. All of these copies break
partial register dependencies by zeroing the high part of the target
register.
llvm-svn: 140348
2011-09-22 22:45:24 +00:00
0e4fcb8e3b
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
...
floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
llvm-svn: 140332
2011-09-22 20:15:48 +00:00
56acf840f1
Print parentheses in next line.
...
llvm-svn: 140325
2011-09-22 18:29:29 +00:00
c021a4b8b4
Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment.
...
llvm-svn: 140324
2011-09-22 18:24:21 +00:00
79a45a839c
Define a new sub-register index sub_32 for accessing the 32-bit sub-register of
...
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.
llvm-svn: 140319
2011-09-22 17:57:32 +00:00
35b7fe8c25
Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or
...
VK_Mips_GPOFF_LO.
llvm-svn: 140316
2011-09-22 17:44:37 +00:00
da33066424
Add F31 to the set of callee-saved registers.
...
llvm-svn: 140315
2011-09-22 17:35:03 +00:00
cf9c4f80ba
Fix typo.
...
llvm-svn: 140313
2011-09-22 17:26:58 +00:00
efc211d977
PTX: Remove physical register defs
...
llvm-svn: 140310
2011-09-22 16:45:48 +00:00
43787cd447
PTX: Use .param space for device function return values on SM 2.0+, and attempt
...
to fix up parameter passing on SM < 2.0
llvm-svn: 140309
2011-09-22 16:45:46 +00:00
ae10a30386
PTX: Fix style issues
...
llvm-svn: 140308
2011-09-22 16:45:43 +00:00
8bc34e72e9
PTX: Fixup codegen to handle emission of virtual registers.
...
llvm-svn: 140307
2011-09-22 16:45:40 +00:00
47423e4fb9
PTX: Customize codegen passes in backend
...
llvm-svn: 140306
2011-09-22 16:45:37 +00:00
28a548ebe3
PTX: Add new PTX-specific register allocator that keeps virtual registers
...
instead of allocating physical registers.
This is part of a work-in-progress overhaul of the PTX register allocation scheme.
llvm-svn: 140305
2011-09-22 16:45:33 +00:00
6d1872b77a
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
...
llvm-svn: 140299
2011-09-22 07:01:50 +00:00
3d10b95bf7
Add definition of 64-bit floating registers used for Mips64.
...
llvm-svn: 140297
2011-09-22 03:48:47 +00:00
cfd26cd744
The SSE version differences for fmin/fmax are more involved than I thought.
...
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)
llvm-svn: 140296
2011-09-22 03:27:22 +00:00
25ce3647e5
Add enums and functions for symbols Mips64 uses.
...
llvm-svn: 140295
2011-09-22 03:09:07 +00:00
dc397a6402
X86: Don't form min/max nodes if the target is missing SSE.
...
llvm-svn: 140294
2011-09-22 03:01:42 +00:00
dc7baed9d3
Mips64 aligns stack on 16-byte boundary.
...
llvm-svn: 140292
2011-09-22 02:53:37 +00:00
6a5f8b2fd4
Remove unnecessary condition check.
...
llvm-svn: 140291
2011-09-22 02:41:29 +00:00
fbe52c0192
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
...
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
e5e189f669
X86Disassembler: if verbose logging is going to nulls(), disable logging completely.
...
Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.
llvm-svn: 140276
2011-09-21 21:47:35 +00:00
eee3afcb86
Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile.
...
patch contributed by Jia Liu!
llvm-svn: 140273
2011-09-21 19:23:46 +00:00
bcc3fadad9
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
...
llvm-svn: 140267
2011-09-21 17:58:45 +00:00
1b185f4c65
Undo a change made in r140254.
...
MipsArchVersion needs to be initialized to Mips32.
llvm-svn: 140261
2011-09-21 17:31:45 +00:00
50f123d8e5
fix comment
...
llvm-svn: 140258
2011-09-21 17:14:40 +00:00
bcc7a92e53
MipsArchVersion does not need to be in the initialization list and MipsABI
...
should be initialized to UnknownABI.
llvm-svn: 140254
2011-09-21 16:41:43 +00:00
c1cd8506ce
Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995.
...
llvm-svn: 140246
2011-09-21 08:45:10 +00:00
a318b8dce6
Change:
...
assert(!"error message");
To:
assert(0 && "error message");
which is more consistant across the code base.
llvm-svn: 140234
2011-09-21 03:09:09 +00:00
3d673cc323
Add a base class for Mips TargetMachines and add Mips64 TargetMachines.
...
llvm-svn: 140233
2011-09-21 03:00:58 +00:00
6de4d12120
Set ABI if it hasn't been set on the command line.
...
Check if architecture & ABI combination is valid.
llvm-svn: 140230
2011-09-21 02:45:29 +00:00
6e506eb57d
Fix typo.
...
llvm-svn: 140229
2011-09-21 02:24:25 +00:00
924123acb3
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
...
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
3f1fdf1b31
whitespace
...
llvm-svn: 140227
2011-09-21 02:17:37 +00:00
69fa8ffeef
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
...
llvm-svn: 140217
2011-09-21 00:25:23 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
...
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
8058234b32
Revert r140097, working on a better approach
...
llvm-svn: 140203
2011-09-20 23:19:29 +00:00
f7638e1e51
Simplify max/minp[s|d] dagcombine matching
...
llvm-svn: 140199
2011-09-20 22:34:45 +00:00
60aa85b672
Tidy up a bit more, fix tab and remove trailing whitespaces
...
llvm-svn: 140186
2011-09-20 21:45:26 +00:00
33e91a6cf7
The wrong relocation was being emitted for several SSSE3 instructions.
...
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
llvm-svn: 140184
2011-09-20 21:39:21 +00:00
05f3f4939a
Tidy up code!
...
llvm-svn: 140183
2011-09-20 21:39:06 +00:00
61a003315e
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
...
llvm-svn: 140181
2011-09-20 21:38:18 +00:00
2b37261fd6
Initial Mips64 support. Patch by Liu with some modifications.
...
llvm-svn: 140178
2011-09-20 20:28:08 +00:00
52363bdbeb
Restore hasPostISelHook tblgen flag.
...
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
llvm-svn: 140160
2011-09-20 18:22:31 +00:00
68c92d86da
Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.
...
llvm-svn: 140140
2011-09-20 07:38:59 +00:00
8586e62d91
ARM isel bug fix for adds/subs operands.
...
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
53df4b6dfa
whitespace
...
llvm-svn: 140133
2011-09-20 03:06:13 +00:00
b35198021a
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
...
llvm-svn: 140125
2011-09-20 00:46:54 +00:00
716f17399e
Thumb2 assembly parsing and encoding for USAX.
...
llvm-svn: 140119
2011-09-20 00:30:45 +00:00
691389c93f
Remove incorrect comments. These are not disassmebly only patterns.
...
llvm-svn: 140116
2011-09-20 00:26:34 +00:00
62f8eee0eb
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
...
llvm-svn: 140111
2011-09-20 00:18:52 +00:00
08a478063c
Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
...
llvm-svn: 140108
2011-09-20 00:10:37 +00:00
4da03f007f
Thumb CPS definition is not disassembler only.
...
llvm-svn: 140106
2011-09-20 00:00:06 +00:00
d9846bbce2
Thumb2 range check on CPS mode immediate.
...
llvm-svn: 140105
2011-09-19 23:58:31 +00:00
163be01d69
tMOVSr is not allowed in an IT block either.
...
llvm-svn: 140104
2011-09-19 23:57:20 +00:00
61e4604dd8
CPS instructions are UNPREDICTABLE inside IT blocks.
...
llvm-svn: 140102
2011-09-19 23:47:10 +00:00
fbb4481097
Tidy up comments.
...
llvm-svn: 140099
2011-09-19 23:38:34 +00:00
c4398d2c7b
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
...
llvm-svn: 140098
2011-09-19 23:36:59 +00:00
51792dcc4d
Based on the small opt Zvi's patch was trying to achieve, eliminate
...
128-bit undef subvector insertion into a 256-bit vector
llvm-svn: 140097
2011-09-19 23:36:50 +00:00
fc5451832a
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
...
llvm-svn: 140095
2011-09-19 23:31:02 +00:00
15d97fd89b
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
...
llvm-svn: 140088
2011-09-19 23:13:25 +00:00
a6e6504e2a
Thumb2 assembly parsing and encoding for UASX.
...
llvm-svn: 140085
2011-09-19 23:05:22 +00:00
f902d92fc9
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
...
llvm-svn: 140079
2011-09-19 22:34:23 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
...
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
d4a3d452d4
Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
...
PR10955 and PR10948.
llvm-svn: 140069
2011-09-19 21:29:24 +00:00
1a23fbb9fd
Tidy up a bit.
...
llvm-svn: 140050
2011-09-19 20:31:59 +00:00
8221319707
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
...
llvm-svn: 140047
2011-09-19 20:29:33 +00:00
79738336a8
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't
...
yet legal according to comments in LegalizeDAG.cpp:227.
Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.
The two failing tests reported in PR10876 pass after applying this patch.
llvm-svn: 140046
2011-09-19 20:26:02 +00:00
8c021d85a6
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
...
llvm-svn: 140041
2011-09-19 20:00:02 +00:00
40700e0992
ARM asm parsing should handle pre-indexed writeback w/o immediate.
...
For example, 'ldrb r9, [sp]!' is odd, but valid.
llvm-svn: 140035
2011-09-19 18:42:21 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
...
llvm-svn: 140032
2011-09-19 18:07:10 +00:00
264abdecf0
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
...
llvm-svn: 140029
2011-09-19 17:56:37 +00:00
763c11cc12
Fix typos in my prev commit, found by Tobi.
...
llvm-svn: 140003
2011-09-18 19:00:23 +00:00
261a10a007
setOperationAction should be done on the return value of the type, not the operands.
...
llvm-svn: 140001
2011-09-18 14:57:03 +00:00
7ae11279e9
When promoting integer vectors we often create ext-loads. This patch adds a
...
dag-combine optimization to implement the ext-load efficiently (using shuffles).
For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.
llvm-svn: 139995
2011-09-18 10:39:32 +00:00
d9d01917ee
Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC.
...
llvm-svn: 139993
2011-09-18 08:03:58 +00:00
f2b8c854dd
Synthesize x86 max/min instructions also for vectors (i.e. produce
...
maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
llvm-svn: 139986
2011-09-17 16:49:39 +00:00
4641efe304
Describe more AVX 128-bit convert instructions without patterns to have
...
mayLoad = 1
llvm-svn: 139973
2011-09-16 23:41:29 +00:00
502cd9d87a
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
...
llvm-svn: 139972
2011-09-16 23:30:01 +00:00
b925e935d7
Fix bitfield decoding based on Eli's feedback.
...
llvm-svn: 139969
2011-09-16 23:04:48 +00:00
d0c435c23c
Thumb2 assembly parsing and encoding for SUB(immediate).
...
llvm-svn: 139966
2011-09-16 22:58:42 +00:00
bcfa9a6f89
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
...
llvm-svn: 139965
2011-09-16 22:42:36 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
...
llvm-svn: 139964
2011-09-16 22:29:48 +00:00
9764bced10
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
...
llvm-svn: 139958
2011-09-16 22:17:02 +00:00
5389ed5dfb
Add mayLoad attribute to AVX convert instructions, since non of them
...
are declared with load patterns. This fix the crash in PR10941. No testcases,
since a fold is triggered and then converted back to the register form
afterwards.
llvm-svn: 139953
2011-09-16 22:02:14 +00:00
9c0b86a76d
Thumb2 assembly parsing and encoding for STR.
...
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
llvm-svn: 139949
2011-09-16 21:55:56 +00:00
5c3657a0e5
Tidy up. 80 columns.
...
llvm-svn: 139944
2011-09-16 21:09:00 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
...
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
92606beeae
Thumb2 assembly parsing and encoding for STR(immediate).
...
Add aliases for STRB/STRH while there. Tests forthcoming for those.
llvm-svn: 139942
2011-09-16 21:06:12 +00:00
2d406f02bf
Fix PR10884.
...
This PR basically reports a problem where a crash in generated code
happened due to %rbp being clobbered:
pushq %rbp
movq %rsp, %rbp
....
vmovmskps %ymm12, %ebp
....
movq %rbp, %rsp
popq %rbp
ret
Since Eric's r123367 commit, the default stack alignment for x86 32-bit
has changed to be 16-bytes. Since then, the MaxStackAlignmentHeuristicPass
hasn't been really used, but with AVX it becomes useful again, since per
ABI compliance we don't always align the stack to 256-bit, but only when
there are 256-bit incoming arguments.
ReserveFP was only used by this pass, but there's no RA target hook that
uses getReserveFP() to check for the presence of FP (since nothing was
triggering the pass to run, the uses of getReserveFP() were removed
through time without being noticed). Change this pass to use
setForceFramePointer, which is properly called by MachineFunction
hasFP method.
The testcase is very big and dependent on RA, not sure if it's worth
adding to test/CodeGen/X86.
llvm-svn: 139939
2011-09-16 20:58:28 +00:00
099c9767c3
Thumb2 assembly parsing and encoding for STMIA.
...
llvm-svn: 139938
2011-09-16 20:50:13 +00:00
8aee874bf1
Thumb2 assembly parsing and encoding for SSAX.
...
llvm-svn: 139929
2011-09-16 18:37:10 +00:00
9d9c99ff07
Thumb2 assembly parsing and encoding for SSAT.
...
llvm-svn: 139926
2011-09-16 18:32:30 +00:00
e6e7cd146a
Thumb2 assembly parsing and encoding for SRS.
...
llvm-svn: 139925
2011-09-16 18:25:22 +00:00
d73c6458de
Thumb2 assembly parsing and encoding for SMMULL.
...
llvm-svn: 139921
2011-09-16 18:05:48 +00:00
c1826a9de0
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
...
llvm-svn: 139909
2011-09-16 17:10:44 +00:00
7a0b90b187
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
...
llvm-svn: 139906
2011-09-16 16:58:03 +00:00
5e6d5cd7da
Kill some dead code.
...
llvm-svn: 139904
2011-09-16 16:45:40 +00:00
6c45b75154
Tidy up a bit.
...
llvm-svn: 139903
2011-09-16 16:39:25 +00:00
f9799d2c2d
Thumb2 assembly parsing and encoding for SMLAL.
...
llvm-svn: 139902
2011-09-16 16:38:00 +00:00
10a93ff8e0
Remove incorrect comments.
...
llvm-svn: 139877
2011-09-15 23:45:50 +00:00
a0c3b97221
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
...
llvm-svn: 139876
2011-09-15 23:38:46 +00:00
7b43568a93
Add a fixme note!
...
llvm-svn: 139872
2011-09-15 23:04:24 +00:00
b08ce9b4c4
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
...
llvm-svn: 139870
2011-09-15 22:34:29 +00:00
10f9ce2b7d
Minor cleanup.
...
llvm-svn: 139869
2011-09-15 22:26:18 +00:00
ba912e06c2
Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
...
llvm-svn: 139865
2011-09-15 22:18:49 +00:00
c69d68a150
Add the remaining AVX versions of instructions to X86InstrInfo, this
...
time for describing high latency ones and for recognizting loads
from the same base pointer
llvm-svn: 139864
2011-09-15 22:15:52 +00:00
6b302955b1
Factor out partial register update checks for some SSE instructions.
...
Also add the AVX versions and add comments!
llvm-svn: 139854
2011-09-15 21:42:23 +00:00
10725a202b
Thumb2 assembly parsing and encoding for SASX.
...
llvm-svn: 139843
2011-09-15 21:01:23 +00:00
eaa5265285
Thumb2 assembly parsing and encoding for RSB.
...
llvm-svn: 139839
2011-09-15 20:54:14 +00:00
4cbe06e7f8
Thumb2 assembly parsing and encoding for REV16/REVSH.
...
llvm-svn: 139828
2011-09-15 19:46:13 +00:00
d1814791ad
Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
...
llvm-svn: 139820
2011-09-15 18:36:29 +00:00
fa1ca3070b
Change all checks regarding the presence of any SSE level to always
...
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite
llvm-svn: 139817
2011-09-15 18:27:36 +00:00
62d79875d3
Enable SSEDomainFix pass for AVX mode.
...
llvm-svn: 139816
2011-09-15 18:27:32 +00:00
ab154f0b65
Thumb2 assembly parsing and encoding for REV.
...
llvm-svn: 139813
2011-09-15 18:13:30 +00:00
d93c4ece15
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
...
llvm-svn: 139796
2011-09-15 16:16:50 +00:00
22f76390a6
Thumb2 push/pop mnemonic recognition.
...
llvm-svn: 139794
2011-09-15 15:55:04 +00:00
da5f010177
Fix the code creating VZEXT_LOAD so that it creates the right memoperand. Issue spotted in -debug output. I can't think of any practical effects at the moment, but it might matter if we start doing more aggressive alias analysis in CodeGen.
...
llvm-svn: 139758
2011-09-14 23:42:45 +00:00
801e06b768
Thumb2 assembly parsing and encoding for PKH.
...
llvm-svn: 139754
2011-09-14 23:16:41 +00:00
521526845c
ARMv7a has the PKH instructions.
...
llvm-svn: 139753
2011-09-14 23:16:34 +00:00
25ca53b268
ARM tighten up the register classes for the PKH instructions.
...
llvm-svn: 139748
2011-09-14 22:52:14 +00:00
d7791b961c
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
...
llvm-svn: 139747
2011-09-14 22:46:14 +00:00
752d6fd529
Thumb2 assembly parsing and encoding for MVN.
...
llvm-svn: 139739
2011-09-14 21:24:41 +00:00
f1e384421a
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
...
llvm-svn: 139736
2011-09-14 21:06:21 +00:00
9c8b9932d6
Thumb2 assembly parsing and encoding for MUL.
...
llvm-svn: 139735
2011-09-14 21:00:40 +00:00
0ecd395095
Thumb2 assembly parsing and encoding for MSR/MRS.
...
Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
18b8b17579
Thumb2 assembly parsing for MOV in IT block.
...
Select the right 16 vs. 32 bit encoding in an IT block.
llvm-svn: 139714
2011-09-14 19:12:11 +00:00
3ac26b138b
ARM fix assembly parser handling of ranges in register lists.
...
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
llvm-svn: 139707
2011-09-14 18:08:35 +00:00
3efff6c9f8
Add comment.
...
llvm-svn: 139699
2011-09-14 17:22:51 +00:00
ee8157cb41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
...
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
96e00e5a24
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
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llvm-svn: 139690
2011-09-14 05:55:28 +00:00
483c269a33
One more patch towards JIT support for Mips.
...
- Add TSFlags for the instruction formats. The idea here is to use
as much encoding as possible from getBinaryCodeForInstr, and having
TSFLags formats for that would make it easier to encode most part
of the instructions (since Mips encodings are pretty straightforward)
- Improve the mips mechanism for compilation callback
- Add Mips specific code for invalidating the instruction cache
- Next patch will address wrong tablegen encoding
Commit msg added by my own but the patch is from Sasa Stankovic.
llvm-svn: 139688
2011-09-14 03:00:41 +00:00
d560b8c8e9
Teach the foldable tables about 128-bit AVX instructions and make the
...
alignment check for 256-bit classes more strict. There're no testcases
but we catch more folding cases for AVX while running single and multi
sources in the llvm testsuite.
Since some 128-bit AVX instructions have different number of operands
than their SSE counterparts, they are placed in different tables.
256-bit AVX instructions should also be added in the table soon. And
there a few more 128-bit versions to handled, which should come in
the following commits.
llvm-svn: 139687
2011-09-14 02:36:58 +00:00
333a59eced
Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
...
llvm-svn: 139686
2011-09-14 02:36:14 +00:00
75461af000
Remove unnecessary scope resolution operator.
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llvm-svn: 139656
2011-09-13 22:56:44 +00:00
7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
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llvm-svn: 139639
2011-09-13 20:46:26 +00:00
e3a6a82f16
There's only 16 regs legal in a register list.
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llvm-svn: 139637
2011-09-13 20:35:57 +00:00
e7e2aca322
Tidy up a few 80 column violations.
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llvm-svn: 139636
2011-09-13 20:30:37 +00:00
50087ea1ec
Tidy up a bit.
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llvm-svn: 139635
2011-09-13 20:27:44 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
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tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
9cfbeaff15
swap vselect operand order - pr10907
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llvm-svn: 139630
2011-09-13 19:56:38 +00:00
03d6002d68
Add versions 256-bit versions of alignedstore and alignedload, to be
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more strict about the alignment checking. This was found by inspection
and I don't have any testcases so far, although the llvm testsuite runs
without any problem.
llvm-svn: 139625
2011-09-13 19:33:03 +00:00
56d9b51caf
Revert the remaining part of r139528. According to PR10907 the bug seems
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to be in the VSELECT operands order, so I'll leave the fix for Nadav.
llvm-svn: 139624
2011-09-13 19:33:00 +00:00
52202fbf2d
Add vselect target support for targets that do not support blend but do support
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xor/and/or (For example SSE2).
llvm-svn: 139623
2011-09-13 19:17:42 +00:00
b491f48aba
Support for PSP is gone too.
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llvm-svn: 139622
2011-09-13 18:55:33 +00:00
44ae2da4ec
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
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llvm-svn: 139610
2011-09-13 17:59:19 +00:00
b0e99ef8f0
It is not necessary to search for mipsallegrex in target triple string.
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llvm-svn: 139607
2011-09-13 17:35:28 +00:00
c3c60a0882
Fix encoding of Thumb2 shifted register operands with RRX shifts.
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llvm-svn: 139606
2011-09-13 17:34:32 +00:00
8dd7bbcc80
Only disassembler instructions with vvvv != 1111 if the instruction actually uses the vvvv field to encode an operand. Fixes PR10851.
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llvm-svn: 139591
2011-09-13 07:37:44 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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llvm-svn: 139588
2011-09-13 06:54:58 +00:00
b7ae29e404
Fix encoding of VMOVDQU to not simultaneously be 'TB OpSize' and 'XS'. 'XS' is correct and seems to have been taking priority.
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llvm-svn: 139587
2011-09-13 06:39:34 +00:00
12ea1b72a4
Zap some junk from the ARM instruction descriptions.
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llvm-svn: 139575
2011-09-13 02:29:58 +00:00
d68a727bd0
Fix the assembler strings for a couple of atomic instructions. Doesn't really matter much in practice, but it's a bit cleaner.
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llvm-svn: 139563
2011-09-13 00:27:04 +00:00
3337e396c8
Tidy up a bit.
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llvm-svn: 139559
2011-09-12 23:36:42 +00:00
ff8d8a830e
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
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destination types are equal!
llvm-svn: 139553
2011-09-12 22:59:23 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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llvm-svn: 139542
2011-09-12 21:28:46 +00:00
973d2921e8
Revert the wrong part of r139528, and fix testcases.
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llvm-svn: 139541
2011-09-12 21:24:07 +00:00
4a9eb5f8dc
Fix encoding of PC-relative LDRSHW with an immediate offset.
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llvm-svn: 139537
2011-09-12 20:36:51 +00:00
3543398bcf
There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
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llvm-svn: 139531
2011-09-12 20:07:22 +00:00
be7a086f58
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
...
However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
llvm-svn: 139528
2011-09-12 19:30:40 +00:00
f6382979f2
Organize a bit the operand names for CMPPS and CMPPD
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llvm-svn: 139527
2011-09-12 19:30:36 +00:00
2e4bee16bb
Realign BLEND patterns to match the general style for patterns in .td file.
...
llvm-svn: 139526
2011-09-12 19:30:33 +00:00
9c9f64918c
Fix 80-columns
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llvm-svn: 139525
2011-09-12 19:30:29 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
97a2a5c4dc
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
llvm-svn: 139495
2011-09-12 14:43:23 +00:00
dcde6e30b9
Mark LDWCP as having no side effects.
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llvm-svn: 139494
2011-09-12 14:41:31 +00:00
c0c71e162a
Format patterns, remove unused X86blend patterns
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llvm-svn: 139491
2011-09-12 08:41:50 +00:00
48f2b36911
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
...
llvm-svn: 139486
2011-09-11 23:19:54 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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llvm-svn: 139485
2011-09-11 21:41:45 +00:00
b873b18721
CR fixes per Bruno's request.
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Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
llvm-svn: 139479
2011-09-11 15:02:23 +00:00
7f50e00203
r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase.
...
llvm-svn: 139458
2011-09-10 02:01:42 +00:00
74996f2a79
Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and
...
lib/ExecutionEngine/MCJIT/MCJIT.cpp from:
assert("error");
to:
assert(0 && "error");
llvm-svn: 139456
2011-09-10 01:42:07 +00:00
d9917bef6c
Fixed an assert from:
...
assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
llvm-svn: 139454
2011-09-10 01:26:21 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
eb3f0fbdce
Fix an ambiguously nested if.
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llvm-svn: 139431
2011-09-09 23:13:02 +00:00
93cd31869b
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
...
llvm-svn: 139429
2011-09-09 23:05:14 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
8b983d9773
O64 will not be supported.
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llvm-svn: 139421
2011-09-09 22:22:48 +00:00
be159b5f2d
Make F31 and D15 non-reserved registers.
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llvm-svn: 139420
2011-09-09 22:11:26 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
9d5f9278e3
Mips32 does not reserve even-numbered floating point registers.
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llvm-svn: 139412
2011-09-09 21:31:46 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
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llvm-svn: 139405
2011-09-09 20:45:50 +00:00
de838daefd
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
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llvm-svn: 139400
2011-09-09 20:29:17 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
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llvm-svn: 139399
2011-09-09 20:24:45 +00:00
779a2bee7b
Thumb2 assembly parsing and encoding for LDRSB.
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llvm-svn: 139389
2011-09-09 19:42:40 +00:00
d22a1c6c95
Drop support for Allegrex. Allegrex implements a variant of Mips2.
...
llvm-svn: 139383
2011-09-09 19:00:51 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
...
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
5d5134014f
Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.
...
llvm-svn: 139353
2011-09-09 05:40:53 +00:00
df1df7edf1
Change default target architecture from Mips1 to Mips32r1 in preparation for
...
removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
llvm-svn: 139344
2011-09-09 01:13:27 +00:00
83dee99c1b
80 columns.
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llvm-svn: 139339
2011-09-09 00:13:35 +00:00
33d39536e6
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
...
llvm-svn: 139329
2011-09-08 22:48:37 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
...
llvm-svn: 139328
2011-09-08 22:42:49 +00:00
b5df62036b
Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types.
...
llvm-svn: 139324
2011-09-08 22:17:35 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
...
Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
46b9cde019
Add a AVX version of a simple i64 -> f64 bitcast. This could be
...
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
llvm-svn: 139320
2011-09-08 21:52:33 +00:00
23eb5265b4
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
...
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
llvm-svn: 139311
2011-09-08 18:35:57 +00:00
fb113a0051
Add AVX versions of blend vector operations and fix some issues noticed
...
in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
llvm-svn: 139305
2011-09-08 18:05:08 +00:00
ea8d803bb0
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
llvm-svn: 139304
2011-09-08 18:05:02 +00:00
2550ba2a27
Add X86-SSE4 codegen support for vector-select.
...
llvm-svn: 139285
2011-09-08 08:11:19 +00:00
3343da5424
Thumb2 assembly parsing and encoding for LDR post-indexed.
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More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
c086f689f8
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
...
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
f174959286
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
...
llvm-svn: 139268
2011-09-08 00:11:18 +00:00
2392c53e73
Thumb2 assembly parsing and encoding for LDRBT.
...
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
e0ebc1c396
Thumb2 assembly parsing and encoding for LDR(register).
...
llvm-svn: 139264
2011-09-07 23:10:15 +00:00
2e63f6eac0
Add two notes for correlated-expression optimizations.
...
llvm-svn: 139263
2011-09-07 22:49:26 +00:00
c8e3656b43
Thumb2 assembly parsing and encoding for LDRB(immediate).
...
llvm-svn: 139258
2011-09-07 21:41:25 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
...
llvm-svn: 139256
2011-09-07 21:10:42 +00:00
5bfa8bab06
Thumb2 parsing and encoding for LDR(immediate).
...
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
llvm-svn: 139254
2011-09-07 20:58:57 +00:00
1c7406767e
Thumb2 parsing and encoding for LDMDB.
...
llvm-svn: 139251
2011-09-07 19:57:53 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
...
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
02f2f89a98
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
...
This isn't exactly ideal, but it is good enough for the moment.
llvm-svn: 139245
2011-09-07 18:48:32 +00:00
42b5570850
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
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There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
llvm-svn: 139243
2011-09-07 18:39:47 +00:00
a31f223af8
Thumb2 parsing and encoding for LDMIA.
...
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
llvm-svn: 139242
2011-09-07 18:05:34 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
4c493e8050
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
...
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
4ff93f3bc2
Thumb2 use 'ldm' as default mnemonic.
...
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
llvm-svn: 139234
2011-09-07 16:22:42 +00:00
6559656e73
Detect attempt to use segmented stacks on non ELF systems and error
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(not assert) early.
llvm-svn: 139233
2011-09-07 16:10:57 +00:00
39c6e1d66d
Better diagnostic location information for mnemonic suffices.
...
llvm-svn: 139232
2011-09-07 16:06:04 +00:00
226c4ed92a
Reenable compact unwind by default. However, also emit the old version of unwind
...
information for older linkers.
llvm-svn: 139206
2011-09-06 23:47:14 +00:00
5b5c953b07
ISB is HasDB, not just HasV7.
...
llvm-svn: 139202
2011-09-06 23:09:19 +00:00
83a6188f18
Thumb2 parsing and encoding for ISB.
...
llvm-svn: 139200
2011-09-06 22:53:27 +00:00
e95f46384e
Thumb2 parsing and encoding for DMB.
...
llvm-svn: 139193
2011-09-06 22:14:58 +00:00
c048b905b4
Thumb2 parsing and encoding for DBG.
...
llvm-svn: 139191
2011-09-06 22:06:40 +00:00
565e2f5752
Thumb2 parsing and encoding for CMN and CMP.
...
llvm-svn: 139188
2011-09-06 21:44:58 +00:00
fc4b343dda
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
...
llvm-svn: 139179
2011-09-06 20:53:37 +00:00
803898f119
Thumb2 parsing and encoding for CLREX.
...
llvm-svn: 139172
2011-09-06 20:27:04 +00:00
9d96c94278
Fix comment. Noticed by Duncan.
...
llvm-svn: 139161
2011-09-06 19:29:31 +00:00
f2641e1bc1
Add codegen support for vector select (in the IR this means a select
...
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
0b758ed6ba
Fix fall outs from my recent change on how carry bit is modeled during isel.
...
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
llvm-svn: 139157
2011-09-06 18:52:20 +00:00
f471ac3c72
ARM .code directive should always go to the streamer.
...
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
llvm-svn: 139155
2011-09-06 18:46:23 +00:00
db5823dc77
Fix style issues and typos found by Duncan.
...
llvm-svn: 139154
2011-09-06 18:43:08 +00:00
50ef7611aa
Atomic pseudos don't use (as in read) CPSR. They clobber it.
...
llvm-svn: 139148
2011-09-06 17:40:35 +00:00
a098436b32
Split the init.trampoline intrinsic, which currently combines GCC's
...
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
llvm-svn: 139140
2011-09-06 13:37:06 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
...
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
df06b6e069
Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger!
...
llvm-svn: 139124
2011-09-05 18:50:59 +00:00
f1a5f57d2f
Fix typo in comment.
...
llvm-svn: 139122
2011-09-05 18:35:03 +00:00
7859d2e148
Use internal storage for command line option.
...
llvm-svn: 139079
2011-09-03 03:45:06 +00:00
07d9914620
Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends
...
the cycle of missing AVX counterparts of already present SSE* patterns
llvm-svn: 139073
2011-09-03 00:47:08 +00:00
1d5c2d9227
Add AVX version of a SSE4.1 VPBLENDVB pattern
...
llvm-svn: 139072
2011-09-03 00:47:05 +00:00
212a8c4357
Add AVX versions of SSE4.1 EXTRACTPS patterns
...
llvm-svn: 139071
2011-09-03 00:47:03 +00:00
3d581a36b6
Add AVX versions for SSE4.1 MOVZX* patterns
...
llvm-svn: 139070
2011-09-03 00:47:01 +00:00
6d701fcef0
Add one more AVX pattern for MOVZPQILo2PQI
...
llvm-svn: 139069
2011-09-03 00:46:58 +00:00
9923c51564
Move PUNPCKLQDQ splat pattern close to the instruction definition and
...
duplicate it for AVX mode.
llvm-svn: 139068
2011-09-03 00:46:56 +00:00
96b11f39e2
Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
...
llvm-svn: 139067
2011-09-03 00:46:54 +00:00
9a0da1e57a
Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
...
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
llvm-svn: 139066
2011-09-03 00:46:51 +00:00
903952223a
Enforce subtarget checks in a few places to be explicit when the
...
pattern should be matched
llvm-svn: 139065
2011-09-03 00:46:49 +00:00
521b0cfdc6
Tidy up code moving patterns to their appropriate place!
...
llvm-svn: 139064
2011-09-03 00:46:47 +00:00
aad5e50ded
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
...
it!
llvm-svn: 139063
2011-09-03 00:46:45 +00:00
d893fc92af
Teach X86FastISel to use AVX versions of instructions when possible
...
llvm-svn: 139062
2011-09-03 00:46:42 +00:00
006c9371a1
Fix 80-column and style
...
llvm-svn: 139061
2011-09-03 00:46:40 +00:00
dbb40015ff
Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
...
OptForSize pattern
llvm-svn: 139060
2011-09-03 00:46:38 +00:00
1f72dd40c7
Pseudo CMOV instructions don't clobber EFLAGS.
...
The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
llvm-svn: 139057
2011-09-02 23:52:55 +00:00
f08354d183
Check for EFLAGS live-out before clobbering it.
...
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
llvm-svn: 139056
2011-09-02 23:52:52 +00:00
d0c8a31c8b
Use existing function.
...
llvm-svn: 139055
2011-09-02 23:52:49 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
38019e3188
Remove unused variables.
...
llvm-svn: 139047
2011-09-02 22:41:25 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
05dec8b122
Tidy up. Formatting.
...
llvm-svn: 139024
2011-09-02 18:46:15 +00:00
0a57375a28
Tidy up. 80 columns.
...
llvm-svn: 139022
2011-09-02 18:43:25 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
4e1d018935
Revert r138826 until PR10834 can be fixed.
...
llvm-svn: 139018
2011-09-02 18:15:04 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
f5769c1070
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
...
llvm-svn: 139004
2011-09-02 10:05:01 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
...
llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
...
llvm-svn: 138980
2011-09-01 23:23:50 +00:00
6397051ece
Don't drop alignment info on local common symbols.
...
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
d7776ed030
Null-initialize to shut up -Wuninitialized warnings.
...
llvm-svn: 138974
2011-09-01 22:27:41 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
f61d1c072e
Fix vbroadcast matching logic to early unmatch if the node doesn't have
...
only one use. Fix PR10825.
llvm-svn: 138951
2011-09-01 18:15:06 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
...
llvm-svn: 138948
2011-09-01 18:02:14 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
17847ae757
Fixup for functions that return a bool.
...
llvm-svn: 138918
2011-08-31 23:49:05 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
...
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
...
llvm-svn: 138910
2011-08-31 22:00:41 +00:00
99bc84662f
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
...
llvm-svn: 138898
2011-08-31 21:17:31 +00:00
a0d85139e5
Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS
...
llvm-svn: 138897
2011-08-31 21:15:32 +00:00
21a180367b
Move MOVAPS,MOVUPS patterns close to the instructions definition
...
llvm-svn: 138896
2011-08-31 21:15:29 +00:00
941001312a
Remove "_Int" forms of MOVUPSmr and MOVAPSmr
...
llvm-svn: 138895
2011-08-31 21:15:22 +00:00
a455a0b1e7
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
939cd21248
When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
...
<rdar://problem/10046188>
llvm-svn: 138885
2011-08-31 20:00:11 +00:00
cfa9421e16
Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.
...
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.
llvm-svn: 138879
2011-08-31 18:39:39 +00:00
5c160fd243
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
c61fc8f301
tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).
...
llvm-svn: 138873
2011-08-31 18:29:05 +00:00
af8c3cc710
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
1ccecbb9d3
64-bit atomic cmpxchg for ARM.
...
llvm-svn: 138868
2011-08-31 17:52:22 +00:00
1fcf140ae3
Fix typo. Patch by Liu.
...
llvm-svn: 138866
2011-08-31 17:49:04 +00:00
6d606fbe14
Tweak Thumb1 ADD encoding selection a bit.
...
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
llvm-svn: 138862
2011-08-31 17:07:33 +00:00
cd893390f5
Put VMOVS widening under a command line option, off by default.
...
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
llvm-svn: 138861
2011-08-31 17:00:02 +00:00
6e31dfea35
Spelling and grammar fixes to problems found by Duncan.
...
llvm-svn: 138858
2011-08-31 16:43:33 +00:00
635d9692b6
Make sure we don't crash when -miphoneos-version-min is specified on x86. Hopefully this will fix gcc testsuite failures.
...
llvm-svn: 138856
2011-08-31 16:19:51 +00:00
72d1d5e193
Rework this conditional a bit.
...
Patch by Sanjoy Das
llvm-svn: 138853
2011-08-31 04:17:21 +00:00
9fc6b8be03
- Move all MOVSS and MOVSD patterns close to their definitions
...
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
and update a testcase to check it properly
llvm-svn: 138851
2011-08-31 03:04:20 +00:00
aa1daa63da
Remove unnecessary AVX checks
...
llvm-svn: 138850
2011-08-31 03:04:14 +00:00
db520db514
Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,
...
whenever AVX is enabled.
llvm-svn: 138849
2011-08-31 03:04:09 +00:00
cb1e5bae4c
Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
...
llvm-svn: 138848
2011-08-31 02:05:24 +00:00
2c7bb52f56
Some minor cleanups for r138845.
...
llvm-svn: 138846
2011-08-31 00:41:05 +00:00
c3f9c4a852
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
...
llvm-svn: 138845
2011-08-31 00:31:29 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
fdf3cd7f2b
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
...
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
d16fb43b1f
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
...
llvm-svn: 138835
2011-08-30 22:10:03 +00:00
543c89fb15
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
...
llvm-svn: 138834
2011-08-30 22:03:20 +00:00
1732c2ebf6
Clean up whitespace.
...
llvm-svn: 138833
2011-08-30 21:58:18 +00:00
6470e07e20
Fix off-by-one error Benjamin noticed.
...
llvm-svn: 138832
2011-08-30 21:23:24 +00:00
7a9c3033a4
Enable compact unwind info by default. This only applies to Darwin when CFI is
...
disabled.
llvm-svn: 138826
2011-08-30 20:54:11 +00:00
065c35726f
Fix C++0x narrowing errors when char is unsigned.
...
In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.
llvm-svn: 138825
2011-08-30 20:53:29 +00:00
94d3253626
Adds support for variable sized allocas. For a variable sized alloca,
...
code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.
Patch by Sanjoy Das.
llvm-svn: 138818
2011-08-30 19:47:04 +00:00
3353017668
Adds a SelectionDAG node X86SegAlloca which will be custom lowered
...
from DYNAMIC_STACKALLOC.
Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added. They
will be custom emitted to inject the actual stack handling code.
Patch by Sanjoy Das.
llvm-svn: 138814
2011-08-30 19:43:21 +00:00
c21742112b
Emit segmented-stack specific code into function prologues for
...
X86. Modify the pass added in the previous patch to call this new
code.
This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required
Patch by Sanjoy Das.
llvm-svn: 138812
2011-08-30 19:39:58 +00:00
ddc0f8779e
Command line option to enable support for segmented stacks:
...
-segmented-stacks.
Patch by Sanjoy Das!
llvm-svn: 138811
2011-08-30 19:29:02 +00:00
e6fba77971
Follow up to r138791.
...
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
llvm-svn: 138810
2011-08-30 19:09:48 +00:00
71038e7021
Set CR1EQ only when lowering vararg floating arguments (not any vararg
...
arguments as before), unset CR1EQ otherwise.
llvm-svn: 138802
2011-08-30 17:04:16 +00:00
87cec4d172
Fix typos in SPUMCTargetDesc.h
...
Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138799
2011-08-30 07:27:02 +00:00
02ad655446
Fix typo in BlackfinFrameLowering.h
...
Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138798
2011-08-30 07:26:11 +00:00
9668f2d775
Fix typo in MSP430MCTargetDesc.h.
...
Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138797
2011-08-30 07:24:47 +00:00
8c54533f99
Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com)
...
llvm-svn: 138796
2011-08-30 07:23:29 +00:00
e891654a58
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
...
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
llvm-svn: 138791
2011-08-30 01:34:54 +00:00
6e59d5c916
Revert 138781. It's not playing nicely with the immediate forms for ADC.
...
llvm-svn: 138782
2011-08-29 23:24:15 +00:00
19a75f075d
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
...
llvm-svn: 138781
2011-08-29 23:20:54 +00:00
3e0aa03fe9
Add missing encoding information for some of the GPR<->FP register moves.
...
llvm-svn: 138780
2011-08-29 23:15:25 +00:00
ed16ec4248
Thumb2 parsing and encoding for IT blocks.
...
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
850b9a9a84
Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802.
...
llvm-svn: 138768
2011-08-29 21:15:46 +00:00
243274c789
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
...
llvm-svn: 138766
2011-08-29 21:14:19 +00:00
32ac76616e
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
...
llvm-svn: 138760
2011-08-29 20:42:00 +00:00
4d5c8f894d
addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.
...
llvm-svn: 138758
2011-08-29 20:16:50 +00:00
967674d26c
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
7dfa791f4f
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
...
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
6314343333
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
...
llvm-svn: 138746
2011-08-29 17:59:41 +00:00
50e0170fa5
Move non-intruction patterns to a more appropriate place!
...
llvm-svn: 138744
2011-08-29 17:51:24 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
7ea09c9462
Remove premature previous commit.
...
llvm-svn: 138725
2011-08-28 14:52:51 +00:00
f786bae6ac
Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
...
llvm-svn: 138723
2011-08-28 13:07:57 +00:00
61a1ff543c
Silence GCC warnings and make an array const.
...
llvm-svn: 138706
2011-08-27 17:36:14 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
b9d4e37776
ARM assembly parsing tweak for pldw.
...
llvm-svn: 138669
2011-08-26 22:21:51 +00:00
240d20af79
Spelling fail.
...
llvm-svn: 138667
2011-08-26 21:47:57 +00:00
3d1eac85c3
Thumb2 assembler parsing and encoding of IT instruction.
...
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
llvm-svn: 138665
2011-08-26 21:43:41 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
...
llvm-svn: 138660
2011-08-26 21:21:21 +00:00
fd60f60ed1
Fix ARM codegen breakage caused by r138653.
...
llvm-svn: 138657
2011-08-26 21:12:37 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
5658b49f64
Update for feedback from Jim.
...
llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
db6f646ec3
Don't insert branch hint lables that are never used.
...
llvm-svn: 138630
2011-08-26 10:14:56 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
...
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
...
llvm-svn: 138623
2011-08-26 04:49:29 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
...
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
ed834810be
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138592
2011-08-25 22:23:58 +00:00
64bfca1b60
Remove stray fullstop.
...
llvm-svn: 138589
2011-08-25 21:46:20 +00:00
8347b86293
Add support for AVX 256-bit version of MOVDDUP!
...
llvm-svn: 138588
2011-08-25 21:40:37 +00:00
388eacee2c
Make isMOVDDUP mask check more strict and update comments!
...
llvm-svn: 138587
2011-08-25 21:40:34 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
...
rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
f7ecc16c96
whitespace
...
llvm-svn: 138566
2011-08-25 17:40:54 +00:00
1c171b121a
Explicitly disallow predication in Thumb1 assembly.
...
llvm-svn: 138562
2011-08-25 17:23:55 +00:00
14380ff9a0
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
...
llvm-svn: 138553
2011-08-25 08:11:01 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
llvm-svn: 138551
2011-08-25 06:57:46 +00:00
296256fb32
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
...
llvm-svn: 138546
2011-08-25 02:58:26 +00:00
54366cc332
Add memory version of SHUFPD to mask decoding!
...
llvm-svn: 138545
2011-08-25 02:58:21 +00:00
9dad430486
Hide -global-merge option.
...
llvm-svn: 138540
2011-08-25 01:22:49 +00:00
f066b2fe99
Add a command line option to disable global merge pass.
...
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
3ca20e64ac
Remove a out-of-place comment.
...
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
50d74211df
Create a section for non-instructions patterns in the beginning of the
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file, and move more code around!
llvm-svn: 138521
2011-08-24 23:18:11 +00:00
2fb51d38e6
Move code around!
...
llvm-svn: 138520
2011-08-24 23:18:09 +00:00
fb702fe8d6
Organize UNPCK* patterns, also add remaining for AVX.
...
llvm-svn: 138519
2011-08-24 23:18:06 +00:00
9ade17b7f2
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
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the missing ones for AVX.
llvm-svn: 138518
2011-08-24 23:18:04 +00:00
c1e1e7ab97
Organize and tidy up MOVDDUP section. Also update comments!
...
llvm-svn: 138517
2011-08-24 23:18:02 +00:00
813891a215
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
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pattern for 128-bit AVX mode.
llvm-svn: 138516
2011-08-24 23:17:59 +00:00
9566a66a7c
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
llvm-svn: 138515
2011-08-24 23:17:57 +00:00
2953d7b320
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
llvm-svn: 138514
2011-08-24 23:17:55 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
9c73a57b20
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
...
llvm-svn: 138505
2011-08-24 22:33:28 +00:00
21a60b6f90
ARM asm backend initialize isThumbMode based on target triple.
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llvm-svn: 138501
2011-08-24 22:27:35 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
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We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
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Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
38cd821dc4
Fix whitespace.
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llvm-svn: 138487
2011-08-24 21:17:30 +00:00
342e8df0e0
Basic x86 code generation for atomic load and store instructions.
...
llvm-svn: 138478
2011-08-24 20:50:09 +00:00
af2f827a2c
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
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rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
ce02840633
Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138461
2011-08-24 18:48:33 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
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rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
a281f2d07d
Thumb add SP assembly syntax fix.
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llvm-svn: 138448
2011-08-24 18:04:27 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
...
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
6e3c83eb1c
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
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variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
de92622aa5
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
...
llvm-svn: 138427
2011-08-24 06:14:18 +00:00
9e9f2ce32d
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
...
permutations. Also tidy up some patterns and make them close to their
instruction definition!
llvm-svn: 138392
2011-08-23 22:06:37 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
...
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
...
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
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from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
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llvm-svn: 138360
2011-08-23 19:49:10 +00:00
4c8ff77f1b
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
...
llvm-svn: 138354
2011-08-23 19:01:24 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
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llvm-svn: 138348
2011-08-23 18:39:41 +00:00
d80d169a04
Thumb parsing and encoding for STM.
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llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
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llvm-svn: 138344
2011-08-23 18:13:04 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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llvm-svn: 138341
2011-08-23 17:51:38 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
...
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
e364ad540a
Clean up Thumb load/store multiple definitions.
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There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
llvm-svn: 138338
2011-08-23 17:41:15 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
6612e35b0d
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
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llvm-svn: 138321
2011-08-23 04:36:33 +00:00
2a3ffb5d97
Introduce a pass to insert vzeroupper instructions to avoid AVX to
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SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.
llvm-svn: 138317
2011-08-23 01:14:17 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
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llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
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llvm-svn: 138308
2011-08-22 23:47:13 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
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llvm-svn: 138306
2011-08-22 23:44:04 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
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llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
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llvm-svn: 138300
2011-08-22 23:27:47 +00:00
bfeb4f78af
Revert r138278 now that r138289 has fixed the root issue.
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llvm-svn: 138299
2011-08-22 23:25:48 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
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llvm-svn: 138298
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
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llvm-svn: 138295
2011-08-22 23:17:34 +00:00
2844a81079
Match operand names to provide correct decoding for Thumb2 SMULL.
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llvm-svn: 138294
2011-08-22 23:16:48 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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llvm-svn: 138292
2011-08-22 23:10:16 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
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llvm-svn: 138287
2011-08-22 23:01:07 +00:00
9dc808e74d
X86: Add some operand types required to identify calls.
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llvm-svn: 138285
2011-08-22 22:55:32 +00:00
ca2ffad8b1
Temporarilly mark tMUL as not commutable.
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It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
llvm-svn: 138278
2011-08-22 22:00:18 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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llvm-svn: 138273
2011-08-22 21:34:00 +00:00
74f090d44c
Add support for breaking 256-bit int VETCC into two 128-bit ones,
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avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.
llvm-svn: 138271
2011-08-22 20:31:04 +00:00
6e62ca940a
Add 128-bit AVX codegen for PCMP* family of integer instructions
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llvm-svn: 138270
2011-08-22 20:31:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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llvm-svn: 138269
2011-08-22 20:27:12 +00:00
5c932b24be
Tighten up ARM reglist validation a bit.
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llvm-svn: 138258
2011-08-22 18:50:36 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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llvm-svn: 138251
2011-08-22 18:22:06 +00:00
6caa557ae6
Clean up predicates on ARM target instruction aliases.
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llvm-svn: 138249
2011-08-22 18:04:24 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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llvm-svn: 138246
2011-08-22 17:56:58 +00:00
5800a8c3ad
Cast through intptr_t, ISO C++ requires it.
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llvm-svn: 138186
2011-08-20 02:22:42 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
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llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
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llvm-svn: 138174
2011-08-20 00:40:14 +00:00
59015c8b17
Add <imp-def> operands to QQ and QQQQ stack loads.
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This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
llvm-svn: 138164
2011-08-20 00:17:45 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
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Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
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The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
419fd4f315
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
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needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
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llvm-svn: 138131
2011-08-19 22:51:03 +00:00
8022015a16
Fix NEG alias
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llvm-svn: 138125
2011-08-19 22:30:58 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
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llvm-svn: 138124
2011-08-19 22:30:46 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
066e9ec1e4
Update tests.
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llvm-svn: 138116
2011-08-19 22:19:48 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
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llvm-svn: 138108
2011-08-19 22:07:46 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
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llvm-svn: 138076
2011-08-19 20:46:54 +00:00
dbb60f960a
Tidy up. Tab character.
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llvm-svn: 138072
2011-08-19 20:30:19 +00:00
9c92049069
Tab characters.
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llvm-svn: 138066
2011-08-19 19:41:46 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
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llvm-svn: 138063
2011-08-19 19:29:25 +00:00
7c4739da3c
Thumb assembly parsing and encoding for LDRSB and LDRSH.
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llvm-svn: 138061
2011-08-19 19:17:58 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
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llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
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llvm-svn: 138059
2011-08-19 18:49:59 +00:00
181d2f92b5
Thumb assembly parsing and encoding for LDR(literal).
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llvm-svn: 138052
2011-08-19 18:20:48 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
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llvm-svn: 138050
2011-08-19 18:13:48 +00:00
7473329725
Use helper function to check for low registers.
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llvm-svn: 138048
2011-08-19 17:57:22 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
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llvm-svn: 138047
2011-08-19 17:55:24 +00:00
e93807049b
Add explanatory comment.
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llvm-svn: 138042
2011-08-19 16:52:32 +00:00
024d2614b6
Have SPU backend use the external TCE scheduler, if the library is loaded as a
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module.
Patch by Pekka Jääskeläinen.
llvm-svn: 138037
2011-08-19 10:50:24 +00:00
ba6c2a52c7
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
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llvm-svn: 138034
2011-08-19 05:28:50 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
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implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
4938edb02c
Make a bunch of symbols private.
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llvm-svn: 138025
2011-08-19 01:42:18 +00:00
5647d84aa4
Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands
...
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.
Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.
There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)
llvm-svn: 138012
2011-08-18 23:59:21 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
5d2db89ba6
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
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llvm-svn: 137997
2011-08-18 22:15:25 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
73d78b7ab1
Make IsShiftedMask a static function rather than defining it in an
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anonymous namespace.
llvm-svn: 137975
2011-08-18 20:07:42 +00:00
4f240a1fd5
Thumb assembly parsing and encoding for CMP.
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llvm-svn: 137963
2011-08-18 18:08:29 +00:00
8a6bed863a
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
...
llvm-svn: 137956
2011-08-18 17:51:36 +00:00
f00b9ccd22
ARM Thumb blx instruction fixup has same data range as bl.
...
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
llvm-svn: 137947
2011-08-18 16:57:50 +00:00
8fa3f6a2b4
80 columns.
...
llvm-svn: 137946
2011-08-18 16:50:45 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
...
llvm-svn: 137943
2011-08-18 16:30:49 +00:00
6ddb568ab8
Add missing 'break'.
...
llvm-svn: 137941
2011-08-18 16:08:39 +00:00
56f3b70225
Add intrinsics for SETEV, GETED, GETET.
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llvm-svn: 137938
2011-08-18 13:00:48 +00:00
3c7d6eb64c
Cleanup vector logical ops in AVX and add use int versions for simple
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v2i64
llvm-svn: 137919
2011-08-18 02:11:34 +00:00
50aafeaa2c
Remove extraneous newline from operand print method. PR10569.
...
llvm-svn: 137900
2011-08-17 23:23:07 +00:00
23b729eeba
Clean up patterns for Thumb1 system instructions.
...
llvm-svn: 137897
2011-08-17 23:08:57 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
...
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
...
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
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llvm-svn: 137889
2011-08-17 22:49:09 +00:00
1a87fcb9ba
Fix PR10688. Add support for spliting 256-bit vector shifts when the
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shift amount is variable
llvm-svn: 137885
2011-08-17 22:12:20 +00:00
d14b70d00b
Tidy up. 80 columns.
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llvm-svn: 137881
2011-08-17 21:58:18 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
...
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
854fe433d4
Fix predicate for imm1_32
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llvm-svn: 137865
2011-08-17 21:01:11 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
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llvm-svn: 137864
2011-08-17 20:37:40 +00:00
3b5a69cc45
80 columns.
...
llvm-svn: 137857
2011-08-17 19:55:51 +00:00
8637523886
Tidy up.
...
llvm-svn: 137856
2011-08-17 19:53:53 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
...
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
187e1e46f9
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
...
llvm-svn: 137838
2011-08-17 18:14:48 +00:00
184b63d09c
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
...
llvm-svn: 137831
2011-08-17 17:45:08 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
be5e987379
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
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match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
llvm-svn: 137810
2011-08-17 02:29:19 +00:00
6d33c7f303
Update comments about vector splat handling in x86
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llvm-svn: 137808
2011-08-17 02:29:13 +00:00
ed786a346e
Now that we have a canonical way to handle 256-bit splats:
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vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!
llvm-svn: 137807
2011-08-17 02:29:10 +00:00
5360f88355
Add support for ext and ins.
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llvm-svn: 137804
2011-08-17 02:05:42 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
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llvm-svn: 137788
2011-08-16 23:57:34 +00:00
91a8f9be20
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
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llvm-svn: 137787
2011-08-16 23:45:44 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
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llvm-svn: 137779
2011-08-16 22:20:01 +00:00
64610e52e7
Add missing exit for 'case'.
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llvm-svn: 137774
2011-08-16 21:42:31 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
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llvm-svn: 137759
2011-08-16 21:34:08 +00:00
7283da9bb2
Move some logic into a helper function and expand the commentary.
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llvm-svn: 137756
2011-08-16 21:12:37 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
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Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
2e99f1b3aa
Instead of always leaving the work to the generic legalizer when
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there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:
For this shuffle:
shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
<i32 1, i32 0, i32 7, i32 6>
This was expanded to:
vextractf128 $1, %ymm1, %xmm2
vpextrq $0, %xmm2, %rax
vmovd %rax, %xmm1
vpextrq $1, %xmm2, %rax
vmovd %rax, %xmm2
vpunpcklqdq %xmm1, %xmm2, %xmm1
vpextrq $0, %xmm0, %rax
vmovd %rax, %xmm2
vpextrq $1, %xmm0, %rax
vmovd %rax, %xmm0
vpunpcklqdq %xmm2, %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
ret
Now we get:
vshufpd $1, %xmm0, %xmm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vshufpd $1, %xmm1, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
llvm-svn: 137733
2011-08-16 18:21:54 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
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Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
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Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
77f1fd5e44
Define function MipsMCInstLower::LowerOperand.
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llvm-svn: 137707
2011-08-16 02:21:03 +00:00
6520b9857f
Add parameter Offset to MipsMCInstLower::LowerSymbolOperand.
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llvm-svn: 137706
2011-08-16 02:15:03 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
c1676e41c0
While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and
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also add the AVX versions of the 128-bit patterns
llvm-svn: 137685
2011-08-15 23:36:51 +00:00
67005029bc
Reorder declarations of vmovmskp* and also put the necessary AVX
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predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
120a96a721
MCTargetAsmParser target match predicate support.
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Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
llvm-svn: 137675
2011-08-15 23:03:29 +00:00
cbe7feeab9
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
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when AVX mode is one. Otherwise is just more work for the type
legalizer.
llvm-svn: 137661
2011-08-15 21:45:54 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
de25f9aa8f
Remove dead classes.
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llvm-svn: 137643
2011-08-15 20:11:11 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
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llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
30694dcdeb
Update comment to reflect MC target machine refactor.
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llvm-svn: 137615
2011-08-15 16:52:24 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
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Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
2325474368
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
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Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
llvm-svn: 137525
2011-08-12 22:20:41 +00:00
c53dd2ac01
Fix comment!
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llvm-svn: 137521
2011-08-12 21:54:42 +00:00
f15dfe5818
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
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vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
llvm-svn: 137519
2011-08-12 21:48:26 +00:00
960c8f71aa
Move code around and add comments
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llvm-svn: 137518
2011-08-12 21:48:22 +00:00
2fcc1cfdce
Define unaligned load and store.
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llvm-svn: 137515
2011-08-12 21:30:06 +00:00
f402f694e2
ARM expansion of pre-indexed store pseudos should maintain memoperands.
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Partial fix for rdar://9945172.
llvm-svn: 137513
2011-08-12 21:02:34 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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llvm-svn: 137502
2011-08-12 20:36:11 +00:00
60138eaf93
Fix decoding of ARM-mode STRH.
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llvm-svn: 137499
2011-08-12 20:02:50 +00:00
1043e173bc
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
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llvm-svn: 137494
2011-08-12 19:41:29 +00:00
3987a61c16
Fix decoding of pre-indexed stores.
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llvm-svn: 137487
2011-08-12 18:12:39 +00:00
7bd6e6ebef
When constant double 0.0 is lowered, make sure 0 is copied directly from an
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integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.
- In the test case, the following code is generated before this patch is
applied:
mtc1 $zero, $f2 ; unformatted copy to $f2
mov.s $f0, $f2 ; $f0 is in single format
sdc1 $f12, 0($sp)
mov.s $f1, $f2 ; $f1 is in single format
c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double
- The following code is generated after this patch is applied:
mtc1 $zero, $f0 ; unformatted copy to $f0
mtc1 $zero, $f1 ; unformatted copy to $f1
c.eq.d $f12, $f0 ; $f0 can be interpreted as double
Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.
llvm-svn: 137484
2011-08-12 18:09:59 +00:00
01becebef3
switch to the new struct apis.
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llvm-svn: 137481
2011-08-12 18:07:07 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
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llvm-svn: 137476
2011-08-12 17:58:32 +00:00
a41634e307
Silence a bunch (but not all) "variable written but not read" warnings
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when building with assertions disabled.
llvm-svn: 137460
2011-08-12 14:54:45 +00:00
210bf8351d
findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.
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Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.
llvm-svn: 137404
2011-08-12 00:49:19 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
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llvm-svn: 137389
2011-08-11 23:51:13 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
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warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
37f7e6b2f4
Remove no-longer-true comments. These are for the assembler, also.
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llvm-svn: 137375
2011-08-11 22:30:30 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
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llvm-svn: 137372
2011-08-11 22:18:00 +00:00
eca346ee1a
Make the USAT16 operand decoder auto-generate-able.
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llvm-svn: 137371
2011-08-11 22:10:11 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
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llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
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llvm-svn: 137368
2011-08-11 22:05:38 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
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llvm-svn: 137367
2011-08-11 22:05:09 +00:00
12d13efa21
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
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llvm-svn: 137364
2011-08-11 21:52:38 +00:00
f05e744857
Making SEL decodings auto-generate-able.
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llvm-svn: 137363
2011-08-11 21:50:56 +00:00
8fbf023c9b
Add a dag combine to xform 256-bit shuffles into simple vector
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inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
llvm-svn: 137362
2011-08-11 21:50:44 +00:00
Craig Topper