Craig Topper
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01deb5f2df
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Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
llvm-svn: 160420
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2012-07-18 04:11:12 +00:00 |
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Devang Patel
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63fe5697f4
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Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
llvm-svn: 149142
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2012-01-27 19:48:28 +00:00 |
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Devang Patel
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cf893a437e
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Intel syntax: Robustify parsing of memory operand's displacement experssion.
llvm-svn: 148737
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2012-01-23 22:35:25 +00:00 |
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Devang Patel
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e660fdd953
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Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
llvm-svn: 148721
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2012-01-23 20:20:06 +00:00 |
|
Devang Patel
|
880bc1644b
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Intel syntax: Parse segment registers.
llvm-svn: 148712
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2012-01-23 18:31:58 +00:00 |
|
Devang Patel
|
ce6a2ca8c8
|
Intel syntax: Robustify register parsing.
llvm-svn: 148591
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2012-01-20 22:32:05 +00:00 |
|
Devang Patel
|
de47cced25
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Process instructions after match to select alternative encoding which may be more desirable.
llvm-svn: 148431
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2012-01-18 22:42:29 +00:00 |
|
Devang Patel
|
c9ed518792
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Intel syntax: Fix parser match class to check memory operand size.
llvm-svn: 148338
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2012-01-17 21:48:03 +00:00 |
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Devang Patel
|
a7143b6a2b
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Intel syntax: Parse "BYTE PTR [RDX + RCX]"
llvm-svn: 148334
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2012-01-17 21:25:10 +00:00 |
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Devang Patel
|
8b39be79ad
|
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
llvm-svn: 148321
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2012-01-17 19:08:07 +00:00 |
|
Devang Patel
|
a77c03be54
|
Intel syntax: Ignore mnemonic aliases.
llvm-svn: 148316
|
2012-01-17 18:30:45 +00:00 |
|
Devang Patel
|
41b9ddeb7a
|
Intel syntax: Robustify memory operand parsing.
llvm-svn: 148312
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2012-01-17 18:00:18 +00:00 |
|
Devang Patel
|
5d85276e30
|
Add new test.
llvm-svn: 148128
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2012-01-13 18:45:31 +00:00 |