1d54d2210a
Update test to something more sensible.
...
llvm-svn: 146282
2011-12-09 21:54:10 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
dd998ff4df
[fast-isel] Add support for selecting insertvalue.
...
rdar://10530851
llvm-svn: 146276
2011-12-09 20:09:54 +00:00
7e0a793183
Handle reloc_signed_4byte in here. Not doing so was a regression from my
...
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
llvm-svn: 146273
2011-12-09 19:57:29 +00:00
e7739d484f
The second part of support for generating dwarf for assembly source files. This
...
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
llvm-svn: 146262
2011-12-09 18:09:40 +00:00
16bbfbec66
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
...
llvm-svn: 146257
2011-12-09 15:44:03 +00:00
d04d152998
Add -unroll-runtime for unrolling loops with run-time trip counts.
...
Patch by Brendon Cahoon!
This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.
llvm-svn: 146245
2011-12-09 06:19:40 +00:00
5895fa79d6
Forgot setting -march.
...
llvm-svn: 146244
2011-12-09 06:15:00 +00:00
0a7f336475
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
...
symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
llvm-svn: 146238
2011-12-09 03:03:58 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
053a724483
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
...
llvm-svn: 146219
2011-12-09 01:16:26 +00:00
fe970725cc
Fix infinite loop in DSE when deleting a free in a reachable loop that's also
...
trivially infinite.
llvm-svn: 146197
2011-12-08 22:36:35 +00:00
b96bca81e7
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
...
llvm-svn: 146196
2011-12-08 22:30:45 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
...
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
2a217be25f
Add various missing AVX patterns which was causing crashes. Sadly, the generated
...
code looks pretty bad compared to SSE.
rdar://10538793
llvm-svn: 146191
2011-12-08 22:05:28 +00:00
3a97d946d2
Tidy up a bit.
...
llvm-svn: 146190
2011-12-08 22:04:40 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
...
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
27a33edfa0
Tidy up a bit.
...
llvm-svn: 146181
2011-12-08 20:53:19 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
...
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
...
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
0b9b9da6c8
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
...
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
3294538546
Add test for r146163.
...
llvm-svn: 146167
2011-12-08 19:21:39 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
...
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
0faa233439
test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.
...
llvm-svn: 146152
2011-12-08 15:24:09 +00:00
26edb291ac
Fix a bug in the integer-promotion of bitcast operations on vector types.
...
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
llvm-svn: 146150
2011-12-08 13:10:01 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
...
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
5ff64c7141
Tidy up.
...
llvm-svn: 146113
2011-12-08 00:41:54 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
...
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
...
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
...
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
...
llvm-svn: 146086
2011-12-07 22:11:43 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
d6ae4ba002
Darwin assembler improved relocs when w/o subsections_via_symbols.
...
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
2011-12-07 19:46:59 +00:00
18b0e5dca0
Thumb2 alias for long-form pop and friends.
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rdar://10542474
llvm-svn: 146046
2011-12-07 18:32:28 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
...
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
...
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
a4337ced68
Tidy up. Move MachO tests to MachO directory.
...
llvm-svn: 146038
2011-12-07 17:50:28 +00:00
ed8b3e38ec
Support vector bitcasts in the AsmPrinter. PR11495.
...
llvm-svn: 146001
2011-12-07 00:50:54 +00:00
0e58cba286
Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
...
llvm-svn: 145996
2011-12-07 00:11:56 +00:00
0fc34bc2d3
delaying restore-cr changed assigned registers in some tests
...
llvm-svn: 145963
2011-12-06 20:55:46 +00:00
0702bc1b28
add a test case that uses RESTORE_CR
...
llvm-svn: 145962
2011-12-06 20:55:41 +00:00
04424665c3
PTX: Continue to fix up the register mess.
...
llvm-svn: 145947
2011-12-06 17:39:48 +00:00
6572e0f203
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
...
llvm-svn: 145927
2011-12-06 09:04:59 +00:00
51416d5f00
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
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FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
2011-12-06 06:48:26 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
bf41eb3a98
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
...
llvm-svn: 145921
2011-12-06 04:59:07 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
5bdc0fbabd
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
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MC/MachO assumes x86.
llvm-svn: 145916
2011-12-06 03:56:05 +00:00
5df9096584
LSR: prune undesirable formulae early.
...
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.
llvm-svn: 145906
2011-12-06 03:13:31 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
2e05db2fa0
Align ARM constant pool islands via their basic block.
...
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
...
rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
8abf65a130
Probably not a good idea to convert a single vector load into a memcpy. We
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don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684
llvm-svn: 145879
2011-12-06 00:19:08 +00:00
19446a07a7
Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio
...
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150
llvm-svn: 145865
2011-12-05 22:37:00 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
...
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
8b5e92577b
Update tests for r145860. Add a few new ones.
...
llvm-svn: 145861
2011-12-05 22:21:28 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
...
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
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O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
97a6028b3a
Add test case - this input used to crash because of duplicate generation of SPILL_CRs
...
llvm-svn: 145820
2011-12-05 17:55:22 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
...
llvm-svn: 145819
2011-12-05 17:55:17 +00:00
e18c72689c
remove wasted space for extra bit copies of CR2 subregs
...
llvm-svn: 145817
2011-12-05 17:55:06 +00:00
e6efe405de
test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux.
...
llvm-svn: 145805
2011-12-05 07:54:57 +00:00
3924cb0267
Add support for vectors of pointers.
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llvm-svn: 145801
2011-12-05 06:29:09 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
...
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
...
AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
006e43bcc0
Check for stack space more intelligently.
...
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
165ca1d4ba
Fix a bug in the x86-32 code generated for segmented stacks.
...
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
llvm-svn: 145765
2011-12-03 09:21:07 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
e03fe83d98
Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur
...
Turns out long long + unsigned long long is unsigned. Doh!
Fixes http://llvm.org/bugs/show_bug.cgi?id=11455
llvm-svn: 145731
2011-12-03 00:04:30 +00:00
0155a63513
Add support for constant folding the pow intrinsic.
...
rdar://10514247
llvm-svn: 145730
2011-12-03 00:00:03 +00:00
430f917fbe
Test cases for 64-bit multiplication and division.
...
llvm-svn: 145717
2011-12-02 22:31:36 +00:00
bbc5555bee
Fix test cases to use FileCheck.
...
llvm-svn: 145716
2011-12-02 22:28:09 +00:00
7276397f41
ARM tests for VLD1 single lane w/ writeback.
...
llvm-svn: 145713
2011-12-02 22:03:52 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
d87f7af1f3
specify cpu for test to fix failure on some darwin systems with a g4+ cpu
...
llvm-svn: 145699
2011-12-02 19:38:17 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
abeb79eee3
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
...
llvm-svn: 145680
2011-12-02 07:16:01 +00:00
9286705955
adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec.
...
llvm-svn: 145678
2011-12-02 04:58:12 +00:00
3367123b12
Prevent library calls from being folded if -fno-builtin has been specified.
...
rdar://10500969
llvm-svn: 145639
2011-12-01 22:14:50 +00:00
fdddc27143
Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment
...
llvm-svn: 145618
2011-12-01 19:13:26 +00:00
9da7f305a4
For 64-bit the rest of the general regs are ok for the q constraint. Make
...
sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
2011-12-01 08:12:41 +00:00
d61887dd0a
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
...
llvm-svn: 145573
2011-12-01 04:49:21 +00:00
3b7f35bf08
Removed use of grep from test and moved it to be with other icmp tests
...
llvm-svn: 145570
2011-12-01 04:35:26 +00:00
bc5c524b71
Added instcombine pattern to spot comparing -val or val against 0.
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(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"
Fixes <rdar://problem/10482509>
llvm-svn: 145563
2011-12-01 03:58:40 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
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remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
6cff9df298
Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.
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<rdar://problem/10497732>.
llvm-svn: 145523
2011-11-30 21:54:15 +00:00
7d8517b1d4
Add some tests for all-lanes VLD1 parsing.
...
llvm-svn: 145512
2011-11-30 19:37:38 +00:00
0a1801015c
Add test arch to make it pass on non x86 targets
...
llvm-svn: 145498
2011-11-30 17:34:28 +00:00
66427bcce9
Add a tripple to the test
...
llvm-svn: 145489
2011-11-30 11:20:56 +00:00
96923cc2bb
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
...
llvm-svn: 145488
2011-11-30 10:13:37 +00:00
613c67e475
Better test case found in duplicate PR10570.
...
llvm-svn: 145484
2011-11-30 06:26:42 +00:00
ceafa2c746
LSR: handle the expansion of phi operands that use postinc forms of the IV.
...
Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.
llvm-svn: 145482
2011-11-30 06:07:54 +00:00
82e1bd8e94
Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
...
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410
llvm-svn: 145460
2011-11-29 23:57:10 +00:00
f50d2eafdb
FileCheckize.
...
llvm-svn: 145452
2011-11-29 23:09:16 +00:00
dc25f9f38a
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
...
tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
llvm-svn: 145451
2011-11-29 23:08:41 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
...
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
648e48d02e
Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.
...
llvm-svn: 145448
2011-11-29 22:48:34 +00:00
2a9c43649a
Enable some VST1 tests and add a few more.
...
llvm-svn: 145443
2011-11-29 22:40:32 +00:00
bde32d36bb
Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
...
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.
This also makes the AVX variants redundant.
llvm-svn: 145440
2011-11-29 22:27:25 +00:00
46addb9e07
If fast-isel fails, remove dead instructions generated during the failed
...
attempt.
llvm-svn: 145425
2011-11-29 19:40:47 +00:00
ca6f8ddbf8
Fix a theoretical problem (not seen in the wild): if different instances of a
...
weak variable are compiled by different compilers, such as GCC and LLVM, while
LLVM may increase the alignment to the preferred alignment there is no reason to
think that GCC will use anything more than the ABI alignment. Since it is the
GCC version that might end up in the final program (as the linkage is weak), it
is wrong to increase the alignment of loads from the global up to the preferred
alignment as the alignment might only be the ABI alignment.
Increasing alignment up to the ABI alignment might be OK, but I'm not totally
convinced that it is. It seems better to just leave the alignment of weak
globals alone.
llvm-svn: 145413
2011-11-29 18:26:38 +00:00
de3a2118db
MC/X86/COFF: Allow quotes in names when targeting MS/Windows,
...
as MC is the only assembler we support.
This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.
llvm-svn: 145409
2011-11-29 18:00:06 +00:00
cbe72fc959
Fixed ObjectFile functions:
...
- getSymbolOffset() renamed as getSymbolFileOffset()
- getSymbolFileOffset(), getSymbolAddress(), getRelocationAddress() returns same result for ELFObjectFile, MachOObjectFile and COFFObjectFile.
- added getRelocationOffset()
- fixed MachOObjectFile::getSymbolSize()
- fixed MachOObjectFile::getSymbolSection()
- fixed MachOObjectFile::getSymbolOffset() for symbols without section data.
llvm-svn: 145408
2011-11-29 17:40:10 +00:00
7a81dea516
Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.
...
Added a test.
Thanks Bruno for reviewing the patch.
llvm-svn: 145403
2011-11-29 15:00:45 +00:00
1d63ae3731
Fix shuffle decoding for memory forms for (V)SHUFPS/D.
...
llvm-svn: 145392
2011-11-29 07:58:09 +00:00
c16db840be
Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD.
...
llvm-svn: 145390
2011-11-29 07:49:05 +00:00
12b72def4e
Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled.
...
llvm-svn: 145376
2011-11-29 05:37:58 +00:00
897a7d4b9c
Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2.
...
llvm-svn: 145370
2011-11-29 03:57:34 +00:00
d25089f8e0
SCEV fix. In general, Add/Mul expressions should not inherit NSW/NUW.
...
This reverts r139450, fixes r139453, and adds much needed comments and a
unit test.
llvm-svn: 145367
2011-11-29 02:16:38 +00:00
5ec136c57e
Filecheckize.
...
llvm-svn: 145363
2011-11-29 02:05:23 +00:00
e756031a62
Reenable this IndVars unit test.
...
SCEV can't optimize undef in all cases, which is a separate issue from this test case.
llvm-svn: 145343
2011-11-29 00:52:04 +00:00
b3f9b0676a
Add a missing safety check to ProcessUGT_ADDCST_ADD. Fixes PR11438.
...
llvm-svn: 145316
2011-11-28 23:32:19 +00:00
e7ab1a2f0f
Make SelectionDAG::InferPtrAlignment use llvm::ComputeMaskedBits instead of duplicating the logic for globals. Make llvm::ComputeMaskedBits handle GlobalVariables slightly more aggressively, to match what InferPtrAlignment knew how to do.
...
llvm-svn: 145304
2011-11-28 22:48:22 +00:00
4a5b2040e2
Revert r145273 and fix in SelectionDAG::InferPtrAlignment() instead.
...
Conservatively returns zero when the GV does not specify an alignment nor is it
initialized. Previously it returns ABI alignment for type of the GV. However, if
the type is a "packed" type, then the under-specified alignments is attached to
the load / store instructions. In that case, the alignment of the type cannot be
trusted.
rdar://10464621
llvm-svn: 145300
2011-11-28 22:37:34 +00:00
a4b6404cf0
DAG combine should not increase alignment of loads / stores with alignment less
...
than ABI alignment. These are loads / stores from / to "packed" data structures.
Their alignments are intentionally under-specified.
rdar://10301431
llvm-svn: 145273
2011-11-28 20:42:56 +00:00
818a983e93
Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar.
...
llvm-svn: 145238
2011-11-28 10:14:51 +00:00
8284ec46b6
test/lit.cfg: Enable the feature 'asserts' to check output of llc -version.
...
llc knows whether he is compiled with -DNDEBUG.
| Optimized build with assertions.
llvm-svn: 145230
2011-11-28 05:09:15 +00:00
251d827d2c
remove a test that is using old-style llvm.dbg intrinsics, apparently only
...
fails on ppc and arm hosts.
llvm-svn: 145188
2011-11-27 18:13:47 +00:00
03adbd46ca
Take two on rotating the block ordering of loops. My previous attempt
...
was centered around the premise of laying out a loop in a chain, and
then rotating that chain. This is good for preserving contiguous layout,
but bad for actually making sane rotations. In order to keep it safe,
I had to essentially make it impossible to rotate deeply nested loops.
The information needed to correctly reason about a deeply nested loop is
actually available -- *before* we layout the loop. We know the inner
loops are already fused into chains, etc. We lose information the moment
we actually lay out the loop.
The solution was the other alternative for this algorithm I discussed
with Benjamin and some others: rather than rotating the loop
after-the-fact, try to pick a profitable starting block for the loop's
layout, and then use our existing layout logic. I was worried about the
complexity of this "pick" step, but it turns out such complexity is
needed to handle all the important cases I keep teasing out of benchmarks.
This is, I'm afraid, a bit of a work-in-progress. It is still
misbehaving on some likely important cases I'm investigating in Olden.
It also isn't really tested. I'm going to try to craft some interesting
nested-loop test cases, but it's likely to be extremely time consuming
and I don't want to go there until I'm sure I'm testing the correct
behavior. Sadly I can't come up with a way of getting simple, fine
grained test cases for this logic. We need complex loop structures to
even trigger much of it.
llvm-svn: 145183
2011-11-27 13:34:33 +00:00
a054580993
Rework a bit of the implementation of loop block rotation to not rely so
...
heavily on AnalyzeBranch. That routine doesn't behave as we want given
that rotation occurs mid-way through re-ordering the function. Instead
merely check that there are not unanalyzable branching constructs
present, and then reason about the CFG via successor lists. This
actually simplifies my mental model for all of this as well.
The concrete result is that we now will rotate more loop chains. I've
added a test case from Olden highlighting the effect. There is still
a bit more to do here though in order to regain all of the performance
in Olden.
llvm-svn: 145179
2011-11-27 09:22:53 +00:00
ee471c484a
remove autoupgrade support for old forms of llvm.prefetch and the old
...
trampoline forms. Both of these were correct in LLVM 3.0, and we don't
need to support LLVM 2.9 and earlier in mainline.
llvm-svn: 145174
2011-11-27 07:42:04 +00:00
6a144a2227
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
...
llvm-svn: 145171
2011-11-27 06:54:59 +00:00
90ef78c07f
remove autoupgrade support for really old-style debug info intrinsics.
...
I think this is the last of autoupgrade that can be removed in 3.1.
Can the atomic upgrade stuff also go?
llvm-svn: 145169
2011-11-27 06:18:33 +00:00
6aa6c0c3b7
remove some old autoupgrade logic
...
llvm-svn: 145167
2011-11-27 06:10:54 +00:00
1c9e5678b8
remove support for reading llvm 2.9 .bc files. LLVM 3.1 is only compatible back to 3.0
...
llvm-svn: 145164
2011-11-27 05:48:27 +00:00
97b3da5433
Add several new instructions supported by the latest MicroBlaze.
...
These instructions are not generated by the backend yet, this will come in a later commit.
llvm-svn: 145161
2011-11-27 05:16:58 +00:00
9ffb97e631
Introduce a loop block rotation optimization to the new block placement
...
pass. This is designed to achieve one of the important optimizations
that the old code placement pass did, but more simply.
This is a somewhat rough and *very* conservative version of the
transform. We could get a lot fancier here if there are profitable cases
to do so. In particular, this only looks for a single pattern, it
insists that the loop backedge being rotated away is the last backedge
in the chain, and it doesn't provide any means of doing better in-loop
placement due to the rotation. However, it appears that it will handle
the important loops I am finding in the LLVM test suite.
llvm-svn: 145158
2011-11-27 00:38:03 +00:00
f156f0cf57
FileCheck-ize this test and make it more precise. This is in preparation
...
for adding other tests.
llvm-svn: 145143
2011-11-26 08:24:25 +00:00
a84ad7d0d0
Fix APFloat::convert so that it handles narrowing conversions correctly; it
...
was returning incorrect values in rare cases, and incorrectly marking
exact conversions as inexact in some more common cases. Fixes PR11406, and a
missed optimization in test/CodeGen/X86/fp-stack-O0.ll.
llvm-svn: 145141
2011-11-26 03:38:02 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
...
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
d65a444478
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
...
llvm-svn: 145126
2011-11-24 22:57:10 +00:00
651db37352
X86: alias cqo to cqto.
...
llvm-svn: 145121
2011-11-24 12:02:46 +00:00
7adee1a01a
Fix a silly use-after-free issue. A much earlier version of this code
...
need lots of fanciness around retaining a reference to a Chain's slot in
the BlockToChain map, but that's all gone now. We can just go directly
to allocating the new chain (which will update the mapping for us) and
using it.
Somewhat gross mechanically generated test case replicates the issue
Duncan spotted when actually testing this out.
llvm-svn: 145120
2011-11-24 11:23:15 +00:00
d394bafd2d
When adding blocks to the list of those which no longer have any CFG
...
conflicts, we should only be adding the first block of the chain to the
list, lest we try to merge into the middle of that chain. Most of the
places we were doing this we already happened to be looking at the first
block, but there is no reason to assume that, and in some cases it was
clearly wrong.
I've added a couple of tests here. One already worked, but I like having
an explicit test for it. The other is reduced from a test case Duncan
reduced for me and used to crash. Now it is handled correctly.
llvm-svn: 145119
2011-11-24 08:46:04 +00:00
4f9a8081c3
Correctly byte-swap APInts with bit-widths greater than 64.
...
llvm-svn: 145111
2011-11-23 21:33:37 +00:00
81a2af12d6
Fix a crash in which a multiplication was being reported as being both negative
...
and positive: positive, because it could be directly computed to be positive;
negative, because the nsw flags means it is either negative or undefined (the
multiplication always overflowed).
llvm-svn: 145104
2011-11-23 16:26:47 +00:00
ebcb451874
X86: Use btq for bit tests if the immediate can't be encoded in 32 bits.
...
Before:
movabsq $4294967296, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
testq %rax, %rdi ## encoding: [0x48,0x85,0xf8]
jne LBB0_2 ## encoding: [0x75,A]
After:
btq $32, %rdi ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
jb LBB0_2 ## encoding: [0x72,A]
btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.
llvm-svn: 145103
2011-11-23 13:54:17 +00:00
0b3e996485
test/CodeGen/X86/block-placement.ll: Add explicit -mtriple=i686-linux. X86 Win32 CodeGen does not support EH yet.
...
llvm-svn: 145101
2011-11-23 12:18:22 +00:00
99fe42fbd9
Relax an invariant that block placement was trying to assert a bit
...
further. This invariant just wasn't going to work in the face of
unanalyzable branches; we need to be resillient to the phenomenon of
chains poking into a loop and poking out of a loop. In fact, we already
were, we just needed to not assert on it.
This was found during a bootstrap with block placement turned on.
llvm-svn: 145100
2011-11-23 10:35:36 +00:00
779ba6d7b7
I added several lines in X86 code generator that allow to choose
...
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.
The patch was reviewed by Bruno.
llvm-svn: 145099
2011-11-23 10:23:16 +00:00
8c68f1f3c8
Handle the case of a no-return invoke correctly. It actually still has
...
successors, they just are all landing pad successors. We handle this the
same way as no successors. Comments attached for the next person to wade
through here and another lovely test case courtesy of Benjamin Kramer's
bugpoint reduction.
llvm-svn: 145098
2011-11-23 08:23:54 +00:00
ebb44646c4
Enable stack protectors for all arrays, not just char arrays. rdar://5875909
...
Patch by Bill Wendling.
llvm-svn: 145097
2011-11-23 07:13:56 +00:00
02845410f9
Fix PR11422.
...
This was a bug in keeping track of the available domains when merging
domain values.
The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.
Also add an assertion to catch future attempts at emitting AVX2
instructions.
llvm-svn: 145096
2011-11-23 04:03:08 +00:00
4a87aa0c31
Fix a crash in block placement due to an inner loop that happened to be
...
reversed in the function's original ordering, and we happened to
encounter it while handling an outer unnatural CFG structure.
Thanks to the test case reduced from GCC's source by Benjamin Kramer.
This may also fix a crasher in gzip that Duncan reduced for me, but
I haven't yet gotten to testing that one.
llvm-svn: 145094
2011-11-23 03:03:21 +00:00
8b5c7a56a3
[asan] do not instrument threadlocal globals, this is buggy
...
llvm-svn: 145092
2011-11-23 02:10:54 +00:00
6f0ae783fe
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
...
llvm-svn: 145065
2011-11-22 16:21:04 +00:00
ee54feb6f6
Fix a devilish miscompile exposed by block placement. The
...
updateTerminator code didn't correctly handle EH terminators in one very
specific case. AnalyzeBranch would find no terminator instruction, and
so the fallback in updateTerminator is to assume fallthrough. This is
correct, but the destination of the fallthrough was assumed to be the
first successor.
This is *almost always* true, but in certain cases the loop
transformations will cause the landing pad to be the first successor!
Instead of this brittle logic, actually look through the successors for
a non-landing-pad accessor, and to assert if more than one is found.
This will hopefully fix some (if not all) of the self host miscompiles
with block placement. Thanks to Benjamin Kramer for reporting, Nick
Lewycky for an initial stab at a reduction, and Duncan for endless
advice on EH (which I know nothing about) as well as reviewing the
actual fix.
llvm-svn: 145062
2011-11-22 13:13:16 +00:00
c55e1af137
Add triple to the test.
...
llvm-svn: 145057
2011-11-22 06:36:25 +00:00
2021f38281
If a register is both an early clobber and part of a tied use, handle the use
...
before the clobber so that we copy the value if needed.
Fixes pr11415.
llvm-svn: 145056
2011-11-22 06:27:18 +00:00
063ae5897c
Fix crasher in GVN due to my recent capture tracking changes.
...
llvm-svn: 145047
2011-11-21 19:42:56 +00:00
6270d072c5
Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.
...
llvm-svn: 145028
2011-11-21 08:26:50 +00:00
d12d6f4b1c
Test case for r145026
...
llvm-svn: 145027
2011-11-21 06:58:09 +00:00
a065238c6e
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.
...
llvm-svn: 145022
2011-11-21 01:12:36 +00:00
76dfa03874
test/CodeGen/X86/block-placement.ll: Relax expressions for Win32.
...
llvm-svn: 145011
2011-11-20 12:49:45 +00:00
18dfac385b
The logic for breaking the CFG in the presence of hot successors didn't
...
properly account for the *global* probability of the edge being taken.
This manifested as a very large number of unconditional branches to
blocks being merged against the CFG even though they weren't
particularly hot within the CFG.
The fix is to check whether the edge being merged is both locally hot
relative to other successors for the source block, and globally hot
compared to other (unmerged) predecessors of the destination block.
This introduces a new crasher on GCC single-source, but it's currently
behind a flag, and Ben has offered to work on the reduction. =]
llvm-svn: 145010
2011-11-20 11:22:06 +00:00
650c09aa4d
XFAIL this test until I figure out what indvars is doing here (or find someone who does)
...
llvm-svn: 145008
2011-11-20 11:10:03 +00:00
20df3953d3
Add some comments to the latest test case I added here to document what
...
is actually being tested. Also add some FileCheck goodness to much more
carefully ensure that the result is the desired result. Before this test
would only have failed through an assert failure if the underlying fix
were reverted.
Also, add some weight metadata and a comment explaining exactly what is
going on to a trick section of the test case. Originally, we were
getting very unlucky and trying to form a block chain that isn't
actually profitable. I'm working on a fix to avoid forming these
unprofitable chains, and that would also have masked any failure from
this test case. The easy solution is to add some metadata that makes it
*really* profitable to form the bad chain here.
llvm-svn: 145006
2011-11-20 09:30:40 +00:00
e79761df73
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
...
llvm-svn: 145005
2011-11-20 00:12:05 +00:00
a3a6583694
Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.
...
llvm-svn: 145004
2011-11-19 22:34:59 +00:00
f3dc9eff16
Move the handling of unanalyzable branches out of the loop-driven chain
...
formation phase and into the initial walk of the basic blocks. We
essentially pre-merge all blocks where unanalyzable fallthrough exists,
as we won't be able to update the terminators effectively after any
reorderings. This is quite a bit more principled as there may be CFGs
where the second half of the unanalyzable pair has some analyzable
predecessor that gets placed first. Then it may get placed next,
implicitly breaking the unanalyzable branch even though we never even
looked at the part that isn't analyzable. I've included a test case that
triggers this (thanks Benjamin yet again!), and I'm hoping to synthesize
some more general ones as I dig into related issues.
Also, to make this new scheme work we have to be able to handle branches
into the middle of a chain, so add this check. We always fallback on the
incoming ordering.
Finally, this starts to really underscore a known limitation of the
current implementation -- we don't consider broken predecessors when
merging successors. This can caused major missed opportunities, and is
something I'm planning on looking at next (modulo more bug reports).
llvm-svn: 144994
2011-11-19 10:26:02 +00:00
6d77f4ae14
Test cases for SSSE3/AVX integer horizontal add/sub.
...
llvm-svn: 144990
2011-11-19 09:03:33 +00:00
de6b73bb4d
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
...
llvm-svn: 144987
2011-11-19 07:07:26 +00:00
6b4d578f54
Fix a corner case in updating LoopInfo after fully unrolling an outer loop.
...
The loop tree's inclusive block lists are painful and expensive to
update. (I have no idea why they're inclusive). The design was
supposed to handle this case but the implementation missed it and my
unit tests weren't thorough enough.
Fixes PR11335: loop unroll update.
llvm-svn: 144970
2011-11-18 03:42:41 +00:00
1ec141d0f9
Add AVX2 vpbroadcast support
...
llvm-svn: 144967
2011-11-18 02:49:55 +00:00
1cdc6e9567
[asan] workaround for reg alloc bug 11395: don't instrument functions with large chunks of inline assembler
...
llvm-svn: 144962
2011-11-18 01:41:06 +00:00
107e8ec30d
DISubrange supports unsigned lower/upper array bounds, so let's not fake it in the end while emitting DWARF. If a FE needs to encode signed lower/upper array bounds then we need to extend DISubrange or ad DISignedSubrange.
...
llvm-svn: 144937
2011-11-17 23:43:15 +00:00
949045864d
Fix an overly general check in SimplifyIndvar to handle useless phi cycles.
...
The right way to check for a binary operation is
cast<BinaryOperator>. The original check: cast<Instruction> &&
numOperands() == 2 would match phi "instructions", leading to an
infinite loop in extreme corner case: a useless phi with operands
[self, constant] that prior optimization passes failed to remove,
being used in the loop by another useless phi, in turn being used by an
lshr or udiv.
Fixes PR11350: runaway iteration assertion.
llvm-svn: 144935
2011-11-17 23:36:35 +00:00
65e2211b95
fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr
...
llvm-svn: 144933
2011-11-17 23:14:59 +00:00
f83ab704e4
When fast iseling a GEP, accumulate the offset rather than emitting a series of
...
ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD. Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to
coalesce ADDs.
rdar://10412592
llvm-svn: 144886
2011-11-17 07:15:58 +00:00
489c0ff4a4
Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
...
names for fwrite and fputs.
Fixes <rdar://problem/9815881>.
llvm-svn: 144876
2011-11-17 01:27:36 +00:00
586aabc44a
build/make/test: Get rid of unused BUGPOINT_TOPTS variable.
...
llvm-svn: 144864
2011-11-16 23:56:03 +00:00
ff1eaa7578
Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393.
...
llvm-svn: 144863
2011-11-16 23:50:22 +00:00
f4d2e0d458
Remove obsolete test.
...
The PLD encoding is checked via the .s file now.
llvm-svn: 144853
2011-11-16 22:50:38 +00:00
d3f02cbce9
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
2011-11-16 22:48:37 +00:00
d66cb5ab33
Update test for r144842.
...
llvm-svn: 144851
2011-11-16 22:46:27 +00:00
011538dc79
Another missing X86ISD::MOVLPD pattern. rdar://10450317
...
llvm-svn: 144839
2011-11-16 22:24:44 +00:00
822ddde50d
Disable expensive two-address optimizations at -O0. rdar://10453055
...
llvm-svn: 144806
2011-11-16 18:44:48 +00:00
db408f1857
Fix typo in test.
...
llvm-svn: 144774
2011-11-16 03:56:38 +00:00
c7f1e7993c
Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when
...
looking at the size of the pointee. Fixes PR11390!
llvm-svn: 144773
2011-11-16 03:49:48 +00:00
e6270395e3
Fix testcase.
...
llvm-svn: 144769
2011-11-16 03:03:52 +00:00
87f92512c3
CONCAT_VECTORS can have more than two operands. PR11389.
...
llvm-svn: 144768
2011-11-16 02:52:39 +00:00
6e6b03ec46
AddressSanitizer, first commit (compiler module only)
...
llvm-svn: 144758
2011-11-16 01:35:23 +00:00
90c7a108ca
Fix SCEV overly optimistic back edge taken count for multi-exit loops.
...
Fixes PR11375: Different results for 'clang++ huh.cpp'...
llvm-svn: 144746
2011-11-16 00:52:40 +00:00
e891fe8d6c
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
37010002f2
AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
...
llvm-svn: 144720
2011-11-15 22:50:37 +00:00
f6b315c081
test/CodeGen/X86/dec-eflags-lower.ll: Relax expression for win32 x64.
...
llvm-svn: 144714
2011-11-15 22:30:37 +00:00
75fb4abcdc
ARM assembly parsing two operand forms for shift instructions.
...
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
7c7ba1baa1
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
...
by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
llvm-svn: 144705
2011-11-15 21:57:53 +00:00
131b45e632
ARM alternate size suffices for VTRN instructions.
...
rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
5803f6d5a2
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
llvm-svn: 144691
2011-11-15 20:29:42 +00:00
c5b1bc561e
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
llvm-svn: 144689
2011-11-15 20:14:51 +00:00
72dfd20aba
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
68c899c211
Testcase for r144684.
...
llvm-svn: 144685
2011-11-15 19:56:17 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
...
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
6efa7b9852
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
f11e7f1305
We currently use a callback to handle an IL pass deleting a BB that still
...
has a reference to it. Unfortunately, that doesn't work for codegen passes
since we don't get notified of MBB's being deleted (the original BB stays).
Use that fact to our advantage and after printing a function, check if
any of the IL BBs corresponds to a symbol that was not printed. This fixes
pr11202.
llvm-svn: 144674
2011-11-15 19:08:46 +00:00
4949b9a283
Revert r144611 and r144613.
...
These tests are actually correct, clang was miscompiling ExeDepsFix::processUses.
Evan fixed the miscompilation in r144628.
llvm-svn: 144630
2011-11-15 07:13:03 +00:00
9b548a7fcf
Rather than trying to use the loop block sequence *or* the function
...
block sequence when recovering from unanalyzable control flow
constructs, *always* use the function sequence. I'm not sure why I ever
went down the path of trying to use the loop sequence, it is
fundamentally not the correct sequence to use. We're trying to preserve
the incoming layout in the cases of unreasonable control flow, and that
is only encoded at the function level. We already have a filter to
select *exactly* the sub-set of blocks within the function that we're
trying to form into a chain.
The resulting code layout is also significantly better because of this.
In several places we were ending up with completely unreasonable control
flow constructs due to the ordering chosen by the loop structure for its
internal storage. This change removes a completely wasteful vector of
basic blocks, saving memory allocation in the common case even though it
costs us CPU in the fairly rare case of unnatural loops. Finally, it
fixes the latest crasher reduced out of GCC's single source. Thanks
again to Benjamin Kramer for the reduction, my bugpoint skills failed at
it.
llvm-svn: 144627
2011-11-15 06:26:43 +00:00
05baa85f58
Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.
...
llvm-svn: 144622
2011-11-15 05:55:35 +00:00
9c0de9bb6b
Really fix test.
...
llvm-svn: 144613
2011-11-15 03:17:01 +00:00
14b66375a9
Allow for depencendy-breaking instructions before cvt*.
...
This should unbreak clang-x86_64-darwin10-RA, but I can't actually
reproduce the failure.
llvm-svn: 144611
2011-11-15 02:29:48 +00:00
7ca4b6eb5c
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
...
integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
f8ad336bc4
Break false dependencies before partial register updates.
...
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.
The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.
The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.
llvm-svn: 144602
2011-11-15 01:15:30 +00:00
a498af2b1d
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
72838a0345
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
3d6c0e0bb2
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
...
rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
7013a19e8a
Refactor capture tracking (which already had a couple flags for whether returns
...
and stores capture) to permit the caller to see each capture point and decide
whether to continue looking.
Use this inside memdep to do an analysis that basicaa won't do. This lets us
solve another devirtualization case, fixing PR8908!
llvm-svn: 144580
2011-11-14 22:49:42 +00:00
4e88fbebde
Add newline to end of file. Thanks, Eli.
...
llvm-svn: 144579
2011-11-14 22:48:33 +00:00
ab7223e99a
Add support for inlining small memcpys.
...
rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
45110fdf8d
Fix a performance regression from r144565. Positive offsets were being lowered
...
into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
fb13d32b3f
Add a missing pattern for X86ISD::MOVLPD. rdar://10436044
...
llvm-svn: 144566
2011-11-14 20:35:52 +00:00
adfd200bcb
Add support for Thumb load/stores with negative offsets.
...
rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
30f44ad785
Teach two-address pass to re-schedule two-address instructions (or the kill
...
instructions of the two-address operands) in order to avoid inserting copies.
This fixes the few regressions introduced when the two-address hack was
disabled (without regressing the improvements).
rdar://10422688
llvm-svn: 144559
2011-11-14 19:48:55 +00:00
890e02e854
Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered
...
Constant idx case is still done in tablegen but other cases are then expanded
Fixes <rdar://problem/10435460>
llvm-svn: 144557
2011-11-14 19:38:42 +00:00
7e6004a3c1
Fix early-clobber handling in shrinkToUses.
...
I broke this in r144515, it affected most ARM testers.
<rdar://problem/10441389>
llvm-svn: 144547
2011-11-14 18:45:38 +00:00
7e07b388ac
Delete stale comment.
...
llvm-svn: 144542
2011-11-14 18:03:05 +00:00
ed5aa547bc
Fix an overflow bug in MachineBranchProbabilityInfo. This pass relied on
...
the sum of the edge weights not overflowing uint32, and crashed when
they did. This is generally safe as BranchProbabilityInfo tries to
provide this guarantee. However, the CFG can get modified during codegen
in a way that grows the *sum* of the edge weights. This doesn't seem
unreasonable (imagine just adding more blocks all with the default
weight of 16), but it is hard to come up with a case that actually
triggers 32-bit overflow. Fortuately, the single-source GCC build is
good at this. The solution isn't very pretty, but its no worse than the
previous code. We're already summing all of the edge weights on each
query, we can sum them, check for an overflow, compute a scale, and sum
them again.
I've included a *greatly* reduced test case out of the GCC source that
triggers it. It's a pretty lame test, as it clearly is just barely
triggering the overflow. I'd like to have something that is much more
definitive, but I don't understand the fundamental pattern that triggers
an explosion in the edge weight sums.
The buggy code is duplicated within this file. I'll colapse them into
a single implementation in a subsequent commit.
llvm-svn: 144526
2011-11-14 08:50:16 +00:00
2a1df883d0
Add support for ARM halfword load/stores and signed byte loads with negative
...
offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
1071cfa4ae
Teach machine block placement to cope with unnatural loops. These don't
...
get loop info structures associated with them, and so we need some way
to make forward progress selecting and placing basic blocks. The
technique used here is pretty brutal -- it just scans the list of blocks
looking for the first unplaced candidate. It keeps placing blocks like
this until the CFG becomes tractable.
The cost is somewhat unfortunate, it requires allocating a vector of all
basic block pointers eagerly. I have some ideas about how to simplify
and optimize this, but I'm trying to get the logic correct first.
Thanks to Benjamin Kramer for the reduced test case out of GCC. Sadly
there are other bugs that GCC is tickling that I'm reducing and working
on now.
llvm-svn: 144516
2011-11-14 00:00:35 +00:00
8d15078927
Rewrite #3 of machine block placement. This is based somewhat on the
...
second algorithm, but only loosely. It is more heavily based on the last
discussion I had with Andy. It continues to walk from the inner-most
loop outward, but there is a key difference. With this algorithm we
ensure that as we visit each loop, the entire loop is merged into
a single chain. At the end, the entire function is treated as a "loop",
and merged into a single chain. This chain forms the desired sequence of
blocks within the function. Switching to a single algorithm removes my
biggest problem with the previous approaches -- they had different
behavior depending on which system triggered the layout. Now there is
exactly one algorithm and one basis for the decision making.
The other key difference is how the chain is formed. This is based
heavily on the idea Andy mentioned of keeping a worklist of blocks that
are viable layout successors based on the CFG. Having this set allows us
to consistently select the best layout successor for each block. It is
expensive though.
The code here remains very rough. There is a lot that needs to be done
to clean up the code, and to make the runtime cost of this pass much
lower. Very much WIP, but this was a giant chunk of code and I'd rather
folks see it sooner than later. Everything remains behind a flag of
course.
I've added a couple of tests to exercise the issues that this iteration
was motivated by: loop structure preservation. I've also fixed one test
that was exhibiting the broken behavior of the previous version.
llvm-svn: 144495
2011-11-13 11:20:44 +00:00
1198d894d0
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
...
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
a476e391f1
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
...
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
c8cfd3a8fb
Add support for emitting both signed- and zero-extend loads. Fix
...
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
6ddb767fb5
Remove the -color-ss-with-regs option.
...
It was off by default.
The new register allocators don't have the problems that made it
necessary to reallocate registers during stack slot coloring.
llvm-svn: 144481
2011-11-13 00:31:23 +00:00
7ef502f6d1
Delete the 'standard' spiller with used the old spilling framework.
...
The current register allocators all use the inline spiller.
llvm-svn: 144477
2011-11-12 23:29:02 +00:00
ce4ef9f8d5
Remove histogram tests.
...
Counting the number of occurences of each opcode is not a useful test.
llvm-svn: 144474
2011-11-12 22:39:40 +00:00
0eac531bc2
RAGreedy is better about hinting now.
...
Or maybe we are just getting lucky.
llvm-svn: 144473
2011-11-12 22:39:37 +00:00
8ec1a92afd
Linear scan is going away.
...
llvm-svn: 144472
2011-11-12 22:39:34 +00:00
654d60888e
XFAIL test that depends on linear scan to remove dead code.
...
Filed PR11364 to track the problem. Should the register allocator
eliminate dead code?
llvm-svn: 144471
2011-11-12 22:39:30 +00:00
fa3a8ee6e2
Remove obsolete test.
...
This test was committed with a bugfix to RemoveCopyByCommutingDef, but
that optimization is no longer triggered by this test.
llvm-svn: 144470
2011-11-12 22:39:27 +00:00
80b3d299a9
Remove obsolete test.
...
This test is for a very specific LocalRewriter bug. LocalRewriter is
going away.
llvm-svn: 144469
2011-11-12 22:39:24 +00:00
0c7d9d90ef
Remove obsolete test.
...
I don't think this test does what is was supposed to do, and
LocalRewriter is going away anyway.
llvm-svn: 144463
2011-11-12 20:37:57 +00:00
126f9779c3
Eliminate more linear scan tests.
...
llvm-svn: 144462
2011-11-12 20:35:26 +00:00
9d090daa33
Switch a couple -O0 tests to RABasic.
...
llvm-svn: 144461
2011-11-12 20:11:04 +00:00
4deff7bc1d
Switch a few tests off linearscan.
...
llvm-svn: 144460
2011-11-12 19:53:52 +00:00
6ac6aa782d
Delete old test of a VirtRegRewriter feature.
...
This test doesn't expose the issue with RAGreedy.
I filed PR11363 to track the missing InlineSpiller feature.
llvm-svn: 144459
2011-11-12 19:53:48 +00:00
74d091b395
Remove old test that doesn't make sense.
...
The test is checking that the output doesn't contains any 'mov '
strings. It does contain movl, though.
llvm-svn: 144458
2011-11-12 19:53:45 +00:00
3dc75f9e3b
Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
...
llvm-svn: 144457
2011-11-12 09:58:49 +00:00
d48ab84556
Don't try to loop on iterators that are potentially invalidated inside the loop. Fixes PR11361!
...
llvm-svn: 144454
2011-11-12 03:09:12 +00:00
ecb453805d
Make sure scalarrepl picks the correct alloca when it rewrites a bitcast. Fixes PR11353.
...
llvm-svn: 144442
2011-11-12 02:07:50 +00:00
e7cc8bff82
The dwarf standard says that the only differences between a out-of-line
...
instance and a concrete inlined instance are the use of DW_TAG_subprogram
instead of DW_TAG_inlined_subroutine and the who owns the tree.
We were also omitting DW_AT_inline from the abstract roots. To fix this,
make sure we mark abstract instance roots with DW_AT_inline even when
we have only out-of-line instances referring to them with DW_AT_abstract_origin.
FileCheck is not a very good tool for tests like this, maybe we should add
a -verify mode to llvm-dwarfdump.
llvm-svn: 144441
2011-11-12 01:57:54 +00:00
9d448e4a42
Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029.
...
llvm-svn: 144438
2011-11-12 00:35:34 +00:00
609d113874
ARM optional size suffix for VLDR/VSTR syntax.
...
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
a7ebc5617d
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
...
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
ab1a4a2301
Loosen test by using REs. Approved by Devang.
...
llvm-svn: 144425
2011-11-11 23:25:38 +00:00
28c1d18434
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
...
Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
85a2343b01
ARM allow Q registers in vldm/vstm register lists.
...
rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
a90cb76489
Move X86 specific test in X86 directory.
...
llvm-svn: 144395
2011-11-11 18:13:19 +00:00
a39794b029
Move X86 specific test in X86 directory.
...
llvm-svn: 144394
2011-11-11 18:10:38 +00:00
089cc53232
allow non-device function calls in PTX when natively handling device-side printf
...
llvm-svn: 144388
2011-11-11 14:45:12 +00:00
ea28a34c43
Add lowering for AVX2 shift instructions.
...
llvm-svn: 144380
2011-11-11 07:39:23 +00:00
7ddd63ce4e
Add support for using immediates with select instructions.
...
rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
c4a001478c
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
...
llvm-svn: 144361
2011-11-11 03:16:38 +00:00
0a309292c4
Get rid of an optimization in SCCP which appears to have many issues. Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which
...
lead to it trying to re-mark a value marked as a constant with a different value. It also appears to trigger very rarely.
Fixes PR11357.
llvm-svn: 144352
2011-11-11 01:16:15 +00:00
2a3503e061
Add support for using MVN to materialize negative constants.
...
rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
9bded9dc24
Thumb2 parsing for push/pop w/ hi registers in the reglist.
...
rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
79278365d3
Check in getOrCreateSubprogramDIE if a declaration exists and if so output
...
it first.
This is a more general fix to pr11300.
llvm-svn: 144324
2011-11-10 22:34:29 +00:00
5a5ce63742
Thumb MUL assembly parsing for 3-operand form.
...
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
d1762e00e2
When in ARM mode, LDRH/STRH require special handling of negative offsets.
...
For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
c14871cc67
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
61db5a59f7
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
270354100a
test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd bots to specify explicit -mtriple=x86_64-darwin.
...
I guess it expects -relocation-model=pic.
llvm-svn: 144290
2011-11-10 14:18:59 +00:00
d33b2d6b7a
Use a bigger hammer to fix PR11314 by disabling the "forcing two-address
...
instruction lower optimization" in the pre-RA scheduler.
The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.
Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.
llvm-svn: 144267
2011-11-10 07:43:16 +00:00
3fbd094ad9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
eef48b6938
Strip old implicit operands after foldMemoryOperand.
...
The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction. This is not what we want when those implicit
operands refer to the register being spilled.
Implicit operands referring to other registers are preserved.
This fixes PR11347.
llvm-svn: 144247
2011-11-10 00:17:03 +00:00
25bc090170
Thumb2 assembly parsing STMDB w/ optional .w suffix.
...
rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
2d4055b683
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
...
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
856977cb15
DeadStoreElimination can now trim the size of a store if the end of the store is dead.
...
Currently checks alignment and killing stores on a power of 2 boundary as this is likely
to trim the size of the earlier store without breaking large vector stores into scalar ones.
Fixes <rdar://problem/10140300>
llvm-svn: 144239
2011-11-09 23:07:35 +00:00
53218b6fcc
Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319.
...
llvm-svn: 144216
2011-11-09 22:25:12 +00:00
1938482bfa
AVX2: Add patterns for variable shift operations
...
llvm-svn: 144212
2011-11-09 21:22:13 +00:00
c22f6518b2
Use REs to remove dependencies on the register allocation order.
...
llvm-svn: 144209
2011-11-09 20:06:13 +00:00
635e4efca0
Speculatively revert commit 144124 (djg) in the hope that the 32 bit
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dragonegg self-host buildbot will recover (it is complaining about object
files differing between different build stages). Original commit message:
Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.
llvm-svn: 144188
2011-11-09 14:20:48 +00:00
79135d844d
Add AVX2 support for vselect of v32i8
...
llvm-svn: 144187
2011-11-09 13:21:28 +00:00
f87a2bef51
Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions.
...
llvm-svn: 144179
2011-11-09 09:37:21 +00:00
c9eb09d3b8
Add instruction selection for AVX2 integer comparisons.
...
llvm-svn: 144176
2011-11-09 08:06:13 +00:00
8c8a431057
Add AVX2 instruction lowering for add, sub, and mul.
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llvm-svn: 144174
2011-11-09 07:28:55 +00:00
0485d51a76
Don't forget to check FlagNW when determining whether an AddRecExpr will wrap
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or not. Patch by Brendon Cahoon!
llvm-svn: 144173
2011-11-09 07:11:37 +00:00
595d419427
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
3dc89c9768
Collapse DomainValues across loop back-edges.
...
During the initial RPO traversal of the basic blocks, remember the ones
that are incomplete because of back-edges from predecessors that haven't
been visited yet.
After the initial RPO, revisit all those loop headers so the incoming
DomainValues on the back-edges can be properly collapsed.
This will properly fix execution domains on software pipelined code,
like the included test case.
llvm-svn: 144151
2011-11-09 01:06:56 +00:00
a4bc6171a5
Add a hack to the scheduler to disable pseudo-two-address dependencies in
...
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.
llvm-svn: 144124
2011-11-08 21:29:06 +00:00
c3770ac687
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
...
llvm-svn: 144123
2011-11-08 21:21:09 +00:00
0bae8b2cfb
Fix code to match comment. Fixes PR11340, a regression from r143209.
...
llvm-svn: 144121
2011-11-08 21:08:02 +00:00
9ee220915b
LICM pass now understands invariant load metadata. Nothing generates this yet so it will currently never get used in real tests
...
llvm-svn: 144107
2011-11-08 19:30:00 +00:00
fbbbd04705
Adding test for machine-licm operating on invariant load instructions
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llvm-svn: 144104
2011-11-08 19:06:53 +00:00
b85fcd07df
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
...
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
llvm-svn: 144102
2011-11-08 18:56:23 +00:00
d8d583f766
test/CodeGen/X86/vec_shuffle-39.ll: Add explicit -mtriple=x86_64-linux. Passing packed value is not compatible on Win32 x64.
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llvm-svn: 144068
2011-11-08 03:46:39 +00:00
ac9ef21f02
test/CodeGen/X86/vec_shuffle-38.ll: Relax expression for Win32 x64.
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llvm-svn: 144067
2011-11-08 03:46:32 +00:00
33dac06330
test/CodeGen/X86/vec_shuffle.ll: Add explicit -mtriple=i686-linux. We may see some suboptimal frame (%ebp) emission on certain hosts. Possible [PR11031]
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llvm-svn: 144066
2011-11-08 03:46:25 +00:00
6f84fed675
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
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llvm-svn: 144057
2011-11-08 01:43:53 +00:00
f2a9bd4b1e
Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318.
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Re-commit of r144034, with an extra fix so that RemoveDeadNode doesn't blow up.
llvm-svn: 144055
2011-11-08 01:25:24 +00:00
91b56e0390
Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222
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llvm-svn: 144052
2011-11-08 00:31:58 +00:00
2a917595d2
Convert to the new EH model.
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llvm-svn: 144050
2011-11-08 00:23:01 +00:00
2197b015c8
Convert to the new EH model.
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llvm-svn: 144049
2011-11-08 00:17:28 +00:00
9b7942a543
Convert tests to the new EH model.
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llvm-svn: 144048
2011-11-08 00:09:27 +00:00
5de1bea5c9
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
...
callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
2dc40434aa
Added missing newline
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llvm-svn: 144046
2011-11-08 00:03:24 +00:00
a35a5295e0
Revert r144034 while I try to track down a crash.
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llvm-svn: 144044
2011-11-07 23:53:20 +00:00
9279f9efbc
Fix test for Windows as well.
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llvm-svn: 144038
2011-11-07 23:10:43 +00:00
a70e9417fb
Kill and collapse outstanding DomainValues.
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DomainValues that are only used by "don't care" instructions are now
collapsed to the first possible execution domain after all basic blocks
have been processed. This typically means the PS domain on x86.
For example, the vsel_i64 and vsel_double functions in sse2-blend.ll are
completely collapsed to the PS domain instead of containing a mix of
execution domains created by isel.
llvm-svn: 144037
2011-11-07 23:08:21 +00:00
7a4be01ac8
InstCombine now optimizes vector udiv by power of 2 to shifts
...
Fixes r8429
llvm-svn: 144036
2011-11-07 23:04:49 +00:00
55a86d32d3
Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318.
...
llvm-svn: 144034
2011-11-07 22:51:10 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
7f076cb6cc
Fix test for Linux.
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llvm-svn: 144003
2011-11-07 20:47:23 +00:00
0241308954
Expand V_SET0 to xorps by default.
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The xorps instruction is smaller than pxor, so prefer that encoding.
The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.
llvm-svn: 143996
2011-11-07 19:15:58 +00:00
a6d409d543
Add AVX2 variable shift instructions and intrinsics.
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llvm-svn: 143915
2011-11-07 08:26:24 +00:00
ff39be0afc
Add AVX2 VPMOVMASK instructions and intrinsics.
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llvm-svn: 143904
2011-11-07 03:20:35 +00:00
e122dcbf4a
Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects.
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llvm-svn: 143902
2011-11-07 02:00:04 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
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llvm-svn: 143895
2011-11-06 23:04:08 +00:00
05d1cb98e7
Add more AVX2 instructions and intrinsics.
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llvm-svn: 143861
2011-11-06 06:12:20 +00:00
d0191a53c9
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
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zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
807cf22b55
Update lit's list of tools.
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llvm-svn: 143815
2011-11-05 16:20:52 +00:00
c74798d5cf
Add an option to pad an uleb128 to MCObjectWriter and remove the uleb128 encoding from the DWARF asm printer.
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As a side effect we now print dwarf ulebs with .ascii directives.
llvm-svn: 143809
2011-11-05 11:52:44 +00:00
f2905afe62
Do simple cross-block DSE when we encounter a free statement. Fixes PR11240.
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llvm-svn: 143808
2011-11-05 10:48:42 +00:00
8f249600e7
Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes.
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I'm going to wait for any review comments and perform some additional testing before turning this on by default.
llvm-svn: 143750
2011-11-04 23:46:11 +00:00
21079cad11
build/cmake: Change to require Python be available.
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llvm-svn: 143742
2011-11-04 23:04:05 +00:00
c2a8401ad2
Add triple to test.
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llvm-svn: 143735
2011-11-04 20:20:34 +00:00
6cf4e830ce
Emit declarations before definitions if they are available. This causes DW_AT_specification to
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point back in the file in the included testcase. Fixes PR11300.
llvm-svn: 143726
2011-11-04 19:00:29 +00:00
ce3d6248b2
Add tests for existing InstSimplify features.
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llvm-svn: 143721
2011-11-04 18:39:16 +00:00
85977e6ab4
Teach instsimplify to simplify calls to undef.
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llvm-svn: 143719
2011-11-04 18:32:42 +00:00
b9a46e6b83
Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions
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llvm-svn: 143682
2011-11-04 06:59:21 +00:00
f3e73ad5da
Add fast-isel support for returning i1, i8, and i16.
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llvm-svn: 143669
2011-11-04 00:50:21 +00:00
e6d40de414
Speculatively revert "DeadStoreElimination can now trim the size of a store if
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the end of it is dead.", which appears to break bootstrapping LLVM.
llvm-svn: 143668
2011-11-04 00:48:26 +00:00
198b7ffc11
Reapply r143206, with fixes. Disallow physical register lifetimes
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across calls, and only check for nested dependences on the special
call-sequence-resource register.
llvm-svn: 143660
2011-11-03 21:49:52 +00:00
65ba66c660
Reverted r143600 - selector reference change
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llvm-svn: 143646
2011-11-03 20:47:50 +00:00
b68515c232
fixed global array handling for ptx to use the correct bit widths
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llvm-svn: 143640
2011-11-03 19:24:46 +00:00
8a95aedb5d
DeadStoreElimination can now trim the size of a store if the end of it is dead.
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Only currently done if the later store is writing to a power of 2 address or
has the same alignment as the earlier store as then its likely to not break up
large stores into smaller ones
Fixes <rdar://problem/10140300>
llvm-svn: 143630
2011-11-03 18:01:56 +00:00
0e7cbbabea
Add new X86 AVX2 VBROADCAST instructions.
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llvm-svn: 143612
2011-11-03 07:35:53 +00:00
bf5f4bec1a
Add support for sign-extending non-legal types in SelectSIToFP().
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llvm-svn: 143603
2011-11-03 02:04:59 +00:00
e6173d81ae
Treat objc selector reference globals as invariant so that MachineLICM can hoist them out of loops. Fixes <rdar://problem/6027699>
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llvm-svn: 143600
2011-11-03 00:56:36 +00:00
9929c423a1
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
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llvm-svn: 143582
2011-11-02 22:52:45 +00:00
000307fef9
I added the first test to run llvm-dwarfdump.
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llvm-svn: 143571
2011-11-02 21:02:27 +00:00
d1ee7f8cf1
Don't emit a directory entry for the value in DW_AT_comp_dir, that is always
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implied by directory index zero.
llvm-svn: 143570
2011-11-02 20:55:33 +00:00
9cf803c4bf
Add support for comparing integer non-legal types.
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llvm-svn: 143559
2011-11-02 18:08:25 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
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llvm-svn: 143557
2011-11-02 18:03:14 +00:00
5aba1b4ea3
tests: Clean up tests/CMakeLists.txt to drop some variable configuration we no
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longer need substitutions for.
llvm-svn: 143555
2011-11-02 17:54:51 +00:00
c2c79c90f2
Rewrite LinearFunctionTestReplace to handle pointer-type IVs.
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We've been hitting asserts in this code due to the many supported
combintions of modes (iv-rewrite/no-iv-rewrite) and IV types. This
second rewrite of the code attempts to deal with these cases systematically.
llvm-svn: 143546
2011-11-02 17:19:57 +00:00
a47b05c7f3
More AVX2 instructions and intrinsics.
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llvm-svn: 143536
2011-11-02 06:54:17 +00:00
682b850602
Add a bunch more X86 AVX2 instructions and their corresponding intrinsics.
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llvm-svn: 143529
2011-11-02 04:42:13 +00:00
0dae890346
Broaden an assert to handle enable-iv-rewrite=true following r143183.
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Narrowest possible fix for PR11279.
llvm-svn: 143522
2011-11-02 00:02:45 +00:00
82ed3be1fb
Fixed a bug in the code to create a dwarf file and directory table entires when
...
it is separating the directory part from the basename of the FileName. Noticed
that this:
.file 1 "dir/foo"
when assembled got the two parts switched. Using the Mac OS X dwarfdump tool
it can be seen easily:
% dwarfdump -a a.out
include_directories[ 1] = 'foo'
Dir Mod Time File Len File Name
---- ---------- ---------- ---------------------------
file_names[ 1] 1 0x00000000 0x00000000 dir
...
Which should be:
...
include_directories[ 1] = 'dir'
Dir Mod Time File Len File Name
---- ---------- ---------- ---------------------------
file_names[ 1] 1 0x00000000 0x00000000 foo
llvm-svn: 143521
2011-11-01 23:39:05 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
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llvm-svn: 143507
2011-11-01 22:18:13 +00:00
3f5eccbe7a
Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289.
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llvm-svn: 143498
2011-11-01 21:18:39 +00:00
56ce0932db
Don't fold negative offsets into cp / dp accesses to avoid relocation errors.
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This can happen if the address + addend is less than the start of the cp / dp.
llvm-svn: 143459
2011-11-01 11:31:53 +00:00
37fe7d6641
Combine various XCore tests for floating point intrinsic support into a single test.
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llvm-svn: 143458
2011-11-01 10:51:48 +00:00
8591b6b0ab
Move various XCore tests to FileCheck
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llvm-svn: 143457
2011-11-01 10:41:28 +00:00
fec80c6ad2
Fix operand type for x86 pmadd_ub_sw intrinsic.
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llvm-svn: 143455
2011-11-01 07:25:22 +00:00
a49b828f8f
Make sure we use the right insertion point when instcombine replaces a PHI with another instruction. (Specifically, don't insert an arbitrary instruction before a PHI.) Fixes PR11275.
...
llvm-svn: 143437
2011-11-01 04:49:29 +00:00
0eb88775ef
Move x86-specific tests into X86 folder.
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llvm-svn: 143424
2011-11-01 03:21:48 +00:00
6185a2aa7c
Move another test requiring x86 into X86 directory.
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llvm-svn: 143421
2011-11-01 03:12:47 +00:00
2cd281ea67
Move test requiring x86 backend into X86 directory.
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llvm-svn: 143420
2011-11-01 03:11:41 +00:00
1c1a2b8123
Change the actual tests to match the input directory rename (duh)
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llvm-svn: 143404
2011-10-31 23:56:52 +00:00
da5e57cba1
Rename "TestObjectFiles" to "Inputs" (like the pattern for Clang tests)
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llvm-svn: 143400
2011-10-31 23:46:38 +00:00
300dcb8e37
Move test to the X86 directory, note the PR number and only run MC once.
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llvm-svn: 143352
2011-10-31 17:23:09 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
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llvm-svn: 143351
2011-10-31 17:17:32 +00:00
9821e75e64
Fix operand type for int_x86_ssse3_phadd_sw_128 intrinsic
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llvm-svn: 143336
2011-10-31 07:16:37 +00:00
242d1f8c73
Test case for X86 FS/GS Base intrinsics
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llvm-svn: 143332
2011-10-31 02:15:47 +00:00
cfcfdf2aab
Begin adding AVX2 instructions. No selection support yet other than intrinsics.
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llvm-svn: 143331
2011-10-31 02:15:10 +00:00
aab6169ef6
Switch new .file directive emission off by default, change llc's flag for it to
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-enable-dwarf-directory.
llvm-svn: 143326
2011-10-31 01:06:02 +00:00
3d5692a475
Reapply commit 143214 with a fix: m_ICmp doesn't match conditions
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with the given predicate, it matches any condition and returns the
predicate - d'oh! Original commit message:
The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex. We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.
llvm-svn: 143318
2011-10-30 19:56:36 +00:00
7402ee6ec2
X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.
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llvm-svn: 143315
2011-10-30 17:31:21 +00:00
9cdb9ffa43
Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers.
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llvm-svn: 143313
2011-10-30 17:22:45 +00:00
c602b2c4de
Fix pr11266.
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On x86: (shl V, 1) -> add V,V
Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.
llvm-svn: 143311
2011-10-30 13:24:22 +00:00
1dda6a8ce1
Stabilize the test by specifying an exact cpu target
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llvm-svn: 143307
2011-10-30 08:07:50 +00:00
bf6568b5d6
Add a new DAGCombine optimization for BUILD_VECTOR.
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If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.
llvm-svn: 143297
2011-10-29 21:23:04 +00:00
932de2bc86
Force SSE for this test.
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llvm-svn: 143291
2011-10-29 19:43:44 +00:00
594ee77964
SimplifyLibCalls: Use IRBuilder.CreateGlobalString when creating a string for printf->puts, which correctly sets the unnamed_addr bit on the resulting GlobalVariable.
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Fixes PR11264.
llvm-svn: 143289
2011-10-29 19:43:31 +00:00
3af3c046a9
Revert r143214; it's breaking a bunch of stuff.
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llvm-svn: 143265
2011-10-29 00:56:07 +00:00
9b9c970148
Revert r143206, as there are still some failing tests.
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llvm-svn: 143262
2011-10-29 00:41:52 +00:00
6e315dd8ba
test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now.
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llvm-svn: 143247
2011-10-28 23:11:03 +00:00
b009a872d7
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
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When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
llvm-svn: 143235
2011-10-28 22:36:30 +00:00
5524ce7d82
Fix illegal disassembly testcase.
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llvm-svn: 143231
2011-10-28 21:45:09 +00:00
280bc553b3
The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
...
Spotted by my super-optimizer in 186.crafty and 450.soplex. We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.
llvm-svn: 143214
2011-10-28 19:01:20 +00:00
985ba6386d
A shift of a power of two is a power of two or zero.
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For completeness - not spotted in the wild.
llvm-svn: 143211
2011-10-28 18:30:05 +00:00
92af0a8a7f
Fold icmp ugt (udiv X, Y), X to false. Spotted by my super-optimizer
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in 186.crafty.
llvm-svn: 143209
2011-10-28 18:17:44 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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llvm-svn: 143208
2011-10-28 18:02:13 +00:00
73057ad24f
Reapply r143177 and r143179 (reverting r143188), with scheduler
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fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
llvm-svn: 143206
2011-10-28 17:55:38 +00:00
7a49575d7f
Thumb2 ADD/SUB instructions encoding selection outside IT block.
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Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
llvm-svn: 143201
2011-10-28 16:57:07 +00:00
7636f55348
test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction.
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FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?
llvm-svn: 143195
2011-10-28 14:12:30 +00:00
29ccdd8207
Dwarf: [PR11022] Fix emitting DW_AT_const_value(>i64), to be host-endian-neutral.
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Don't assume APInt::getRawData() would hold target-aware endianness nor host-compliant endianness. rawdata[0] holds most lower i64, even on big endian host.
FIXME: Add a testcase for big endian target.
FIXME: Ditto on CompileUnit::addConstantFPValue() ?
llvm-svn: 143194
2011-10-28 14:12:22 +00:00
88dd835f09
test/CodeGen/X86/2010-08-10-DbgConstant.ll: Add explicit -mtriple=i686-linux. It must be for elf!
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llvm-svn: 143189
2011-10-28 10:50:52 +00:00
225a7037d6
Speculatively disable Dan's commits 143177 and 143179 to see if
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it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
llvm-svn: 143188
2011-10-28 09:55:57 +00:00
cc64ae140d
Always use the string pool, even when it makes the .o larger. This may help
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tools that read the debug info in the .o files by making the DIE sizes more
consistent.
llvm-svn: 143186
2011-10-28 05:29:47 +00:00
effdca9441
LFTR should avoid a type mismatch with null pointer IVs.
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Fixes rdar://10359193 Indvar LinearFunctionTestReplace assertion
llvm-svn: 143183
2011-10-28 03:45:11 +00:00
4db3f7dd83
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
...
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
llvm-svn: 143177
2011-10-28 01:29:32 +00:00
080a499ee0
ARM Allow 'q' registers in VLD/VST vector lists.
...
Just treat it as if the constituent D registers where specified.
rdar://10348896
llvm-svn: 143167
2011-10-28 00:06:50 +00:00
4c9fca99c9
Remove the Alpha backend.
...
llvm-svn: 143164
2011-10-27 22:56:32 +00:00
f211416dde
Add testcase for r143162.
...
llvm-svn: 143163
2011-10-27 22:54:14 +00:00
e5a6adceac
Also set addrmode6 alignment when align==size.
...
Previously, we were only setting the alignment bits on over-aligned
loads and stores.
llvm-svn: 143160
2011-10-27 22:39:16 +00:00
f4807a19e8
Avoid partial CPSR dependency from loop backedges. rdar://10357570
...
llvm-svn: 143145
2011-10-27 21:21:05 +00:00
a054790390
tests: Rip out a bunch of now unused test code relating to use of llvm-gcc in LLVM tests.
...
llvm-svn: 143143
2011-10-27 20:59:26 +00:00
f7223fcc80
tests: Remove llvm2cpp, I'm pretty sure no one uses this.
...
llvm-svn: 143142
2011-10-27 20:59:21 +00:00
7cb61e5a0e
Reapply commit 143028 with a fix: the problem was casting a ConstantExpr Mul
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using BinaryOperator (which only works for instructions) when it should have
been a cast to OverflowingBinaryOperator (which also works for constants).
While there, correct a few other dubious looking uses of BinaryOperator.
Thanks to Chad Rosier for the testcase. Original commit message:
My super-optimizer noticed that we weren't folding this expression to
true: (x *nsw x) sgt 0, where x = (y | 1). This occurs in 464.h264ref.
llvm-svn: 143125
2011-10-27 19:16:21 +00:00
652f576a70
2>&1 doesn't work here, it just creates an empty file called "&1"
...
llvm-svn: 143117
2011-10-27 18:27:45 +00:00
ce63700797
Changed test to check for correct load size instead of shift as the shift might change if optimised
...
llvm-svn: 143116
2011-10-27 18:15:58 +00:00
49e6a0da7e
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
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not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
llvm-svn: 143112
2011-10-27 17:40:41 +00:00
6ed3845530
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
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rdar://10348844
llvm-svn: 143110
2011-10-27 17:33:59 +00:00
ba7f90c7df
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
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rdar://10348584
llvm-svn: 143108
2011-10-27 17:16:55 +00:00
1455ce27e4
Revert Duncan's r143028 expression folding which appears to be the culprit
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behind a compile failure on 483.xalancbmk.
llvm-svn: 143102
2011-10-27 15:47:25 +00:00
d59c0cac6c
Teach our Dwarf emission to use the string pool.
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llvm-svn: 143097
2011-10-27 06:44:11 +00:00
e9e356ad6b
Don't crash on 128-bit sdiv by constant. Found by inspection.
...
llvm-svn: 143095
2011-10-27 02:06:39 +00:00
73beaf7bbc
It is not safe to sink an alloca into a stacksave/stackrestore pair, so don't do that. <rdar://problem/10352360>
...
llvm-svn: 143093
2011-10-27 01:33:51 +00:00
d24e7e1d9b
A branch predicated on a constant can just FastEmit an unconditional branch.
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llvm-svn: 143086
2011-10-27 00:21:16 +00:00
61fdba048f
Thumb2 ldr pc-relative encoding fixes.
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We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
llvm-svn: 143068
2011-10-26 22:22:01 +00:00
f5a15529a7
Run test with -verify-machineinstrs.
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Patch by Sanjoy Das.
llvm-svn: 143066
2011-10-26 21:20:26 +00:00
b3285224cd
Fixes an issue reported by -verify-machineinstrs.
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Patch by Sanjoy Das.
llvm-svn: 143064
2011-10-26 21:16:41 +00:00
66393c127d
This commit introduces two fake instructions MORESTACK_RET and
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MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively. Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV). It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.
Patch by Sanjoy Das.
llvm-svn: 143062
2011-10-26 21:12:27 +00:00
c47e283430
Make sure short memsets on ARM lower to stores, even when optimizing for size.
...
llvm-svn: 143055
2011-10-26 20:56:52 +00:00
ba286d7c73
The maximum power of 2 dividing a power of 2 is itself. This occurs
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in 403.gcc and was spotted by my super-optimizer.
llvm-svn: 143054
2011-10-26 20:55:21 +00:00
25d4707c4d
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
...
llvm-svn: 143034
2011-10-26 17:28:15 +00:00
1d2bb9882d
My super-optimizer noticed that we weren't folding this expression to
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true: (x *nsw x) sgt 0, where x = (y | 1). This occurs in 464.h264ref.
llvm-svn: 143028
2011-10-26 15:31:51 +00:00
dd9137aa56
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
...
llvm-svn: 143023
2011-10-26 08:53:19 +00:00
043c9d3f7a
Revert part of r142530. The patch potentially hurts performance especially
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on Darwin platforms where -Os means optimize for size without hurting
performance.
llvm-svn: 143002
2011-10-26 01:17:44 +00:00
6ebf401412
The bitcode reader can create an shuffle with a place holder mask which it will
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fix up later. For this special case, allow such a mask to be considered valid.
<rdar://problem/8622574>
llvm-svn: 142992
2011-10-26 00:34:48 +00:00
8ab7b036f7
Object: change test to create archive.
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llvm-svn: 142982
2011-10-25 22:30:58 +00:00
67a5df5329
Add a few test cases to ensure the bitcode reader is backward compatible with
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LLVM 2.9. My understanding is that we plan to maintain compatibility with 2.9
until the 3.1 release. At that time we can generate new test cases using LLVM
3.0.
llvm-svn: 142958
2011-10-25 20:33:19 +00:00
1248500425
Simplify tests by not piping them through llvm-dis.
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llvm-svn: 142948
2011-10-25 19:59:50 +00:00
a370f3e34e
Restore commits 142790 and 142843 - they weren't breaking the build
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bots. Original commit messages:
- Reapply r142781 with fix. Original message:
Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
loop header when computing the trip count.
With this, we now constant evaluate:
struct ListNode { const struct ListNode *next; int i; };
static const struct ListNode node1 = {0, 1};
static const struct ListNode node2 = {&node1, 2};
static const struct ListNode node3 = {&node2, 3};
int test() {
int sum = 0;
for (const struct ListNode *n = &node3; n != 0; n = n->next)
sum += n->i;
return sum;
}
- Now that we look at all the header PHIs, we need to consider all the header PHIs
when deciding that the loop has stopped evolving. Fixes miscompile in the gcc
torture testsuite!
llvm-svn: 142919
2011-10-25 12:28:52 +00:00
32f46e7c07
Fix the API usage in loop probability heuristics. It was incorrectly
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classifying many edges as exiting which were in fact not. These mainly
formed edges into sub-loops. It was also not correctly classifying all
returning edges out of loops as leaving the loop. With this match most
of the loop heuristics are more rational.
Several serious regressions on loop-intesive benchmarks like perlbench's
loop tests when built with -enable-block-placement are fixed by these
updated heuristics. Unfortunately they in turn uncover some other
regressions. There are still several improvemenst that should be made to
loop heuristics including trip-count, and early back-edge management.
llvm-svn: 142917
2011-10-25 09:47:41 +00:00
805c5b92c8
Speculatively revert commits 142790 and 142843 to see if it fixes
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the dragonegg and llvm-gcc self-host buildbots. Original commit
messages:
- Reapply r142781 with fix. Original message:
Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
loop header when computing the trip count.
With this, we now constant evaluate:
struct ListNode { const struct ListNode *next; int i; };
static const struct ListNode node1 = {0, 1};
static const struct ListNode node2 = {&node1, 2};
static const struct ListNode node3 = {&node2, 3};
int test() {
int sum = 0;
for (const struct ListNode *n = &node3; n != 0; n = n->next)
sum += n->i;
return sum;
}
- Now that we look at all the header PHIs, we need to consider all the header PHIs
when deciding that the loop has stopped evolving. Fixes miscompile in the gcc
torture testsuite!
llvm-svn: 142916
2011-10-25 09:26:43 +00:00
48d436618d
Fix these test cases to not use .bc files. Otherwise, we run into issues with
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bitcode reader/writer backward compatibility.
llvm-svn: 142896
2011-10-25 01:22:20 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
b43c36f391
Remove the Blackfin backend.
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llvm-svn: 142880
2011-10-25 00:05:42 +00:00
dfc96aea90
Remove the SystemZ backend.
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llvm-svn: 142878
2011-10-24 23:48:32 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
a5e244c08d
Don't crash on variable insertelement on ARM. PR10258.
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llvm-svn: 142871
2011-10-24 23:08:52 +00:00
57e3aaad89
Check the visibility of the global variable before placing it into the stubs
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table. A hidden variable could potentially end up in both lists.
<rdar://problem/10336715>
llvm-svn: 142869
2011-10-24 23:05:43 +00:00
3ea0657d54
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
a58fb48a55
Now that we look at all the header PHIs, we need to consider all the header PHIs
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when deciding that the loop has stopped evolving. Fixes miscompile in the gcc
torture testsuite!
llvm-svn: 142843
2011-10-24 21:02:38 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
...
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
2c9bda1512
Remove the explicit request for "Latency" scheduling from MSP430,
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as the Latency scheduler is going away.
llvm-svn: 142811
2011-10-24 17:53:16 +00:00
c32af340fc
Change the default scheduler from Latency to ILP, since Latency
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is going away.
llvm-svn: 142810
2011-10-24 17:45:02 +00:00
3adec13c3e
Update test for r142801.
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llvm-svn: 142806
2011-10-24 17:26:26 +00:00
d48d52e7b2
XFAIL test on leak checkers.
...
llvm-svn: 142804
2011-10-24 17:24:05 +00:00
7111f4564c
Remove return heuristics from the static branch probabilities, and
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introduce no-return or unreachable heuristics.
The return heuristics from the Ball and Larus paper don't work well in
practice as they pessimize early return paths. The only good hitrate
return heuristics are those for:
- NULL return
- Constant return
- negative integer return
Only the last of these three can possibly require significant code for
the returning block, and even the last is fairly rare and usually also
a constant. As a consequence, even for the cold return paths, there is
little code on that return path, and so little code density to be gained
by sinking it. The places where sinking these blocks is valuable (inner
loops) will already be weighted appropriately as the edge is a loop-exit
branch.
All of this aside, early returns are nearly as common as all three of
these return categories, and should actually be predicted as taken!
Rather than muddy the waters of the static predictions, just remain
silent on returns and let the CFG itself dictate any layout or other
issues.
However, the return heuristic was flagging one very important case:
unreachable. Unfortunately it still gave a 1/4 chance of the
branch-to-unreachable occuring. It also didn't do a rigorous job of
finding those blocks which post-dominate an unreachable block.
This patch builds a more powerful analysis that should flag all branches
to blocks known to then reach unreachable. It also has better worst-case
runtime complexity by not looping through successors for each block. The
previous code would perform an N^2 walk in the event of a single entry
block branching to N successors with a switch where each successor falls
through to the next and they finally fall through to a return.
Test case added for noreturn heuristics. Also doxygen comments improved
along the way.
llvm-svn: 142793
2011-10-24 12:01:08 +00:00
9be7f277e4
Reapply r142781 with fix. Original message:
...
Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
loop header when computing the trip count.
With this, we now constant evaluate:
struct ListNode { const struct ListNode *next; int i; };
static const struct ListNode node1 = {0, 1};
static const struct ListNode node2 = {&node1, 2};
static const struct ListNode node3 = {&node2, 3};
int test() {
int sum = 0;
for (const struct ListNode *n = &node3; n != 0; n = n->next)
sum += n->i;
return sum;
}
llvm-svn: 142790
2011-10-24 06:57:05 +00:00
dd1d3df524
A dead malloc, a free(NULL) and a free(undef) are all trivially dead
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instructions.
This doesn't introduce any optimizations we weren't doing before (except
potentially due to pass ordering issues), now passes will eliminate them sooner
as part of their own cleanups.
llvm-svn: 142787
2011-10-24 04:35:36 +00:00
9d28c26d77
Speculatively revert r142781. Bots are showing
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Assertion `i_nocapture < OperandTraits<PHINode>::operands(this) && "getOperand() out of range!"' failed.
coming out of indvars.
llvm-svn: 142786
2011-10-24 04:00:25 +00:00
1700007ecc
Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
...
loop header when computing the trip count.
With this, we now constant evaluate:
struct ListNode { const struct ListNode *next; int i; };
static const struct ListNode node1 = {0, 1};
static const struct ListNode node2 = {&node1, 2};
static const struct ListNode node3 = {&node2, 3};
int test() {
int sum = 0;
for (const struct ListNode *n = &node3; n != 0; n = n->next)
sum += n->i;
return sum;
}
llvm-svn: 142781
2011-10-23 23:43:14 +00:00
b05d9e9bea
Add X86 SARX, SHRX, and SHLX instructions.
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llvm-svn: 142779
2011-10-23 22:18:24 +00:00
1c8ace0e89
Teach the BranchProbabilityInfo pass to print its results, and use that
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to bring it under direct test instead of merely indirectly testing it in
the BlockFrequencyInfo pass.
The next step is to start adding tests for the various heuristics
employed, and to start fixing those heuristics once they're under test.
llvm-svn: 142778
2011-10-23 21:21:50 +00:00
bd1be4d01c
Completely re-write the algorithm behind MachineBlockPlacement based on
...
discussions with Andy. Fundamentally, the previous algorithm is both
counter productive on several fronts and prioritizing things which
aren't necessarily the most important: static branch prediction.
The new algorithm uses the existing loop CFG structure information to
walk through the CFG itself to layout blocks. It coalesces adjacent
blocks within the loop where the CFG allows based on the most likely
path taken. Finally, it topologically orders the block chains that have
been formed. This allows it to choose a (mostly) topologically valid
ordering which still priorizes fallthrough within the structural
constraints.
As a final twist in the algorithm, it does violate the CFG when it
discovers a "hot" edge, that is an edge that is more than 4x hotter than
the competing edges in the CFG. These are forcibly merged into
a fallthrough chain.
Future transformations that need te be added are rotation of loop exit
conditions to be fallthrough, and better isolation of cold block chains.
I'm also planning on adding statistics to model how well the algorithm
does at laying out blocks based on the probabilities it receives.
The old tests mostly still pass, and I have some new tests to add, but
the nested loops are still behaving very strangely. This almost seems
like working-as-intended as it rotated the exit branch to be
fallthrough, but I'm not convinced this is actually the best layout. It
is well supported by the probabilities for loops we currently get, but
those are pretty broken for nested loops, so this may change later.
llvm-svn: 142743
2011-10-23 09:18:45 +00:00
980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
057fbb1a10
The element insertion code in scalar replacement doesn't handle incorrect
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element types, even though the element extraction code does. It is surprising
that this bug has been here for so long. Fixes <rdar://problem/10318778>.
llvm-svn: 142740
2011-10-23 07:02:10 +00:00
e94d277db8
Add X86 MULX instruction for disassembler.
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llvm-svn: 142738
2011-10-23 00:33:32 +00:00
52340ac5f8
Oops! Fix test I forgot to submit as part of r142735.
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llvm-svn: 142736
2011-10-22 22:07:31 +00:00
32f8051d66
A non-escaping malloc in the entry block is not unlike an alloca. Do dead-store
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elimination on them too.
llvm-svn: 142735
2011-10-22 21:59:35 +00:00
a6674c7fc9
Make SCEV's brute force analysis stronger in two ways. Firstly, we should be
...
able to constant fold load instructions where the argument is a constant.
Second, we should be able to watch multiple PHI nodes through the loop; this
patch only supports PHIs in loop headers, more can be done here.
With this patch, we now constant evaluate:
static const int arr[] = {1, 2, 3, 4, 5};
int test() {
int sum = 0;
for (int i = 0; i < 5; ++i) sum += arr[i];
return sum;
}
llvm-svn: 142731
2011-10-22 19:58:20 +00:00
e649d66552
Fix pr11193.
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SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.
llvm-svn: 142724
2011-10-22 12:39:25 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
...
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
688db1d6d0
Remap blockaddress correctly when inlining a function. Fixes PR10162.
...
llvm-svn: 142684
2011-10-21 20:45:19 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
...
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
...
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
ce818277fc
Extend instcombine's shufflevector simplification to handle more cases where the input and output vectors have different sizes. Patch by Xiaoyi Guo.
...
llvm-svn: 142671
2011-10-21 19:06:29 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
...
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
5e00bb5feb
Fix pr11194. When promoting and splitting integers we need to use
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ZExtPromotedInteger and SExtPromotedInteger based on the operation we legalize.
SetCC return type needs to be legalized via PromoteTargetBoolean.
llvm-svn: 142660
2011-10-21 17:35:19 +00:00
70a38058b1
Don't hard code the desired alignment for loops -- it isn't 16-bytes on
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all x86 systems. Sorry for the breakage.
llvm-svn: 142656
2011-10-21 16:41:39 +00:00
d315157f12
1. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC type.
...
2. Fix a typo in CONCAT_VECTORS which exposed the bug in #1 .
llvm-svn: 142648
2011-10-21 11:42:07 +00:00
8b9737cb54
Add loop aligning to MachineBlockPlacement based on review discussion so
...
it's a bit more plausible to use this instead of CodePlacementOpt. The
code for this was shamelessly stolen from CodePlacementOpt, and then
trimmed down a bit. There doesn't seem to be much utility in returning
true/false from this pass as we may or may not have rewritten all of the
blocks. Also, the statistic of counting how many loops were aligned
doesn't seem terribly important so I removed it. If folks would like it
to be included, I'm happy to add it back.
This was probably the most egregious of the missing features, and now
I'm going to start gathering some performance numbers and looking at
specific loop structures that have different layout between the two.
Test is updated to include both basic loop alignment and nested loop
alignment.
llvm-svn: 142645
2011-10-21 08:57:37 +00:00
ddfeaafdfb
Add a very basic test for MachineBlockPlacement. This is essentially the
...
canonical example I used when developing it, and is one of the primary
motivating real-world use cases for __builtin_expect (when burried under
a macro).
I'm working on more test cases here, but I'm trying to make sure both
that the pass is doing the right thing with the test cases and that they
aren't too brittle to changes elsewhere in the code generation pipeline.
Feedback and/or suggestions on how to test this are very welcome.
Especially feedback on whether testing the block comments is a good
strategy; I couldn't find any good examples to steal from but all the
other ideas I had were a lot uglier or more fragile.
llvm-svn: 142644
2011-10-21 08:01:56 +00:00
039a79067a
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
...
llvm-svn: 142642
2011-10-21 06:55:01 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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llvm-svn: 142626
2011-10-20 22:23:58 +00:00
608c60c773
Fix decoding tests for fixed MSR encodings.
...
llvm-svn: 142624
2011-10-20 22:01:48 +00:00
48da0ed477
Fix tests for corrected MSR encodings.
...
llvm-svn: 142622
2011-10-20 21:53:19 +00:00
9036c5cf2b
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
...
llvm-svn: 142583
2011-10-20 15:04:25 +00:00
3ad44e50b3
Tidy up formatting.
...
llvm-svn: 142582
2011-10-20 14:57:47 +00:00
8db25984a9
ARM VTBX (one register) assembly parsing and encoding.
...
llvm-svn: 142581
2011-10-20 14:48:50 +00:00
1923a330e6
Refactor code from inlining and globalopt that checks whether a function definition is unused, and enhance it so it can tell that functions which are only used by a blockaddress are in fact dead. This probably doesn't happen much on most code, but the Linux kernel's _THIS_IP_ can trigger this issue with blockaddress. (GlobalDCE can also handle the given tescase, but we only run that at -O3.) Found while looking at PR11180.
...
llvm-svn: 142572
2011-10-20 05:23:42 +00:00
462098824f
"@string = constant i8 0" is a value i8* string of length zero. Analyze that
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correctly in GetStringLength, fixing PR11181!
llvm-svn: 142558
2011-10-20 00:34:35 +00:00
add38c12b8
Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
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llvm-svn: 142557
2011-10-20 00:07:12 +00:00
54d678fff4
Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355
...
llvm-svn: 142550
2011-10-19 22:22:54 +00:00
8824472a25
Improve code generation for vselect on SSE2:
...
When checking the availability of instructions using the TLI, a 'promoted'
instruction IS available. It means that the value is bitcasted to another type
for which there is an operation. The correct check for the availablity of an
instruction is to check if it should be expanded.
llvm-svn: 142542
2011-10-19 20:43:16 +00:00
e0d0908356
Fix parsing of a line with only a # in it.
...
llvm-svn: 142537
2011-10-19 18:48:52 +00:00
2d768fd379
Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
...
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.
The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
Fixes PR11087.
llvm-svn: 142530
2011-10-19 14:11:07 +00:00
13c8360c26
Add Paste Test
...
This tests TableGen's paste functionality.
llvm-svn: 142526
2011-10-19 13:04:50 +00:00
d699161a99
Add NAME Member
...
Add a Value named "NAME" to each Record. This will be set to the def or defm
name when instantiating multiclasses. This will replace the #NAME# processing
hack once paste functionality is in place.
llvm-svn: 142518
2011-10-19 13:04:13 +00:00
deac50cba9
Generalize the reading of probability metadata to work for both branches
...
and switches, with arbitrary numbers of successors. Still optimized for
the common case of 2 successors for a conditional branch.
Add a test case for switch metadata showing up in the BlockFrequencyInfo pass.
llvm-svn: 142493
2011-10-19 10:32:19 +00:00
d27a7a947b
Teach the BranchProbabilityInfo analysis pass to read any metadata
...
encoding of probabilities. In the absense of metadata, it continues to
fall back on static heuristics.
This allows __builtin_expect, after lowering through llvm.expect
a branch instruction's metadata, to actually enter the branch
probability model. This is one component of resolving PR2577.
llvm-svn: 142492
2011-10-19 10:30:30 +00:00
343fad44ea
Add pass printing support to BlockFrequencyInfo pass. The implementation
...
layer already had support for printing the results of this analysis, but
the wiring was missing.
Now that printing the analysis works, actually bring some of this
analysis, and the BranchProbabilityInfo analysis that it wraps, under
test! I'm planning on fixing some bugs and doing other work here, so
having a nice place to add regression tests and a way to observe the
results is really useful.
llvm-svn: 142491
2011-10-19 10:12:41 +00:00
6652e22bad
Add support for the vector-widening of vselect and vector-setcc
...
llvm-svn: 142488
2011-10-19 09:45:11 +00:00
ef309c3384
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
...
llvm-svn: 142480
2011-10-19 07:48:35 +00:00
20a04e74e3
Added testcase for <rdar://problem/10215997>
...
llvm-svn: 142462
2011-10-18 23:50:52 +00:00
0d3393356b
Add additional element-promotion tests.
...
llvm-svn: 142442
2011-10-18 23:05:33 +00:00
75c2229f41
Fix a bug in the legalization of vector anyext-load and trunc-store. Mem Index starts with zero.
...
llvm-svn: 142434
2011-10-18 22:32:43 +00:00
43f1d206b9
Tidy up formatting.
...
llvm-svn: 142422
2011-10-18 21:09:01 +00:00
1f63e04b2c
Tidy up formatting.
...
llvm-svn: 142421
2011-10-18 21:08:16 +00:00
4e5c764b65
Enable more encoded immediate tests.
...
llvm-svn: 142415
2011-10-18 20:20:51 +00:00
89f9e1dca4
More vmov lane testcases.
...
llvm-svn: 142414
2011-10-18 20:19:48 +00:00
e9f204c197
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142413
2011-10-18 20:14:56 +00:00
712f3670fd
ARM vmov assembly parsing for the lane index operand.
...
llvm-svn: 142412
2011-10-18 20:10:47 +00:00
bfa067862c
llvm-objdump: Add static symbol table dumping.
...
llvm-svn: 142404
2011-10-18 19:32:17 +00:00
611450071c
ARM vmla/vmls assembly parsing for the lane index operand.
...
llvm-svn: 142389
2011-10-18 18:27:07 +00:00
40ec1da2ab
Another failing encoding.
...
llvm-svn: 142388
2011-10-18 18:23:03 +00:00
32b83a4e16
Fix NEON mul encoding tests. Wrong file contents previously.
...
llvm-svn: 142387
2011-10-18 18:14:55 +00:00
c8eff0327a
ARM vqdmulh assembly parsing for the lane index operand.
...
llvm-svn: 142386
2011-10-18 18:12:09 +00:00
d1bc6da657
Remove duplicate test.
...
llvm-svn: 142383
2011-10-18 18:05:50 +00:00
b3ecff77cd
Tidy up formatting.
...
llvm-svn: 142382
2011-10-18 18:05:16 +00:00
e6fbca3a61
ARM vmul assembly parsing for the lane index operand.
...
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
f416cb16c0
Tidy up.
...
llvm-svn: 142380
2011-10-18 18:01:09 +00:00
c91064551a
Add a few more testcases.
...
llvm-svn: 142379
2011-10-18 17:57:31 +00:00
2a498c1107
Add several FIXME cases for ARM encodings.
...
llvm-svn: 142377
2011-10-18 17:50:22 +00:00
9258b76d8d
Fix incorrect check for sign-extended constant BUILD_VECTOR.
...
<rdar://problem/10298332>
llvm-svn: 142371
2011-10-18 17:34:51 +00:00
681561901d
Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.
...
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization. For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.
llvm-svn: 142370
2011-10-18 17:34:47 +00:00
8206790ab0
Tests for 142365.
...
llvm-svn: 142368
2011-10-18 17:23:34 +00:00
95135982cd
Tidy up formatting.
...
llvm-svn: 142367
2011-10-18 17:22:53 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
...
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
1fb5bb126e
PTX: Fix disabling of MAD instruction selection
...
llvm-svn: 142352
2011-10-18 13:39:20 +00:00
0ffe593a16
Add support for dynamic stack realignment when in thumb1 mode.
...
rdar://10288916
llvm-svn: 142337
2011-10-18 05:28:00 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
...
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
81c80ddb0c
Revert "llvm-objdump: Add static symbol table dumping."
...
This reverts commit 0c30d4e4f5f9110c5a67bd0ca84444dc58697596.
llvm-svn: 142320
2011-10-18 00:17:04 +00:00
6b22ef8af2
llvm-objdump: Add static symbol table dumping.
...
llvm-svn: 142319
2011-10-17 23:55:22 +00:00
26bfc9e5da
Enable a few more NEON immediate tests.
...
llvm-svn: 142313
2011-10-17 23:50:19 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
...
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
40f8f2ff24
Add support for a new extension to the .file directive:
...
.file filenumber "directory" "filename"
This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.
llvm-svn: 142300
2011-10-17 23:05:28 +00:00
a7107f992e
Teach the ARC optimizer about the !clang.arc.copy_on_escape metadata
...
tag on objc_retainBlock calls, which indicates that they may be
optimized away. rdar://10211286.
llvm-svn: 142298
2011-10-17 22:53:25 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
...
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
e7594abd87
Fixed quoting on default data layout option.
...
llvm-svn: 142286
2011-10-17 21:54:43 +00:00
c68c8cb8d4
Add support for the Objective-C personality function to the instruction
...
combining of the landingpad instruction. The ObjC personality function acts
almost identically to the C++ personality function. In particular, it uses
"null" as a "catch-all" value.
llvm-svn: 142256
2011-10-17 21:20:24 +00:00
d2c72d6d03
Add CHECKs and document PR11158.
...
llvm-svn: 142240
2011-10-17 20:23:23 +00:00
28e4f67f26
stabalize tests by specifying the exact sse level
...
llvm-svn: 142229
2011-10-17 19:45:38 +00:00
1736c14b85
Suppress partial retain+release elimination when there's a
...
possibility that it will span multiple CFG diamonds/triangles which
could have different controlling predicates. rdar://10282956
llvm-svn: 142222
2011-10-17 18:48:25 +00:00
63a4ea1859
Correct over-zealous removal of hack.
...
Some code want to check that *any* call within a function has the 'returns
twice' attribute, not just that the current function has one.
llvm-svn: 142221
2011-10-17 18:43:40 +00:00
42cf65fe51
Temporarily XFAIL waiting for a fix.
...
llvm-svn: 142215
2011-10-17 18:25:32 +00:00
4e25c02487
llvm-objdump: Add -s, which prints the contents of each section.
...
llvm-svn: 142199
2011-10-17 17:13:22 +00:00
b4f19a5d86
llvm-objdump: Add tests.
...
llvm-svn: 142198
2011-10-17 17:13:05 +00:00
9dda3e0d13
use FileCheck and not grep in new tests
...
llvm-svn: 142189
2011-10-17 16:01:41 +00:00
83d1a93cf4
Clean the triple, add check lines.
...
llvm-svn: 142183
2011-10-17 07:07:51 +00:00
89c282e96f
Previously v2i32 vectors were legalized to v4i32. Now, they are legalized to
...
v2i64. These tests do not check MMX nor zmoving into them.
llvm-svn: 142182
2011-10-17 06:59:01 +00:00
7ccb391d21
Test case for CanLowerReturn fix (r141981)
...
llvm-svn: 142172
2011-10-17 04:03:59 +00:00
ad677b64db
Add PPC 440 scheduler and some associated tests (new files)
...
llvm-svn: 142171
2011-10-17 04:03:55 +00:00
3e8aa65bc2
Add a routine to swap branch instruction operands, and update any
...
profile metadata at the same time. Use it to preserve metadata attached
to a branch when re-writing it in InstCombine.
Add metadata to the canonicalize_branch InstCombine test, and check that
it is tranformed correctly.
Reviewed by Nick Lewycky!
llvm-svn: 142168
2011-10-17 01:11:57 +00:00
053a7358d6
Add tripple and stabalize a few more tests.
...
llvm-svn: 142158
2011-10-16 21:20:54 +00:00
a6b6566db6
Add triple to tests.
...
llvm-svn: 142154
2011-10-16 20:53:20 +00:00
9513104d2a
fix a typo in the test
...
llvm-svn: 142153
2011-10-16 20:43:41 +00:00
486ff59a9f
Enable element promotion type legalization by deafault.
...
Changed tests which assumed that vectors are legalized by widening them.
llvm-svn: 142152
2011-10-16 20:31:33 +00:00
84baea77ea
Oops! Fix testcase.
...
llvm-svn: 142151
2011-10-16 20:20:15 +00:00
0a7e9ccf04
When looking for dependencies on the src pointer, scan the src pointer. Scanning
...
on the memcpy call will pull up other unrelated stuff. Fixes PR11142.
llvm-svn: 142150
2011-10-16 20:13:32 +00:00
2130a07687
Remove the the test which checks the saving of a vector of booleans into memory.
...
The decision was to pack the bits. Currently no codegen supports this.
Currently, all of the bits in the vector are saved into the same address
in memory.
llvm-svn: 142149
2011-10-16 19:06:06 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
bc25b6eb67
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
...
no pattern.
llvm-svn: 142130
2011-10-16 10:02:06 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
...
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
a3a0681083
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
...
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
4f539312df
test/Makefile: Inspect $(PROJ_OBJ_ROOT)/tools/clang/Makefile instead of $(PROJ_SRC_ROOT)/tools/clang for "check-all".
...
llvm-svn: 142100
2011-10-16 02:54:14 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
3a46b375e2
Let this test pass even if 'int' is somewhere in its directory path.
...
On my machine, grep matched:
; ModuleID = '/Volumes/MacintoshHD2/src/chrome-git/src/third_party/llvm/test/Linker/2011-08-18-unique-debug-type.ll'
!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
Explicitly filter out the ModuleID line.
llvm-svn: 142077
2011-10-15 18:07:16 +00:00
fd4ca0f4ac
Fix SCEVExpander assert during LSR: "argument of incompatible type".
...
Just because we're dealing with a GEP doesn't mean we can assert the
SCEV has a pointer type. The fix is simply to ignore the SCEV pointer
type, which we really didn't need.
Fixes PR11138 webkit crash.
llvm-svn: 142058
2011-10-15 06:19:55 +00:00
74d1da5a05
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
...
llvm-svn: 142022
2011-10-14 23:58:49 +00:00
220f2643fa
Update test for disabling of code/data marker labels in ELF.
...
llvm-svn: 142003
2011-10-14 21:12:55 +00:00
3e3ed6d21b
OCaml bindings: add some missing functions and testcases.
...
The C bindings exposed some APIs that weren't covered by the OCaml bindings
llvm-svn: 141997
2011-10-14 20:38:33 +00:00
90e6edf7c4
OCaml bindings: fix infinite recursion on string_of_lltype
...
llvm-svn: 141994
2011-10-14 20:38:14 +00:00
06b6ccfe90
Update live-in lists when splitting critical edges.
...
Fixes PR10814. Patch by Jan Sjödin!
llvm-svn: 141960
2011-10-14 17:25:46 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
...
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
7fb5632e73
Add value numbers when spilling dead defs.
...
When spilling around an instruction with a dead def, remember to add a
value number for the def.
The missing value number wouldn't normally create problems since there
would be an incoming live range as well. However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.
The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.
This fixes part of PR11125.
llvm-svn: 141923
2011-10-14 00:34:31 +00:00
834bd602e6
ELF: Fix the section that relocations apply to. Add test to verify. Patch by Danil Malyshev!
...
llvm-svn: 141901
2011-10-13 22:30:10 +00:00
51862b3890
llvm-object: Add inline relocation information to disassembly.
...
llvm-svn: 141897
2011-10-13 22:17:18 +00:00
870c1a3f15
Reapply r141870, SCEV expansion of post-inc.
...
Speculatively reapply to see if this test case still crashes on
linux. I may have fixed it in my last checkin.
llvm-svn: 141895
2011-10-13 21:55:29 +00:00
41c253c35c
Revert r141870. The test case crashes on linux with data corruption. A deeper issue was exposed.
...
llvm-svn: 141873
2011-10-13 17:58:24 +00:00
e15d6e14e3
LSR: Reuse the post-inc expansion of expressions.
...
This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.
llvm-svn: 141870
2011-10-13 17:31:47 +00:00
f07d898ae1
Force CPU type on test so it doesn't accidentally emit movbe instead of bswap on Intel Atom CPUs.
...
llvm-svn: 141863
2011-10-13 14:27:54 +00:00
3815de8d50
Mark 'branch indirect' instruction as an indirect branch.
...
Not having it confused assembly printing of jumptables.
llvm-svn: 141862
2011-10-13 11:40:03 +00:00
25f6d3e321
More closely follow libgcc, which has code after the `ret' instruction to
...
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.
llvm-svn: 141859
2011-10-13 08:24:19 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
...
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
22a690e3db
Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
...
llvm-svn: 141856
2011-10-13 07:42:32 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
068dc91de9
Also inflate register classes around inline asm.
...
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.
This fixes PR11078.
llvm-svn: 141836
2011-10-12 23:37:40 +00:00
3e5409df77
We need to verify that the machine instruction we're using as a replacement for
...
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>
llvm-svn: 141830
2011-10-12 23:03:40 +00:00
850f7b3cdc
Removed colons from some target datalayout strings in test, since they don't match the required format.
...
llvm-svn: 141825
2011-10-12 22:24:17 +00:00
e7c0c499b8
Finish supporting cpp #file/line comments in assembler for error messages. So
...
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
llvm-svn: 141814
2011-10-12 21:38:39 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
...
llvm-svn: 141811
2011-10-12 20:54:17 +00:00
84cf2b8c98
ARM encoding tests for STC.
...
llvm-svn: 141787
2011-10-12 17:36:13 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
39c31a77b8
Fix -widen-vmovs liveness issues.
...
When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
llvm-svn: 141746
2011-10-12 00:06:23 +00:00
2d3ea9b2f2
Make this test more specific. There are 3 stats that matched "machine-licm".
...
llvm-svn: 141741
2011-10-11 23:34:31 +00:00
6647b83087
Add a new wrapper node for a DILexicalBlock that encapsulates it and a
...
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.
This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.
Part of rdar://10246360
llvm-svn: 141729
2011-10-11 22:59:11 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
265328baf6
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
1a761dcfbd
Fix PR11106 by correcting a typo that has been in the code for over a year. This
...
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.
llvm-svn: 141713
2011-10-11 21:26:40 +00:00
8c799c9826
Update test for r141704.
...
llvm-svn: 141705
2011-10-11 20:18:50 +00:00
453d401a51
Add dominance check for the instruction being hoisted.
...
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
llvm-svn: 141689
2011-10-11 18:09:58 +00:00
3283793c9a
Add support for legalization of vector SHL/SRA/SRL instructions
...
llvm-svn: 141667
2011-10-11 14:36:35 +00:00
3e01bd3b60
Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
...
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.
llvm-svn: 141653
2011-10-11 06:58:11 +00:00
603cc851f8
Test case for X86 LZCNT instruction selection.
...
llvm-svn: 141652
2011-10-11 06:47:01 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
ab3a9b3baf
Add a test for PR10565.
...
llvm-svn: 141647
2011-10-11 06:10:37 +00:00
d7515ccc47
Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's
...
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.
llvm-svn: 141646
2011-10-11 06:10:30 +00:00
288ff0ec82
Test simplification that Ana Pazos noticed.
...
llvm-svn: 141644
2011-10-11 04:43:15 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
29e7b315ac
Also create a shndx even if there are no symbols. This lets us test
...
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.
llvm-svn: 141641
2011-10-11 03:54:50 +00:00
ba38717f34
test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts.
...
llvm-svn: 141640
2011-10-11 03:41:03 +00:00
f9201c572e
Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"
...
IVs.
Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.
llvm-svn: 141633
2011-10-11 02:28:51 +00:00
8782734bcc
Test cases for 64-bit load and store instructions.
...
llvm-svn: 141631
2011-10-11 01:52:31 +00:00
44c78f809b
Added a testcase for r141599, rdar://problem/10063881.
...
llvm-svn: 141628
2011-10-11 01:32:10 +00:00
9449b8b9d2
Add testcase for PR11107.
...
llvm-svn: 141607
2011-10-11 00:26:57 +00:00
478d5bc0d0
Revert r141569 and r141576.
...
llvm-svn: 141594
2011-10-10 23:18:02 +00:00
a7d697e4a6
Reapply r141365 now that PR11107 is fixed.
...
llvm-svn: 141591
2011-10-10 22:59:55 +00:00
8ec0897db6
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
...
llvm-svn: 141585
2011-10-10 22:28:47 +00:00
fcf8462583
Add support for dumping section headers to llvm-objdump. This uses the same
...
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.
llvm-svn: 141579
2011-10-10 21:21:34 +00:00
2689f95875
If loop header is also loop exiting block then it may not be safe to hoist instructions.
...
llvm-svn: 141576
2011-10-10 20:32:03 +00:00
814598563f
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
...
instruction set has no 64-bit SRA support.
llvm-svn: 141570
2011-10-10 19:31:45 +00:00
e554d5995b
Add dominance check for the instruction being hoisted.
...
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
llvm-svn: 141569
2011-10-10 19:09:20 +00:00
42c0330a79
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
...
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
b253f490c3
Insert dummy ED table entries for pseudo-instructions.
...
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
llvm-svn: 141562
2011-10-10 18:30:16 +00:00
47aac51043
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
...
hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
e7ae31cc25
XFAIL tblgen tests on leak checkers.
...
llvm-svn: 141533
2011-10-10 13:09:59 +00:00
ea662bb32f
When getting the number of bits necessary for addressing mode
...
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
llvm-svn: 141529
2011-10-10 07:24:23 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
...
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
729abd360e
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
...
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.
TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.
This fixes PR11088.
llvm-svn: 141499
2011-10-08 18:28:28 +00:00
b81dcdef7b
Add missing test case for r141410.
...
llvm-svn: 141498
2011-10-08 18:06:54 +00:00
ce0cb3a101
Unit test for LSR phi reuse in r141442.
...
llvm-svn: 141472
2011-10-08 02:34:51 +00:00
ba4a362276
llvm-objdump: Add relocation and archive support.
...
llvm-svn: 141451
2011-10-08 00:18:30 +00:00
c87d60a58c
Enable ARM mode VDUP(scalar) tests.
...
llvm-svn: 141447
2011-10-07 23:57:03 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
33f619971f
Remove Multidefs
...
Multidefs are a bit unwieldy and incomplete. Remove them in favor of
another mechanism, probably for loops.
Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"
llvm-svn: 141378
2011-10-07 18:25:05 +00:00
74db300f37
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
...
llvm-svn: 141371
2011-10-07 17:21:44 +00:00
8decdc472f
Reenable tail calls for iOS 5.0 and later.
...
llvm-svn: 141370
2011-10-07 17:17:49 +00:00
bc1589945d
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
...
llvm-svn: 141368
2011-10-07 16:59:21 +00:00
318d6bae80
Peephole optimization for ABS on ARM.
...
Patch by Ana Pazos!
llvm-svn: 141365
2011-10-07 16:15:08 +00:00
c52af46484
Teach GVN to also propagate switch cases. For example, in this code
...
switch (n) {
case 27:
do_something(x);
...
}
the call do_something(x) will be replaced with do_something(27). In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.
llvm-svn: 141360
2011-10-07 08:29:06 +00:00
d9cfddc5cd
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
...
llvm-svn: 141358
2011-10-07 07:02:24 +00:00
bf136764ae
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
...
llvm-svn: 141354
2011-10-07 05:53:50 +00:00
5aebebe18d
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
...
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
0947102623
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
...
llvm-svn: 141321
2011-10-06 22:04:05 +00:00
4887469138
Fix and clean up tests. Un-XFAIL.
...
llvm-svn: 141318
2011-10-06 21:32:50 +00:00
ceb4c7523f
Fix and clean up tests. Un-XFAIL.
...
llvm-svn: 141316
2011-10-06 21:28:30 +00:00
74842740c0
Make Test More Thorough
...
Check that all ADD patters are processed.
Add a SUB test.
llvm-svn: 141314
2011-10-06 21:20:44 +00:00
7f7f2e9b76
s/tblgen/llvm-tblgen/g in a few missed places, including the tests
...
llvm-svn: 141294
2011-10-06 13:39:59 +00:00
d43a5d76f4
ocaml bindings: add llvm_ipo based on IPO.h
...
llvm-svn: 141284
2011-10-06 12:12:27 +00:00
ba1460adb6
add more tests for the OCaml bindings
...
llvm-svn: 141283
2011-10-06 12:12:12 +00:00
23eb468b1f
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
...
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
87aa18378e
Remove a check from ARM shifted operand isel helper methods, which were blocking
...
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
llvm-svn: 141247
2011-10-05 23:38:50 +00:00
9bc27ec40f
Update Test for Multidefs
...
Update the MultiPat.td test to create some defs via multidefs.
llvm-svn: 141235
2011-10-05 22:42:48 +00:00
52a9cb8063
Add a Multidef Test
...
Add a simple test for multidefs.
llvm-svn: 141234
2011-10-05 22:42:47 +00:00
3e3aecbc2c
PR11061: Make simplifylibcalls fold strcmp("", x) correctly.
...
While I'm here, fix the related issue with strncmp, add some actual tests for strcmp and strncmp, and start using StringRef::compare for constant folding instead of using strcmp/strncmp so that the optimized IR isn't dependent on the host's implementation of strcmp.
llvm-svn: 141227
2011-10-05 22:27:16 +00:00
8f9acfac89
Revert 141203. InstCombine is looping on unit tests.
...
llvm-svn: 141209
2011-10-05 20:44:29 +00:00
79d0c4f4b0
Check for the returns_twice attribute in callsFunctionThatReturnsTwice. This
...
fixes PR11038, but there are still some cleanups to be done.
llvm-svn: 141204
2011-10-05 20:05:13 +00:00
e37e030137
Update InstCombine worklist after instruction transform is complete.
...
When updating the worklist for InstCombine, the Add/AddUsersToWorklist
functions may access the instruction(s) being added, for debug output for
example. If the instructions aren't yet added to the basic block, this
can result in a crash. Finish the instruction transformation before
adjusting the worklist instead.
rdar://10238555
llvm-svn: 141203
2011-10-05 20:05:00 +00:00
8218b8f6ae
Make this test less sensitive to codegen optimizations.
...
llvm-svn: 141195
2011-10-05 18:13:08 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
f4f47ccd12
GVN does simple propagation of conditions: when it sees a conditional
...
branch "br i1 %x, label %if_true, label %if_false" then it replaces
"%x" with "true" in places only reachable via the %if_true arm, and
with "false" in places only reachable via the %if_false arm. Except
that actually it doesn't: if value numbering shows that %y is equal
to %x then, yes, %y will be turned into true/false in this way, but
any occurrences of %x itself are not transformed. Fix this. What's
more, it's often the case that %x is an equality comparison such as
"%x = icmp eq %A, 0", in which case every occurrence of %A that is
only reachable via the %if_true arm can be replaced with 0. Implement
this and a few other variations on this theme. This reduces the number
of lines of LLVM IR in "GCC as one big file" by 0.2%. It has a bigger
impact on Ada code, typically reducing the number of lines of bitcode
by around 0.4% by removing repeated compiler generated checks. Passes
the LLVM nightly testsuite and the Ada ACATS testsuite.
llvm-svn: 141177
2011-10-05 14:28:49 +00:00
e90dd0587e
Generalize GVN's conditional propagation logic slightly:
...
it's OK for the false/true destination to have multiple
predecessors as long as the extra ones are dominated by
the branch destination.
llvm-svn: 141176
2011-10-05 14:17:01 +00:00
887a111e31
Missing test case for r141164.
...
llvm-svn: 141166
2011-10-05 06:23:32 +00:00
0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
28a0bc5562
Tidy up formatting.
...
llvm-svn: 141123
2011-10-04 21:43:51 +00:00
4879f70ab9
Un-XFAIL file. Comment out individual failing instructions.
...
llvm-svn: 141117
2011-10-04 21:16:42 +00:00
f3e1fc3f86
Tidy up formatting.
...
llvm-svn: 141115
2011-10-04 20:52:57 +00:00
8a829e8ecb
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
...
llvm-svn: 141114
2011-10-04 20:50:05 +00:00
8bc8bfdcad
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
...
llvm-svn: 141113
2011-10-04 20:46:49 +00:00
610aa62edc
Tidy up formatting.
...
llvm-svn: 141111
2011-10-04 20:42:35 +00:00
388c0f61e8
Un-XFAIL file. Fix incorrect CHECK line.
...
llvm-svn: 141110
2011-10-04 20:42:09 +00:00
2644375abe
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141108
2011-10-04 20:34:11 +00:00
979697b630
Test Operand Arguments
...
Add a test to do list manipulation and pass the result as arguments.
This tests the new list element operator resolve code and provides an
example of using list manipulation to do instruction pattern
substitution.
llvm-svn: 141102
2011-10-04 18:55:40 +00:00
83e84faa8f
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141099
2011-10-04 18:43:15 +00:00
2d9eb707af
Tidy up. Formatting.
...
llvm-svn: 141096
2011-10-04 17:49:45 +00:00
41090ed753
Fix PR9833/PR11054 (patch provided by Patrik Hägglund)
...
llvm-svn: 141092
2011-10-04 16:26:41 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
8de329a9fc
LSR should avoid redundant edge splitting.
...
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"
llvm-svn: 141059
2011-10-04 03:50:44 +00:00
bf51f97c28
Unit test for r140919, loop unroll heuristics.
...
llvm-svn: 141049
2011-10-04 00:07:02 +00:00
b85400aa58
Tidy up. These tests are covered in the .s file tests now.
...
llvm-svn: 141047
2011-10-03 23:40:13 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
6c71ef32be
Move CHECK after entry label.
...
llvm-svn: 141030
2011-10-03 21:24:30 +00:00
c3a6357ee3
Add support for 64-bit logical NOR.
...
llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
...
llvm-svn: 141028
2011-10-03 21:16:50 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
c3fc62b492
Update test for 141010.
...
llvm-svn: 141022
2011-10-03 20:58:08 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
...
llvm-svn: 141017
2011-10-03 20:01:11 +00:00
b817655b77
Tidy up a bit. Formatting.
...
llvm-svn: 141010
2011-10-03 17:59:31 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
...
llvm-svn: 141007
2011-10-03 17:28:23 +00:00
cc349c8dd8
Add the returns_twice attribute to LLVM.
...
llvm-svn: 141001
2011-10-03 14:45:37 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
...
llvm-svn: 140997
2011-10-03 08:14:29 +00:00
285bc34089
Test updates that were supposed to go with r140993.
...
llvm-svn: 140994
2011-10-03 07:53:59 +00:00
3155552461
Reapply r140979 with fix! We never did get a testcase, but careful review of the
...
logic by David Meyer revealed this bug.
llvm-svn: 140992
2011-10-03 07:10:45 +00:00
0038e0632c
attempt to fix ocaml bindings: landing pads
...
llvm-svn: 140991
2011-10-03 06:41:46 +00:00
b1dbce1406
Revert r140979 due to reports of bootstrap failure.
...
llvm-svn: 140980
2011-10-03 05:14:59 +00:00
3c624b8d0d
Add one more case we compute a max trip count.
...
llvm-svn: 140979
2011-10-03 01:03:57 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
...
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
...
llvm-svn: 140971
2011-10-02 16:56:09 +00:00
99fb091f65
Add a new icmp+select optz'n. Also shows off the load(cst) folding added in
...
r140966.
llvm-svn: 140969
2011-10-02 10:37:37 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
b34639de75
Filecheck-ize.
...
llvm-svn: 140904
2011-09-30 23:40:29 +00:00
24b6b8d16a
Add new line at end of file.
...
llvm-svn: 140903
2011-09-30 23:21:11 +00:00
9925f197cc
When inferring the pointer alignment, if the global doesn't have an initializer
...
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.
For instance, in file A.c:
struct S s;
In file B.c:
struct {
// something long
};
extern S s;
void foo() {
struct S p = s;
// ...
}
this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.
llvm-svn: 140902
2011-09-30 23:19:55 +00:00
dc221dd649
Test More Complicated Lists
...
Test of indexing lists of lists of lists works. This also exercises
some operators.
llvm-svn: 140884
2011-09-30 20:59:52 +00:00
0c3a2b48e7
Test VarListElementInit:: resolveListElementReference
...
Add a TableGen test to check if indexing lists of lists works.
llvm-svn: 140883
2011-09-30 20:59:51 +00:00
1fef284cf9
Remove unnecessary checking of register operands.
...
llvm-svn: 140872
2011-09-30 19:18:24 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
24ff834671
float comparison to double 'zero' constant can just be a float 'zero.'
...
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.
We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
%conv = fpext float %x to double
%cmp = fcmp olt double %conv, 0.000000e+00
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
Into:
define float @bar(float %x) nounwind readnone optsize ssp {
%cmp = fcmp olt float %x, 0.000000e+00 ; <---- This
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
rdar://10215914
llvm-svn: 140869
2011-09-30 18:45:50 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
b381129095
Check values of immediate operands.
...
llvm-svn: 140860
2011-09-30 17:19:21 +00:00
d6c0011d92
Add forgotten tests that the cleanup flag is cleared if there
...
is a catch-all landingpad clause.
llvm-svn: 140858
2011-09-30 17:00:34 +00:00
5c05579f94
Inlining often produces landingpad instructions with repeated
...
catch or repeated filter clauses. Teach instcombine a bunch
of tricks for simplifying landingpad clauses. Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function. Probably
someone should add the ObjC++ personality function. I didn't as
I don't know anything about it.
llvm-svn: 140852
2011-09-30 13:12:16 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
4ac148dcbc
When eliminating unnecessary retain+autorelease on return values,
...
handle the case where the retain is in a different basic block.
rdar://10210274.
llvm-svn: 140815
2011-09-29 22:27:34 +00:00
2053a5dd64
Don't eliminate objc_retainBlock calls on stack objects if the
...
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.
llvm-svn: 140814
2011-09-29 22:25:23 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
bc6de90a5f
LSR: rewrite inner loops only.
...
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
llvm-svn: 140762
2011-09-29 01:33:38 +00:00
37470d5bde
whitespace
...
llvm-svn: 140761
2011-09-29 01:31:48 +00:00
fd47d8af8b
PTX: Add new patterns for bitconvert and any_extend
...
llvm-svn: 140753
2011-09-29 01:13:12 +00:00
8156376aa9
Tighten a ARM dag combine condition to avoid an identity transformation, which
...
ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
2fb357a5b0
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
...
llvm-svn: 140723
2011-09-28 21:00:25 +00:00
5e18b14ee2
PTX: MC-ize the PTX back-end (patch 1 of N)
...
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
llvm-svn: 140697
2011-09-28 14:32:04 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
8c219ecd1a
Test case for r140670: indvars should hoist sext.
...
llvm-svn: 140671
2011-09-28 02:13:32 +00:00
5f476dc3ef
PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.
...
llvm-svn: 140666
2011-09-28 00:34:27 +00:00
30c811246f
Remove X86-dependent stuff from SSEDomainFix.
...
This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
llvm-svn: 140659
2011-09-27 23:50:46 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
6a2eb5c1c8
test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.
...
llvm-svn: 140641
2011-09-27 21:54:50 +00:00
547b6c5ecd
Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.
...
If someone prefers %tmp42 to %42, run instnamer.
llvm-svn: 140634
2011-09-27 20:39:19 +00:00
2bc774ac1a
Add binary archive support to llvm-nm.
...
llvm-svn: 140627
2011-09-27 19:37:18 +00:00
554a012eb5
Unbreak tests.
...
llvm-svn: 140622
2011-09-27 19:06:37 +00:00
9f01f89386
PTX: Add support for sitofp in backend
...
llvm-svn: 140593
2011-09-27 01:04:47 +00:00
90f90da156
Split the landing pad basic block with the correct function. Also merge the
...
split landingpad instructions into a PHI node.
PR11016
llvm-svn: 140592
2011-09-27 00:59:31 +00:00
f6fbfd3f83
Last batch of test conversions to new atomic instructions.
...
llvm-svn: 140585
2011-09-27 00:17:29 +00:00
a486cb972f
Convert a bunch more tests over to the new atomic instructions.
...
llvm-svn: 140582
2011-09-26 23:15:09 +00:00
287d6ef088
Fix an incorrect decoder test.
...
llvm-svn: 140579
2011-09-26 23:08:34 +00:00
d20cd25c69
Remove incorrect testcases.
...
llvm-svn: 140572
2011-09-26 22:13:55 +00:00
ab7b99ab9c
Convert more tests to new atomic instructions.
...
llvm-svn: 140567
2011-09-26 21:36:10 +00:00
6fb0c1e474
Convert more tests over to the new atomic instructions.
...
I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.
The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.
llvm-svn: 140566
2011-09-26 21:30:17 +00:00
c064f2c33e
Convert more tests over to the new atomic instructions.
...
llvm-svn: 140559
2011-09-26 20:27:49 +00:00
bda9e7af58
Upgrade a couple more tests to the new atomic instructions.
...
llvm-svn: 140558
2011-09-26 20:15:56 +00:00
5c91891cf3
Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions.
...
llvm-svn: 140557
2011-09-26 20:15:28 +00:00
67d33b3bf2
Fix this test so it doesn't fail on Mac.
...
llvm-svn: 140553
2011-09-26 19:13:47 +00:00
1395cf8423
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
...
printing of local offsets
llvm-svn: 140547
2011-09-26 18:57:22 +00:00
0ceb8cadd2
Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.
...
llvm-svn: 140539
2011-09-26 17:40:42 +00:00
55f340eb62
PTX: Add .align tests to stack object test file
...
llvm-svn: 140537
2011-09-26 16:20:38 +00:00
14defde057
PTX: Fix some lingering issues with stack allocation
...
llvm-svn: 140535
2011-09-26 16:20:34 +00:00
d40f5ababf
PTX: Unify handling of loads/stores
...
llvm-svn: 140533
2011-09-26 16:20:28 +00:00
1748b37acd
Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported
...
llvm-svn: 140517
2011-09-26 06:44:27 +00:00
b1fbf9ff26
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
...
llvm-svn: 140516
2011-09-26 06:13:20 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
...
llvm-svn: 140515
2011-09-26 05:12:43 +00:00
55cf2ed148
Only run MF.verify() with EXPENSIVE_CHECKS=1.
...
llvm-svn: 140441
2011-09-24 01:11:19 +00:00
3bb99bc957
Verify that terminators follow non-terminators.
...
This exposes a -segmented-stacks bug.
llvm-svn: 140429
2011-09-23 22:45:39 +00:00
8a15a5aa93
PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.
...
llvm-svn: 140428
2011-09-23 22:41:57 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
2056d15bd9
Also match negative offsets for addrmode3 and addrmode5.
...
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
b75772201f
Fix incorrect disassembly test.
...
llvm-svn: 140423
2011-09-23 22:05:54 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
37f35f0083
PTX: Handle function call return values
...
llvm-svn: 140386
2011-09-23 16:48:41 +00:00
6c23d2ee55
PTX: Start fixing function calls
...
llvm-svn: 140378
2011-09-23 14:31:12 +00:00
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
...
llvm-svn: 140370
2011-09-23 06:57:25 +00:00
64a4bf1788
PR10989: Don't print .hidden on Windows.
...
llvm-svn: 140356
2011-09-23 00:13:02 +00:00
87c844cdf8
PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)
...
llvm-svn: 140355
2011-09-22 23:41:28 +00:00
e83e1b2d2c
Fix SimplifySelectCC to add newly created nodes to the DAGCombiner
...
worklist, as it may be possible to perform further optimization on them.
llvm-svn: 140349
2011-09-22 23:01:29 +00:00
0e4fcb8e3b
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
...
floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
llvm-svn: 140332
2011-09-22 20:15:48 +00:00
f9b785f185
PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl.
...
llvm-svn: 140327
2011-09-22 18:56:30 +00:00
5862332f59
PTX: fixup test cases for register changes
...
llvm-svn: 140311
2011-09-22 16:45:51 +00:00
6d1872b77a
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
...
llvm-svn: 140299
2011-09-22 07:01:50 +00:00
fbe52c0192
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
...
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
5e6b65cf0d
Do not unnecessarily use AT_specification DIE because it does not add any value.
...
Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.
llvm-svn: 140282
2011-09-21 23:41:11 +00:00
4ce4a61cac
Remove +.
...
llvm-svn: 140266
2011-09-21 17:43:48 +00:00
24b6588743
Re-enable some of the disabled tests. Use FileCheck instead of grep to check
...
output.
llvm-svn: 140263
2011-09-21 17:36:30 +00:00
253a7391ee
add another testcase for pr10902
...
llvm-svn: 140257
2011-09-21 17:13:40 +00:00
bc9ba30158
[VECTOR-SELECT] Address one of the bugs in pr10902.
...
Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.
llvm-svn: 140249
2011-09-21 14:34:38 +00:00
155137bd10
Remove llvm-gcc and various compiler handling from llvm. It's not needed
...
here anymore and has been migrated to the test-suite project.
llvm-svn: 140216
2011-09-20 23:58:15 +00:00
36faa4d49c
This test is completely invalid with the modern EH model. Delete.
...
llvm-svn: 140213
2011-09-20 23:52:09 +00:00
1815b688cc
Make sure IPSCCP never marks a tracked call as overdefined in SCCPSolver::ResolvedUndefsIn. If we do, we can end up in a situation where a function is resolved to return a constant, but the caller is marked overdefined, which confuses the code later.
...
<rdar://problem/9956541> (again).
llvm-svn: 140210
2011-09-20 23:28:51 +00:00
6cb23f6e7f
Add a DAGCombine for subvector extracts to remove useless chains of
...
subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.
llvm-svn: 140204
2011-09-20 23:19:33 +00:00
8058234b32
Revert r140097, working on a better approach
...
llvm-svn: 140203
2011-09-20 23:19:29 +00:00
cf1372d183
Update this test to the new EH model.
...
Though I think it may be obsolete with the loop extract changes. And I couldn't
get the old version of LLVM to compile so that I could reduce this testcase.
llvm-svn: 140197
2011-09-20 22:29:43 +00:00
33e91a6cf7
The wrong relocation was being emitted for several SSSE3 instructions.
...
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
llvm-svn: 140184
2011-09-20 21:39:21 +00:00
61a003315e
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
...
llvm-svn: 140181
2011-09-20 21:38:18 +00:00
626a6f4160
Update to new EH model.
...
llvm-svn: 140177
2011-09-20 20:21:16 +00:00
2b35d7cff1
Port over more Thumb2 encoding tests to decoding tests.
...
llvm-svn: 140152
2011-09-20 17:44:48 +00:00
011be52871
test/CodeGen/X86/avx-minmax.ll: Unbreak Win32.
...
On Windows x64, 128-bit arguments are not passed by reg but by indirect. eg.
maxpd:
vmovapd (%rcx), %xmm0
vmaxpd (%rdx), %xmm0, %xmm0
FIXME: I don't care YMM on x64 for now.
llvm-svn: 140143
2011-09-20 14:11:35 +00:00
68c92d86da
Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.
...
llvm-svn: 140140
2011-09-20 07:38:59 +00:00
8586e62d91
ARM isel bug fix for adds/subs operands.
...
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
a316da1466
Nuke obsolete test file.
...
llvm-svn: 140127
2011-09-20 01:03:51 +00:00
c70d9dfaea
Thumb2 assembly parsing and encoding for WFE/WFI/YIELD.
...
llvm-svn: 140126
2011-09-20 00:48:56 +00:00
b35198021a
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
...
llvm-svn: 140125
2011-09-20 00:46:54 +00:00
5aaeb91ca6
Thumb2 assembly parsing and encoding for USUB8/USUB16.
...
llvm-svn: 140120
2011-09-20 00:31:57 +00:00
716f17399e
Thumb2 assembly parsing and encoding for USAX.
...
llvm-svn: 140119
2011-09-20 00:30:45 +00:00
42f7b647fa
Thumb2 assembly parsing and encoding for USAT16.
...
llvm-svn: 140118
2011-09-20 00:28:25 +00:00
e0493ade65
Thumb2 assembly parsing and encoding for USAT.
...
llvm-svn: 140117
2011-09-20 00:27:36 +00:00
e65c2ab453
Tidy up.
...
llvm-svn: 140114
2011-09-20 00:24:37 +00:00
db6d378f80
Thumb2 assembly parsing and encoding for UQSAD8/USADA8.
...
llvm-svn: 140113
2011-09-20 00:23:51 +00:00
6286f75161
Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8.
...
llvm-svn: 140112
2011-09-20 00:20:44 +00:00
62f8eee0eb
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
...
llvm-svn: 140111
2011-09-20 00:18:52 +00:00
4b0e7d9457
Thumb2 assembly parsing and encoding for UQADD16/UQADD8.
...
llvm-svn: 140110
2011-09-20 00:15:03 +00:00
0828ab04bf
Attempt to fix -mtriple=i686-{cygwin|mingw|win32} regressions. Nakamura,
...
if this doesn't work, please provide more details.
llvm-svn: 140107
2011-09-20 00:08:12 +00:00
708d38e06a
Update to the new EH syntax.
...
llvm-svn: 140103
2011-09-19 23:50:34 +00:00
ff5d9cc389
Dramatically reduce this testcase.
...
llvm-svn: 140101
2011-09-19 23:47:06 +00:00
c4398d2c7b
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
...
llvm-svn: 140098
2011-09-19 23:36:59 +00:00
51792dcc4d
Based on the small opt Zvi's patch was trying to achieve, eliminate
...
128-bit undef subvector insertion into a 256-bit vector
llvm-svn: 140097
2011-09-19 23:36:50 +00:00
788a8cd4e6
Tidy up a bit.
...
llvm-svn: 140096
2011-09-19 23:34:18 +00:00
fc5451832a
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
...
llvm-svn: 140095
2011-09-19 23:31:02 +00:00
7cdaa3a1a8
Revert r140083 and r140084 until buildbots can be fixed.
...
llvm-svn: 140094
2011-09-19 23:30:41 +00:00
4b0ae48614
Remove llvmc and assorted build machinery for it.
...
The problems that llvmc solved have largely been subsumed with the
tasks that the clang driver can accomplish, but llvmc lacks flexibility
and depends too heavily on the EOL'd llvm-gcc.
llvm-svn: 140093
2011-09-19 23:22:41 +00:00
1ab5e56324
Thumb2 assembly parsing and encoding for UHSUB16/UHSUB8.
...
llvm-svn: 140089
2011-09-19 23:15:36 +00:00
15d97fd89b
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
...
llvm-svn: 140088
2011-09-19 23:13:25 +00:00
3a64050470
Thumb2 assembly parsing and encoding for UHADD16/UHADD8.
...
llvm-svn: 140087
2011-09-19 23:08:24 +00:00
dd00b9f452
Thumb2 assembly parsing and encoding for UBFX.
...
llvm-svn: 140086
2011-09-19 23:06:38 +00:00
a6e6504e2a
Thumb2 assembly parsing and encoding for UASX.
...
llvm-svn: 140085
2011-09-19 23:05:22 +00:00
d01aee587f
Update test to remove the 'unwind' instruction.
...
llvm-svn: 140084
2011-09-19 23:01:11 +00:00
f5028fd141
Fix copy/past-o. Gotta remember that 'modify' step...
...
llvm-svn: 140082
2011-09-19 22:53:00 +00:00
c704263440
Thumb2 assembly parsing and encoding for UADD16/UADD8.
...
llvm-svn: 140081
2011-09-19 22:52:27 +00:00
c74e2c3b07
Thumb2 assembly parsing and encoding for TST.
...
llvm-svn: 140080
2011-09-19 22:46:06 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
...
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
8bf0eab34d
Replace uses of unwind with unreachable for the same effect.
...
llvm-svn: 140077
2011-09-19 22:16:15 +00:00
e7b02b8170
Replace more uses of 'unwind' in the tests with calls to landingpad and
...
resume. Note that some of these tests were basically dead.
llvm-svn: 140076
2011-09-19 22:11:35 +00:00
eb1bd24134
Some additional tests for Thumb atomic load and store (which I somehow forgot to commit earlier).
...
llvm-svn: 140074
2011-09-19 22:02:33 +00:00
61d7c8a065
Fix an infinite loop where a transform in InstCombiner::visitAnd claims a construct is changed when it is not. (See included testcase.)
...
Patch by Xiaoyi Guo.
llvm-svn: 140072
2011-09-19 21:58:15 +00:00
52faf4bff9
Thumb2 assembly parsing and encoding for TEQ.
...
llvm-svn: 140070
2011-09-19 21:41:21 +00:00
d4a3d452d4
Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
...
PR10955 and PR10948.
llvm-svn: 140069
2011-09-19 21:29:24 +00:00
c945f54ea5
This testcase is dead. It doesn't inline even if I add the 'alwaysinline'
...
attribute to the @foo function.
llvm-svn: 140067
2011-09-19 21:14:33 +00:00
ee9ff79319
Remove FIXME. TBB/TBH are Thumb mode only instructions.
...
llvm-svn: 140048
2011-09-19 20:30:29 +00:00
8221319707
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
...
llvm-svn: 140047
2011-09-19 20:29:33 +00:00
222b5a4f5a
Fix a typo in the bitcode reader in the handling of atomic stores. Reported by David Meyer on llvmdev.
...
llvm-svn: 140040
2011-09-19 19:41:28 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
...
llvm-svn: 140032
2011-09-19 18:07:10 +00:00
264abdecf0
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
...
llvm-svn: 140029
2011-09-19 17:56:37 +00:00
7251e41b16
[indvars] Fix PR10946: SCEV cannot handle Vector IVs.
...
llvm-svn: 140026
2011-09-19 17:54:39 +00:00
ec7c23eed3
Thumb2 assembly parsing and encoding for SVC.
...
llvm-svn: 140025
2011-09-19 17:40:35 +00:00
aa4c0d3986
Thumb2 assembly parsing and encoding for SUB(register).
...
llvm-svn: 140024
2011-09-19 17:37:48 +00:00
12746ea313
Added regression test for bug #10869 .
...
llvm-svn: 140012
2011-09-19 07:48:08 +00:00
261a10a007
setOperationAction should be done on the return value of the type, not the operands.
...
llvm-svn: 140001
2011-09-18 14:57:03 +00:00
7ae11279e9
When promoting integer vectors we often create ext-loads. This patch adds a
...
dag-combine optimization to implement the ext-load efficiently (using shuffles).
For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.
llvm-svn: 139995
2011-09-18 10:39:32 +00:00
98e5736295
Apply Duncan's test fix from r139986 to the avx version of that test too.
...
llvm-svn: 139992
2011-09-18 00:41:38 +00:00
f2b8c854dd
Synthesize x86 max/min instructions also for vectors (i.e. produce
...
maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
llvm-svn: 139986
2011-09-17 16:49:39 +00:00
09a9b6b953
Add a testcase for another corner-case decoding.
...
llvm-svn: 139970
2011-09-16 23:15:29 +00:00
d0c435c23c
Thumb2 assembly parsing and encoding for SUB(immediate).
...
llvm-svn: 139966
2011-09-16 22:58:42 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
...
llvm-svn: 139964
2011-09-16 22:29:48 +00:00
45715a7b9d
Thumb2 assembly parsing and encoding for STRT.
...
llvm-svn: 139963
2011-09-16 22:27:12 +00:00
0876856aa0
Thumb2 assembly parsing and encoding for LDRHT/STRHT.
...
llvm-svn: 139962
2011-09-16 22:26:01 +00:00
5c06de5bb9
Thumb2 assembly parsing and encoding for STREX/STREXB/STREXH/STREXD.
...
llvm-svn: 139961
2011-09-16 22:22:07 +00:00
bb24913d7b
Thumb2 assembly parsing and encoding for STRD.
...
llvm-svn: 139960
2011-09-16 22:19:38 +00:00
dfb9c30319
Simplify comment. There's no Thumb LDRD(register) encoding. That's ARM only.
...
llvm-svn: 139959
2011-09-16 22:18:42 +00:00
9764bced10
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
...
llvm-svn: 139958
2011-09-16 22:17:02 +00:00
c0f032a570
Thumb2 assembly parsing and encoding for STRBT.
...
llvm-svn: 139957
2011-09-16 22:15:51 +00:00
a46765300d
Thumb2 assembly parsing and encoding for STRH.
...
llvm-svn: 139956
2011-09-16 22:12:19 +00:00
d372cb7312
Remove test of undocumented format.
...
llvm-svn: 139955
2011-09-16 22:09:58 +00:00
85348bd8cd
Thumb2 assembly parsing and encoding for STRB.
...
llvm-svn: 139954
2011-09-16 22:09:19 +00:00
b0c04e7335
Shuffle a few more thumb2 tests to match the comment headings.
...
llvm-svn: 139952
2011-09-16 22:01:18 +00:00
21a073e4d3
Thumb2 tests for STR(literal), STR(register) and STR pre/post indexed immediate.
...
llvm-svn: 139951
2011-09-16 21:59:13 +00:00
42042e405a
Shuffle a few tests around.
...
llvm-svn: 139950
2011-09-16 21:57:10 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
...
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
92606beeae
Thumb2 assembly parsing and encoding for STR(immediate).
...
Add aliases for STRB/STRH while there. Tests forthcoming for those.
llvm-svn: 139942
2011-09-16 21:06:12 +00:00
bb9825ffe3
Thumb2 assembly parsing and encoding for STMDB.
...
llvm-svn: 139940
2011-09-16 20:58:38 +00:00
099c9767c3
Thumb2 assembly parsing and encoding for STMIA.
...
llvm-svn: 139938
2011-09-16 20:50:13 +00:00
4646a740ab
Thumb2 assembly parsing and encoding for SSUB16/SSUB8.
...
llvm-svn: 139931
2011-09-16 18:52:36 +00:00
8aee874bf1
Thumb2 assembly parsing and encoding for SSAX.
...
llvm-svn: 139929
2011-09-16 18:37:10 +00:00
2a2d50b7ad
Thumb2 assembly parsing and encoding for SSAT16.
...
llvm-svn: 139927
2011-09-16 18:33:22 +00:00
9d9c99ff07
Thumb2 assembly parsing and encoding for SSAT.
...
llvm-svn: 139926
2011-09-16 18:32:30 +00:00
e6e7cd146a
Thumb2 assembly parsing and encoding for SRS.
...
llvm-svn: 139925
2011-09-16 18:25:22 +00:00
5d1d50b8f7
Thumb2 assembly parsing and encoding for SMMUSD/SMUSDX.
...
llvm-svn: 139923
2011-09-16 18:08:48 +00:00
0f90d9e161
Thumb2 assembly parsing and encoding for SMMULWB/SMULWT.
...
llvm-svn: 139922
2011-09-16 18:07:18 +00:00
d73c6458de
Thumb2 assembly parsing and encoding for SMMULL.
...
llvm-svn: 139921
2011-09-16 18:05:48 +00:00
4eea5d6284
Fix comment.
...
llvm-svn: 139919
2011-09-16 18:03:00 +00:00
8e968d996b
Thumb2 assembly parsing and encoding for SMULBB/SMULBT/SMULTB/SMULTT.
...
llvm-svn: 139918
2011-09-16 18:02:36 +00:00
8124284140
Thumb2 assembly parsing and encoding for SMMUAD'dib.
...
llvm-svn: 139917
2011-09-16 17:58:21 +00:00
601597f329
Thumb2 assembly parsing and encoding for SMMUL/SMMULR.
...
llvm-svn: 139916
2011-09-16 17:56:06 +00:00
30fc19a6dd
Port over more Thumb2 assembly tests to disassembly tests.
...
llvm-svn: 139915
2011-09-16 17:56:04 +00:00
b489e3b408
Port over more Thumb2 assembly tests to disassembly tests.
...
llvm-svn: 139912
2011-09-16 17:22:48 +00:00
1adc9c103c
Thumb2 assembly parsing and encoding for SMMLS/SMMLSR.
...
llvm-svn: 139911
2011-09-16 17:16:55 +00:00
ffec9d7bd5
Thumb2 assembly parsing and encoding for SMMLA/SMMLAR.
...
llvm-svn: 139910
2011-09-16 17:15:18 +00:00
c1826a9de0
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
...
llvm-svn: 139909
2011-09-16 17:10:44 +00:00
92738fe1b4
Thumb2 assembly parsing and encoding for SMLSD/SMLSDX.
...
llvm-svn: 139908
2011-09-16 17:08:45 +00:00
53bc90d190
Thumb2 assembly parsing and encoding for SMLAWB/SMLAWT.
...
llvm-svn: 139907
2011-09-16 17:03:01 +00:00
7a0b90b187
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
...
llvm-svn: 139906
2011-09-16 16:58:03 +00:00
e0891d6915
Thumb2 assembly parsing and encoding for SMLALBB/SMLALBT/SMLALTB/SMLALTT.
...
llvm-svn: 139905
2011-09-16 16:53:25 +00:00
f9799d2c2d
Thumb2 assembly parsing and encoding for SMLAL.
...
llvm-svn: 139902
2011-09-16 16:38:00 +00:00
31004375fc
Test case trial and error. Not sure the proper way to check MBB names.
...
llvm-svn: 139900
2011-09-16 03:57:19 +00:00
b57d9c38a2
Reduced a stronger test case for coalescer bug PR10920.
...
llvm-svn: 139898
2011-09-16 03:46:49 +00:00
b1feced676
Thumb2 assembly parsing and encoding for SMLAD/SMLADX.
...
llvm-svn: 139884
2011-09-16 00:09:37 +00:00
5798cfddd7
Thumb2 assembly parsing and encoding for SMLABB/SMLABT/SMLATB/SMLATT.
...
llvm-svn: 139881
2011-09-16 00:00:23 +00:00
6568ab142e
Thumb2 assembly parsing and encoding for SHSUB16/SHSUB8.
...
llvm-svn: 139880
2011-09-15 23:58:56 +00:00
c38642b3e1
Thumb2 assembly parsing and encoding for SHADD16/SHADD8.
...
llvm-svn: 139871
2011-09-15 22:36:10 +00:00
b08ce9b4c4
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
...
llvm-svn: 139870
2011-09-15 22:34:29 +00:00
e2481db60f
Thumb2 assembly parsing and encoding for SEV.W.
...
llvm-svn: 139866
2011-09-15 22:24:20 +00:00
9086a1ed4e
Thumb2 assembly parsing and encoding for SEL.
...
llvm-svn: 139861
2011-09-15 22:01:09 +00:00
0be3ede9e1
Thumb2 assembly parsing and encoding for SBFX.
...
llvm-svn: 139858
2011-09-15 21:58:42 +00:00
ee8f14a799
Some legalization fixes for atomic load and store.
...
llvm-svn: 139851
2011-09-15 21:20:49 +00:00
d2868cf016
Add some missing 'CHECK' lines and tidy up others.
...
llvm-svn: 139849
2011-09-15 21:17:38 +00:00
8620d97ad9
Thumb2 assembly parsing and encoding for SBC.
...
llvm-svn: 139844
2011-09-15 21:04:10 +00:00
10725a202b
Thumb2 assembly parsing and encoding for SASX.
...
llvm-svn: 139843
2011-09-15 21:01:23 +00:00
74111ee07f
Reapply r139759. Disable IV rewriting by default. See PR10916.
...
llvm-svn: 139842
2011-09-15 20:58:37 +00:00
4e91164049
Thumb2 assembly parsing and encoding for SADD16/SADD8.
...
llvm-svn: 139841
2011-09-15 20:57:39 +00:00
eaa5265285
Thumb2 assembly parsing and encoding for RSB.
...
llvm-svn: 139839
2011-09-15 20:54:14 +00:00
82dd698575
Thumb2 assembly parsing and encoding for RRX.
...
llvm-svn: 139831
2011-09-15 19:52:43 +00:00
8082169d7c
Thumb2 assembly parsing and encoding for ROR.
...
llvm-svn: 139830
2011-09-15 19:50:04 +00:00
4cbe06e7f8
Thumb2 assembly parsing and encoding for REV16/REVSH.
...
llvm-svn: 139828
2011-09-15 19:46:13 +00:00
53e2e48de7
VirtRegMap is counting spill slots, not register spills.
...
Fix the stats counters to reflect that.
llvm-svn: 139819
2011-09-15 18:31:13 +00:00
fa1ca3070b
Change all checks regarding the presence of any SSE level to always
...
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite
llvm-svn: 139817
2011-09-15 18:27:36 +00:00
ab154f0b65
Thumb2 assembly parsing and encoding for REV.
...
llvm-svn: 139813
2011-09-15 18:13:30 +00:00
5c5c42bf76
Thumb2 assembly parsing and encoding for RBIT.
...
llvm-svn: 139811
2011-09-15 18:07:14 +00:00
5e18a31da4
Thumb2 assembly parsing and encoding for signed saturating arithmetic insns.
...
llvm-svn: 139810
2011-09-15 18:06:15 +00:00
3661859214
Re-order test.
...
llvm-svn: 139795
2011-09-15 16:04:13 +00:00
888bea0b95
Make demanded-elt simplification for shufflevector slightly stronger. Spotted by inspection.
...
llvm-svn: 139768
2011-09-15 01:14:29 +00:00
76a86d3d4c
[regcoalescing] bug fix for RegistersDefinedFromSameValue.
...
An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal.
Fixes PR10920 401.bzip2 miscompile with no IV rewrite.
llvm-svn: 139765
2011-09-15 01:09:33 +00:00
16680e1d33
Thumb2 assembly parsing and encoding for PLI.
...
llvm-svn: 139757
2011-09-14 23:29:05 +00:00
2e2f6db24b
Thumb2 assembly parsing and encoding for PLD.
...
llvm-svn: 139756
2011-09-14 23:26:12 +00:00
801e06b768
Thumb2 assembly parsing and encoding for PKH.
...
llvm-svn: 139754
2011-09-14 23:16:41 +00:00
d7791b961c
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
...
llvm-svn: 139747
2011-09-14 22:46:14 +00:00
61326e08ec
Thumb2 assembly parsing and encoding for ORR.
...
llvm-svn: 139742
2011-09-14 21:43:57 +00:00
1fdddf767f
Thumb2 assembly parsing and encoding for ORN.
...
llvm-svn: 139741
2011-09-14 21:29:54 +00:00
36acc8e984
Thumb2 assembly parsing and encoding for NOP.W.
...
llvm-svn: 139740
2011-09-14 21:26:25 +00:00
752d6fd529
Thumb2 assembly parsing and encoding for MVN.
...
llvm-svn: 139739
2011-09-14 21:24:41 +00:00
9c8b9932d6
Thumb2 assembly parsing and encoding for MUL.
...
llvm-svn: 139735
2011-09-14 21:00:40 +00:00
0ecd395095
Thumb2 assembly parsing and encoding for MSR/MRS.
...
Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
e9d80bbc1d
Thumb2 assembly parsing and encoding for MRC/MRC2/MRRC/MRRC2.
...
llvm-svn: 139717
2011-09-14 19:28:49 +00:00
c39c2dfe15
Thumb2 assembly parsing and encoding for MOVT.
...
llvm-svn: 139715
2011-09-14 19:15:15 +00:00
18b8b17579
Thumb2 assembly parsing for MOV in IT block.
...
Select the right 16 vs. 32 bit encoding in an IT block.
llvm-svn: 139714
2011-09-14 19:12:11 +00:00
d4b5e3a4d9
objc_retainBlock is not NoModRef because it can update forwarding pointers
...
in memory relevant to the optimizer. rdar://10050579.
llvm-svn: 139708
2011-09-14 18:13:00 +00:00
3ac26b138b
ARM fix assembly parser handling of ranges in register lists.
...
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
llvm-svn: 139707
2011-09-14 18:08:35 +00:00
d748dbacb0
Add integer promotion support for vselect
...
llvm-svn: 139692
2011-09-14 14:42:15 +00:00
ee8157cb41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
...
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
96e00e5a24
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
...
llvm-svn: 139690
2011-09-14 05:55:28 +00:00
503eef7641
Add test case for PR10851.
...
llvm-svn: 139689
2011-09-14 04:36:54 +00:00
333a59eced
Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
...
llvm-svn: 139686
2011-09-14 02:36:14 +00:00
edc216515e
Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective.
...
llvm-svn: 139675
2011-09-14 00:29:50 +00:00
9cd29103aa
Remove unnecessary old test.
...
llvm-svn: 139674
2011-09-14 00:28:54 +00:00
fc9c4a730e
Update tests. Remove irrelevant tests.
...
llvm-svn: 139658
2011-09-13 23:07:41 +00:00
73b5d6ddc1
Delete test cases that generate code for allegrex/psp and cannot be repurposed.
...
llvm-svn: 139652
2011-09-13 22:29:13 +00:00
3eb2470eed
Make use of Eli's FileCheck sorcery to improve this test.
...
llvm-svn: 139645
2011-09-13 21:37:50 +00:00
f1518216fd
Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case.
...
llvm-svn: 139641
2011-09-13 20:50:54 +00:00
7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
...
llvm-svn: 139639
2011-09-13 20:46:26 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
...
tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
f58d6812a9
Disable tests which generate code for allegrex or psp.
...
llvm-svn: 139632
2011-09-13 20:00:35 +00:00
1af0c538e0
update checked pattern
...
llvm-svn: 139631
2011-09-13 19:59:18 +00:00
52202fbf2d
Add vselect target support for targets that do not support blend but do support
...
xor/and/or (For example SSE2).
llvm-svn: 139623
2011-09-13 19:17:42 +00:00
44ae2da4ec
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
...
llvm-svn: 139610
2011-09-13 17:59:19 +00:00
c3c60a0882
Fix encoding of Thumb2 shifted register operands with RRX shifts.
...
llvm-svn: 139606
2011-09-13 17:34:32 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
...
llvm-svn: 139588
2011-09-13 06:54:58 +00:00
f9f68b816b
[indvars] Revert r139579 until 401.bzip -arch i386 miscompilation is fixed. PR10920.
...
llvm-svn: 139583
2011-09-13 05:23:49 +00:00
061d811c51
Disable IV rewriting by default. See PR10916.
...
llvm-svn: 139579
2011-09-13 03:23:21 +00:00
5b28cc84f0
Generalize test case to handle multiple indvars modes.
...
llvm-svn: 139578
2011-09-13 03:17:25 +00:00
1191773a62
Generalize this test's CHECK statements to handle different indvars modes.
...
llvm-svn: 139577
2011-09-13 02:46:27 +00:00
57d8afde93
This test only makes sense with -enable-iv-rewrite.
...
llvm-svn: 139576
2011-09-13 02:45:26 +00:00
3de5b8e4c1
[indvars] Fix bugs in floating point IV range checks noticed by inspection.
...
llvm-svn: 139574
2011-09-13 01:59:32 +00:00
54a109845d
Conditionalize indvars test that relies on SCEV expansion of geps,
...
which is only relevant with canonical IVs
llvm-svn: 139556
2011-09-12 23:13:57 +00:00
bf6e1e2717
Change testcase commandline to be more strict and silence buildbots
...
llvm-svn: 139554
2011-09-12 22:59:26 +00:00
ff8d8a830e
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
...
destination types are equal!
llvm-svn: 139553
2011-09-12 22:59:23 +00:00
a8315c3f2b
indvars test only relevant for -enable-iv-rewrite.
...
Otherwise this case is now covered by no-iv-rewrite.ll.
llvm-svn: 139552
2011-09-12 22:59:00 +00:00
1b7090c9b3
Fix a failing ELF Thumb test. I _think_ this is right, but it's not totally clear to me what this test is doing. Could someone on an ELF platform check?
...
llvm-svn: 139549
2011-09-12 22:40:31 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
...
llvm-svn: 139542
2011-09-12 21:28:46 +00:00
973d2921e8
Revert the wrong part of r139528, and fix testcases.
...
llvm-svn: 139541
2011-09-12 21:24:07 +00:00
4a9eb5f8dc
Fix encoding of PC-relative LDRSHW with an immediate offset.
...
llvm-svn: 139537
2011-09-12 20:36:51 +00:00
d2e61e1f70
Conditionalize indvars tests that rely on SCEV expansion of geps,
...
which is relevant with canonical IVs. Anything else being checked by
these tests is already covered by early CSE.
llvm-svn: 139535
2011-09-12 20:26:34 +00:00
be7a086f58
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
...
However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
llvm-svn: 139528
2011-09-12 19:30:40 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
30e8db98b8
Removing indvars tests that directly test canonical IVs and nothing else.
...
llvm-svn: 139518
2011-09-12 18:33:08 +00:00
183013d8d4
Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for default change.
...
llvm-svn: 139517
2011-09-12 18:28:44 +00:00
57ca95961b
Fix mistake in test runline.
...
llvm-svn: 139505
2011-09-12 17:32:58 +00:00
8c6fb3af6e
Test case for r139453, WidenIV::GetExtendedOperandRecurrence.
...
llvm-svn: 139504
2011-09-12 17:20:57 +00:00
97a2a5c4dc
Associate a MemOperand with LDWCP nodes introduced during ISel.
...
This information is required if we want LDWCP to be hoisted out of loops.
llvm-svn: 139495
2011-09-12 14:43:23 +00:00
48f2b36911
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
...
llvm-svn: 139486
2011-09-11 23:19:54 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
...
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
...
llvm-svn: 139484
2011-09-11 20:23:20 +00:00
501f541b45
Really un-XFAIL the testcase, like I said I would in r139458.
...
llvm-svn: 139459
2011-09-10 02:02:27 +00:00
d9917bef6c
Fixed an assert from:
...
assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
llvm-svn: 139454
2011-09-10 01:26:21 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
...
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
5624707684
Fix test cases.
...
Generate code for Mips32r1 unless a Mips32r2 feature is tested.
llvm-svn: 139433
2011-09-09 23:14:58 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
b7910b79f5
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
...
llvm-svn: 139407
2011-09-09 21:04:06 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
...
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
de838daefd
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
...
llvm-svn: 139400
2011-09-09 20:29:17 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
...
llvm-svn: 139399
2011-09-09 20:24:45 +00:00
b4c32d92ea
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
...
llvm-svn: 139397
2011-09-09 20:19:28 +00:00
54175d519e
Tidy up formatting a bit.
...
llvm-svn: 139396
2011-09-09 20:17:49 +00:00
89b1775256
Thumb2 assembly parsing and encoding for LSL.
...
llvm-svn: 139395
2011-09-09 20:05:38 +00:00
2119a62aae
Thumb2 assembly parsing and encoding for LDRT.
...
llvm-svn: 139393
2011-09-09 20:02:15 +00:00
9b11580719
Thumb2 assembly parsing and encoding for LDRSHT.
...
llvm-svn: 139392
2011-09-09 20:01:18 +00:00
d2165b829f
Thumb2 assembly parsing and encoding for LDRSH.
...
llvm-svn: 139391
2011-09-09 19:54:30 +00:00
f1b71de4ea
Thumb2 assembly parsing and encoding for LDRSBT.
...
llvm-svn: 139390
2011-09-09 19:49:06 +00:00
779a2bee7b
Thumb2 assembly parsing and encoding for LDRSB.
...
llvm-svn: 139389
2011-09-09 19:42:40 +00:00
5af572426d
Thumb2 assembly parsing and encoding for LDRH.
...
llvm-svn: 139386
2011-09-09 19:13:53 +00:00
732f90a61c
Shuffle a bit.
...
llvm-svn: 139385
2011-09-09 19:09:54 +00:00
d22a1c6c95
Drop support for Allegrex. Allegrex implements a variant of Mips2.
...
llvm-svn: 139383
2011-09-09 19:00:51 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
...
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
a042ed5cae
Add FIXME.
...
llvm-svn: 139371
2011-09-09 16:45:31 +00:00
ba60b04148
Mark the eh.typeid.for intrinsic as being 'const', which it is inside
...
any given function. As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.
llvm-svn: 139360
2011-09-09 07:50:37 +00:00
e812f9eed5
Add disassembler test for Intel syntax. Tests r139353.
...
llvm-svn: 139356
2011-09-09 06:35:44 +00:00
df1df7edf1
Change default target architecture from Mips1 to Mips32r1 in preparation for
...
removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
llvm-svn: 139344
2011-09-09 01:13:27 +00:00
9d904e1a97
Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.
...
llvm-svn: 139330
2011-09-08 22:59:09 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
...
llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
...
Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
46b9cde019
Add a AVX version of a simple i64 -> f64 bitcast. This could be
...
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
llvm-svn: 139320
2011-09-08 21:52:33 +00:00
51920a6191
Reapply testcase from r139309!
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llvm-svn: 139318
2011-09-08 21:05:43 +00:00
7b46bb8e32
Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom
...
without a base symbol that must not have a relocation entry.
llvm-svn: 139316
2011-09-08 20:53:44 +00:00
f483c081b6
Remove this crashing test, until I figure out what's going wrong here
...
llvm-svn: 139309
2011-09-08 18:32:36 +00:00
fb113a0051
Add AVX versions of blend vector operations and fix some issues noticed
...
in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
llvm-svn: 139305
2011-09-08 18:05:08 +00:00
ea8d803bb0
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
llvm-svn: 139304
2011-09-08 18:05:02 +00:00
69a4def038
Add tests for Thumb2 LDRB indexed addressing w/ writeback.
...
llvm-svn: 139292
2011-09-08 16:49:36 +00:00
e114ba4465
This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll
...
llvm-svn: 139288
2011-09-08 08:43:23 +00:00
354b7585de
add a testcase for the previous patch
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llvm-svn: 139287
2011-09-08 08:31:31 +00:00
2550ba2a27
Add X86-SSE4 codegen support for vector-select.
...
llvm-svn: 139285
2011-09-08 08:11:19 +00:00
3d1b307672
Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881.
...
llvm-svn: 139276
2011-09-08 02:23:31 +00:00
3343da5424
Thumb2 assembly parsing and encoding for LDR post-indexed.
...
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
c086f689f8
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
...
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
2392c53e73
Thumb2 assembly parsing and encoding for LDRBT.
...
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
f40ca22cd3
Thumb2 assembly parsing and encoding for LDRB(register).
...
llvm-svn: 139266
2011-09-07 23:17:00 +00:00
e0ebc1c396
Thumb2 assembly parsing and encoding for LDR(register).
...
llvm-svn: 139264
2011-09-07 23:10:15 +00:00
c8e3656b43
Thumb2 assembly parsing and encoding for LDRB(immediate).
...
llvm-svn: 139258
2011-09-07 21:41:25 +00:00
e2d68844bc
Thumb2 assembly parsing and encoding for LDR(literal).
...
Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.
llvm-svn: 139257
2011-09-07 21:33:16 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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llvm-svn: 139256
2011-09-07 21:10:42 +00:00
fed3ab5bc1
Add tests for Thumb2 LDR(immediate) from r139254.
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llvm-svn: 139255
2011-09-07 21:06:46 +00:00
1c7406767e
Thumb2 parsing and encoding for LDMDB.
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llvm-svn: 139251
2011-09-07 19:57:53 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
...
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
02f2f89a98
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
...
This isn't exactly ideal, but it is good enough for the moment.
llvm-svn: 139245
2011-09-07 18:48:32 +00:00
5d5f4862eb
Update test for 139243
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llvm-svn: 139244
2011-09-07 18:40:06 +00:00
a31f223af8
Thumb2 parsing and encoding for LDMIA.
...
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
llvm-svn: 139242
2011-09-07 18:05:34 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
524c33a27f
When inlining exception handling code into another function, ensure that
...
duplicate tests are eliminated (for example if the two functions both have
a catch clause catching the same type, ensure the redundant one is removed).
Note that it would probably be safe to say that eh.typeid.for is 'const',
but since two calls to it with the same argument can give different results
(but only if the calls are in different functions), it seems more correct to
mark it only 'pure'; this doesn't get in the way of the optimization.
llvm-svn: 139236
2011-09-07 16:44:14 +00:00
1257042b70
Another forgotten trampoline testcase.
...
llvm-svn: 139230
2011-09-07 10:05:14 +00:00
d7430cea10
Forgot to add this trampoline testcase.
...
llvm-svn: 139229
2011-09-07 09:21:38 +00:00
e978d2f644
Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
...
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)
llvm-svn: 139221
2011-09-07 02:23:42 +00:00
9de7a7db26
While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.
...
llvm-svn: 139208
2011-09-07 00:07:58 +00:00
653cb03191
Teach BasicAA about the aliasing properties of memset_pattern16.
...
Fixes PR10872 and <rdar://problem/10065079>.
llvm-svn: 139204
2011-09-06 23:33:25 +00:00
83a6188f18
Thumb2 parsing and encoding for ISB.
...
llvm-svn: 139200
2011-09-06 22:53:27 +00:00
958feffa11
Thumb2 parsing and encoding for EOR.
...
llvm-svn: 139199
2011-09-06 22:44:50 +00:00
ed9399995a
Thumb2 parsing and encoding for DSB.
...
llvm-svn: 139194
2011-09-06 22:19:40 +00:00
e95f46384e
Thumb2 parsing and encoding for DMB.
...
llvm-svn: 139193
2011-09-06 22:14:58 +00:00
474c455060
Disable these tests harder. They're XFAIL'd, but that means they still run, and
...
these tests all infinitely recurse, bringing my system down into swapping hell.
llvm-svn: 139192
2011-09-06 22:08:18 +00:00
c048b905b4
Thumb2 parsing and encoding for DBG.
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llvm-svn: 139191
2011-09-06 22:06:40 +00:00
565e2f5752
Thumb2 parsing and encoding for CMN and CMP.
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llvm-svn: 139188
2011-09-06 21:44:58 +00:00
e0aa54bb98
This transform only handles two-operand AddRec's. Prevent it from trying to
...
handle anything more complex. Fixes PR10383 again!
llvm-svn: 139186
2011-09-06 21:42:18 +00:00
70532e289f
Thumb2 parsing and encoding for CLZ.
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llvm-svn: 139177
2011-09-06 20:44:17 +00:00
803898f119
Thumb2 parsing and encoding for CLREX.
...
llvm-svn: 139172
2011-09-06 20:27:04 +00:00
b041e866b0
Port more encoding tests over to Thumb2 decoding tests.
...
llvm-svn: 139171
2011-09-06 20:26:34 +00:00
6952281037
Thumb2 parsing and encoding for CDP/CDP2.
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llvm-svn: 139168
2011-09-06 20:12:23 +00:00
0b758ed6ba
Fix fall outs from my recent change on how carry bit is modeled during isel.
...
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
llvm-svn: 139157
2011-09-06 18:52:20 +00:00
58704ee442
Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's.
...
llvm-svn: 139150
2011-09-06 18:14:09 +00:00
50ef7611aa
Atomic pseudos don't use (as in read) CPSR. They clobber it.
...
llvm-svn: 139148
2011-09-06 17:40:35 +00:00
a098436b32
Split the init.trampoline intrinsic, which currently combines GCC's
...
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
llvm-svn: 139140
2011-09-06 13:37:06 +00:00
658bdb5133
The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was
...
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!
llvm-svn: 139133
2011-09-06 05:05:14 +00:00
b1438c763a
Revert r139126 due to selfhost failures reported by buildbots.
...
llvm-svn: 139130
2011-09-06 02:43:13 +00:00
c4c43fbb07
Teach SCEV to report a max backedge count in one interesting case in
...
HowFarToZero; the case for a canonical loop.
llvm-svn: 139126
2011-09-05 23:25:16 +00:00
4b79c21ef2
InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match.
...
Fixes clang selfhost.
llvm-svn: 139120
2011-09-05 18:16:19 +00:00
29192d042e
Delete trivial landing pads that just continue unwinding the caught
...
exception.
llvm-svn: 139117
2011-09-05 12:57:57 +00:00
fd26a954a8
Add some simple insertvalue simplifications, for the purpose of cleaning
...
up do-nothing exception handling code produced by dragonegg.
llvm-svn: 139113
2011-09-05 06:52:48 +00:00
5423017526
Revert r129875, XFAILing this test for arm, since the fix was reverted.
...
llvm-svn: 139058
2011-09-03 00:14:24 +00:00
1f72dd40c7
Pseudo CMOV instructions don't clobber EFLAGS.
...
The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
llvm-svn: 139057
2011-09-02 23:52:55 +00:00
f347d1d772
Thumb2 parsing and encoding for CBZ/CBNZ.
...
llvm-svn: 139054
2011-09-02 23:46:10 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
9e55023ca7
Thumb2 parsing and encoding for BIC.
...
llvm-svn: 139052
2011-09-02 23:37:54 +00:00
93e3fd29b2
Thumb2 parsing and encoding for BFI.
...
llvm-svn: 139051
2011-09-02 23:28:46 +00:00
be31448d99
Thumb2 parsing and encoding for BFC.
...
llvm-svn: 139050
2011-09-02 23:25:46 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
4aa2573748
Try to eliminate the use of the 'unwind' instruction.
...
llvm-svn: 139046
2011-09-02 22:41:11 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
912668d998
Better fix for this testcase. Update it to the new EH scheme entirely.
...
llvm-svn: 139039
2011-09-02 21:27:08 +00:00
17706bcffb
Update for new EH stuff. (I'm not sure if this is 100% correct.)
...
llvm-svn: 139038
2011-09-02 21:24:17 +00:00
310a448cfe
Test case update for unroll-scev.
...
llvm-svn: 139037
2011-09-02 21:21:03 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
5c04c62765
Darwin wants ctors/dtors to be ordered the other way round to linux.
...
llvm-svn: 139015
2011-09-02 18:07:19 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
...
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
b861b2b475
Tests for Thumb2 AND (immediate) instruction.
...
llvm-svn: 139013
2011-09-02 17:44:27 +00:00
63a3a0e010
Extra CHECK-NOT to make sure that GVN transform works properly.
...
llvm-svn: 139012
2011-09-02 17:40:39 +00:00
4a31ba3bae
-unroll-scev flag removal
...
llvm-svn: 139010
2011-09-02 17:36:14 +00:00
c302f5cce7
Add FIXME. Thumb2 ADR encoding choice is non-trivial.
...
llvm-svn: 139008
2011-09-02 17:21:59 +00:00
057d423e4b
ConstantVector returns arbitrary value for the wrong index.
...
This fixes PR10813.
llvm-svn: 139006
2011-09-02 15:43:43 +00:00
7470fb01d0
Compare type size instead of type _store_ size to make sure that BitCastInst
...
will be valid. This fixes PR10820.
llvm-svn: 139005
2011-09-02 14:57:37 +00:00
f5769c1070
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
...
llvm-svn: 139004
2011-09-02 10:05:01 +00:00
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
...
llvm-svn: 138997
2011-09-02 04:17:54 +00:00
723cec7a5f
Update to new EH scheme.
...
llvm-svn: 138989
2011-09-02 01:25:11 +00:00
3767be9aee
Revert r131152, r129796, r129761. This code is currently considered
...
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.
llvm-svn: 138977
2011-09-01 23:07:08 +00:00
6397051ece
Don't drop alignment info on local common symbols.
...
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
4028a51c74
Fix test; sorry for any inconvenience.
...
llvm-svn: 138966
2011-09-01 21:25:42 +00:00
71f5c2f158
Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.)
...
llvm-svn: 138965
2011-09-01 21:21:24 +00:00
cc6e92892f
Add missing newline.
...
llvm-svn: 138964
2011-09-01 21:20:11 +00:00
c032617581
XFAIL this test on arm until the backend is fixed.
...
llvm-svn: 138955
2011-09-01 18:40:03 +00:00
0f6ff8cb2b
This test depends on cmov being available.
...
llvm-svn: 138954
2011-09-01 18:40:01 +00:00
5dc87d0f4d
Permit remat of partial register defs when it is safe.
...
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:
%vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>
The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.
This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.
llvm-svn: 138953
2011-09-01 18:27:51 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
f61d1c072e
Fix vbroadcast matching logic to early unmatch if the node doesn't have
...
only one use. Fix PR10825.
llvm-svn: 138951
2011-09-01 18:15:06 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
6357fa2f06
Prevent remat of partial register redefinitions.
...
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.
This was fixed for the inline spiller in r138794. This patch fixes the
problem for all register allocators, and includes a small test case.
<rdar://problem/10032939>
llvm-svn: 138944
2011-09-01 17:18:50 +00:00
185d377597
Update to new EH scheme.
...
llvm-svn: 138933
2011-09-01 01:28:25 +00:00
d33e3007fa
Update to new EH scheme.
...
llvm-svn: 138928
2011-09-01 01:08:21 +00:00
3b17c1b48d
Update to new EH scheme.
...
llvm-svn: 138927
2011-09-01 01:02:41 +00:00
e88632d667
Update some tests to the new EH scheme.
...
llvm-svn: 138925
2011-09-01 00:58:03 +00:00
832a6a1909
PreRA scheduler should avoid cloning compares.
...
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261
llvm-svn: 138924
2011-09-01 00:54:31 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
080f40a49d
Reenable test.
...
llvm-svn: 138916
2011-08-31 23:08:05 +00:00
54b91028f0
Revert accidental commit
...
llvm-svn: 138915
2011-08-31 23:07:46 +00:00
c472975fd9
Disable this test until Bill fixes it properly.
...
llvm-svn: 138914
2011-08-31 23:03:30 +00:00
5624fe0cff
Update to new EH scheme.
...
llvm-svn: 138908
2011-08-31 21:50:07 +00:00
e336599f6d
Update to new EH scheme.
...
llvm-svn: 138906
2011-08-31 21:44:24 +00:00
55fb73a6e0
Remove old declare statements.
...
llvm-svn: 138905
2011-08-31 21:41:20 +00:00
22055c713f
Update more tests to the new EH scheme.
...
llvm-svn: 138904
2011-08-31 21:40:15 +00:00
d4e871404d
Update more tests to the new EH scheme.
...
llvm-svn: 138903
2011-08-31 21:39:05 +00:00
293c31b81c
Add tests for the transformations SCCP can do on atomic loads and stores (which are safe without any modifications).
...
llvm-svn: 138902
2011-08-31 21:37:06 +00:00
c4c24f03e9
Revert r138894. This was failing on cmake-clang-i686-msvc10.
...
llvm-svn: 138900
2011-08-31 21:20:25 +00:00
e6174a2c85
Update more tests to the new EH scheme.
...
llvm-svn: 138894
2011-08-31 21:04:11 +00:00
b1e680fd3f
Update the tests to the new EH scheme.
...
llvm-svn: 138891
2011-08-31 20:55:40 +00:00
a455a0b1e7
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
6a69d6902f
Run the Thumb1 parser tests in Thumb2 mode, as well.
...
Thumb2 is a superset of Thumb1, so all of the encodings should still work.
llvm-svn: 138883
2011-08-31 19:50:28 +00:00
6eb213c919
Thumb NOP encoding varies depending on ARCH revision.
...
llvm-svn: 138876
2011-08-31 18:35:46 +00:00
5c160fd243
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
7c3bdede25
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM.
...
llvm-svn: 138872
2011-08-31 18:26:09 +00:00
af8c3cc710
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
1ccecbb9d3
64-bit atomic cmpxchg for ARM.
...
llvm-svn: 138868
2011-08-31 17:52:22 +00:00
cdef71f4f3
Compress Repeated Byte Output
...
Emit a repeated sequence of bytes using .zero. This saves an enormous
amount of asm file space for certain programs.
llvm-svn: 138864
2011-08-31 17:30:56 +00:00
6d606fbe14
Tweak Thumb1 ADD encoding selection a bit.
...
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
llvm-svn: 138862
2011-08-31 17:07:33 +00:00
5247ca0ae5
This test requires sse, otherwise x87 ops will block tailcall optimization
...
llvm-svn: 138859
2011-08-31 16:49:05 +00:00
9fc6b8be03
- Move all MOVSS and MOVSD patterns close to their definitions
...
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
and update a testcase to check it properly
llvm-svn: 138851
2011-08-31 03:04:20 +00:00
cb1e5bae4c
Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
...
llvm-svn: 138848
2011-08-31 02:05:24 +00:00
2c7bb52f56
Some minor cleanups for r138845.
...
llvm-svn: 138846
2011-08-31 00:41:05 +00:00
c3f9c4a852
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
...
llvm-svn: 138845
2011-08-31 00:31:29 +00:00
50cabb5de4
Fix test typo.
...
llvm-svn: 138843
2011-08-31 00:02:59 +00:00
a45c20b049
Remove the old tail duplication pass. It is not used and is unable to update
...
ssa, so it has to be run really early in the pipeline. Any replacement
should probably use the SSAUpdater.
llvm-svn: 138841
2011-08-30 23:03:45 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
fdf3cd7f2b
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
...
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
d16fb43b1f
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
...
llvm-svn: 138835
2011-08-30 22:10:03 +00:00
543c89fb15
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
...
llvm-svn: 138834
2011-08-30 22:03:20 +00:00
1450f61e8f
Add a triple.
...
llvm-svn: 138831
2011-08-30 21:19:37 +00:00
b359367a3d
Remove empty file.
...
llvm-svn: 138830
2011-08-30 21:17:20 +00:00
e316e5b2ad
Speculatively revert r138809 in an attempt to fix DragonEgg.
...
llvm-svn: 138829
2011-08-30 21:11:06 +00:00
2e282257ed
Port Thumb2 assembler tests over to disassembler tests.
...
llvm-svn: 138822
2011-08-30 20:03:11 +00:00
9f2edc8d2c
Some test code to check if correct code is being generated.
...
Patch by Sanjoy Das.
llvm-svn: 138820
2011-08-30 19:51:29 +00:00
d708ec4c6a
When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does.
...
llvm-svn: 138809
2011-08-30 18:51:55 +00:00
d74c19449e
Lit option for ignoring stderr output.
...
This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!
llvm-svn: 138804
2011-08-30 17:42:33 +00:00
71038e7021
Set CR1EQ only when lowering vararg floating arguments (not any vararg
...
arguments as before), unset CR1EQ otherwise.
llvm-svn: 138802
2011-08-30 17:04:16 +00:00
4f2fba1108
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
...
llvm-svn: 138795
2011-08-30 07:09:35 +00:00
e891654a58
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
...
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
llvm-svn: 138791
2011-08-30 01:34:54 +00:00
3e0aa03fe9
Add missing encoding information for some of the GPR<->FP register moves.
...
llvm-svn: 138780
2011-08-29 23:15:25 +00:00
4b23a65582
Remove redundant tests from XFAIL'ed test file.
...
llvm-svn: 138779
2011-08-29 23:04:04 +00:00
55d6f43cab
Thumb2 assembly parsing and encoding support for ADC(immediate).
...
llvm-svn: 138778
2011-08-29 23:01:38 +00:00
89a12be8bb
Remove test file. Superceded by other more exhaustive tests.
...
llvm-svn: 138777
2011-08-29 23:00:19 +00:00
ed16ec4248
Thumb2 parsing and encoding for IT blocks.
...
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
7e2489a7c9
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
...
llvm-svn: 138771
2011-08-29 22:06:28 +00:00
850b9a9a84
Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802.
...
llvm-svn: 138768
2011-08-29 21:15:46 +00:00
e79ce47ad7
Update tests to new EH model. Add landingpad instructions to landing pads.
...
llvm-svn: 138759
2011-08-29 20:39:23 +00:00
5fc81ffbac
Fixes following the CR by Chris and Duncan:
...
Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.
llvm-svn: 138756
2011-08-29 19:58:36 +00:00
967674d26c
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
baa7edb06a
Add testcase for r138746.
...
llvm-svn: 138747
2011-08-29 18:02:40 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
4d63542b82
Fix PR5329: pay attention to constructor/destructor priority
...
when outputting them. With this, the entire LLVM testsuite
passes when built with dragonegg.
llvm-svn: 138724
2011-08-28 13:17:22 +00:00
52600ee8c3
Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X.
...
llvm-svn: 138722
2011-08-28 11:51:08 +00:00
d22f9b395b
Reverted r138652, valgrind doesn't understand obj:*/tblgen.
...
llvm-svn: 138703
2011-08-27 06:17:30 +00:00
ba198e661e
Auto upgrade the old EH scheme to use the new one. This is on a trial basis. If
...
things to disasterously over night, this can be reverted.
llvm-svn: 138702
2011-08-27 06:11:03 +00:00
2f92d2cdae
Update to new EH scheme.
...
llvm-svn: 138699
2011-08-27 04:53:41 +00:00
46c720994a
Cannot have an llvm.eh.exception call in a non-landing pad block.
...
llvm-svn: 138698
2011-08-27 04:53:28 +00:00
4f3cb540a6
Excluding ARM JIT tests until someone can fix this compilation path.
...
llvm-svn: 138676
2011-08-26 23:39:30 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
...
llvm-svn: 138660
2011-08-26 21:21:21 +00:00
ac88ab7cce
Revert r138606 until LowerInvoke has been converted to the new EH scheme.
...
llvm-svn: 138656
2011-08-26 21:11:23 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
28dc5abd05
valgrind: Always suppress tblgen leaks.
...
I'll clean up the rest of the XFAIL: vg_leak lines if this works.
llvm-svn: 138652
2011-08-26 20:41:20 +00:00
eed1e8905a
Don't sink landingpad instructions during ind-var simplification.
...
llvm-svn: 138651
2011-08-26 20:40:15 +00:00
07aeb629ec
Use %% for literals in RUN lines.
...
llvm-svn: 138647
2011-08-26 20:09:48 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
6eb9666bb8
We don't care if TableGen leaks memory.
...
llvm-svn: 138634
2011-08-26 17:00:30 +00:00
f3b6507e26
Add a testcase for r138625.
...
llvm-svn: 138626
2011-08-26 06:45:08 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
...
llvm-svn: 138623
2011-08-26 04:49:29 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
...
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
fb212a6309
SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between.
...
In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.
This shrinks the size of a Release clang by 16k on x86_64.
llvm-svn: 138618
2011-08-26 01:22:29 +00:00
62fe9e9aa6
Update to the new EH scheme.
...
llvm-svn: 138606
2011-08-25 23:48:37 +00:00
8347b86293
Add support for AVX 256-bit version of MOVDDUP!
...
llvm-svn: 138588
2011-08-25 21:40:37 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
...
rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
76e3e0b554
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
...
llvm-svn: 138552
2011-08-25 07:42:00 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
llvm-svn: 138551
2011-08-25 06:57:46 +00:00
3fb137f7ef
LSR wants to split the landing pad's critical edge. Let it do it, but use the
...
proper function to do it.
llvm-svn: 138550
2011-08-25 05:55:40 +00:00
296256fb32
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
...
llvm-svn: 138546
2011-08-25 02:58:26 +00:00
ff2091737e
Update tests to the newest EH syntax.
...
llvm-svn: 138541
2011-08-25 01:30:18 +00:00
b37db20e40
Add feature test for the new exception handling stuff.
...
llvm-svn: 138539
2011-08-25 01:19:13 +00:00
9c73a57b20
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
...
llvm-svn: 138505
2011-08-24 22:33:28 +00:00
eee864520c
Some autoconf tests use module level inline asm to test compiler's handling of
...
.cfi_startproc. e.g. libffi:
$ cat confopt.c
asm (".cfi_startproc\n\t.cfi_endproc");
int main () { return 0; }
Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.
rdar://10017184
llvm-svn: 138504
2011-08-24 22:31:37 +00:00
b2a2c031b8
Update tests for 138501.
...
llvm-svn: 138502
2011-08-24 22:30:18 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
5aabaaa367
Basic tests for atomic load and store on x86.
...
llvm-svn: 138486
2011-08-24 21:16:59 +00:00
365af6f17b
Implement Constant::isAllOnesValue(). Fix ConstantFolding to use the new api.
...
llvm-svn: 138469
2011-08-24 20:18:38 +00:00
16fd0d96f2
Port over more encoding tests to decoding tests.
...
llvm-svn: 138441
2011-08-24 17:08:34 +00:00
6e3c83eb1c
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
...
variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
de92622aa5
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
...
llvm-svn: 138427
2011-08-24 06:14:18 +00:00
9e9f2ce32d
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
...
permutations. Also tidy up some patterns and make them close to their
instruction definition!
llvm-svn: 138392
2011-08-23 22:06:37 +00:00
7bc78f692c
Revert "Address Duncan's CR request:"
...
This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340)
Conflicts:
test/Transforms/InstCombine/bitcast.ll
llvm-svn: 138366
2011-08-23 20:11:10 +00:00
37563cd545
Thumb parsing and encoding for WFE, WFI and YIELD.
...
llvm-svn: 138364
2011-08-23 20:02:30 +00:00
ad9e8655ee
Thumb parsing and encoding for UXTB and UXTH.
...
llvm-svn: 138363
2011-08-23 19:59:32 +00:00
5e4ea175f6
Thumb parsing and encoding for TST.
...
llvm-svn: 138362
2011-08-23 19:53:17 +00:00
bb07e73e0d
Thumb parsing and encoding for SXTB and SXTH.
...
llvm-svn: 138361
2011-08-23 19:51:42 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
...
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
d88404fbaa
Thumb parsing and encoding for SUB.
...
llvm-svn: 138359
2011-08-23 19:45:45 +00:00
4c8ff77f1b
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
...
llvm-svn: 138354
2011-08-23 19:01:24 +00:00
f1ca6a6df6
Thumb parsing and encoding for STRH.
...
llvm-svn: 138352
2011-08-23 18:56:20 +00:00
635aa69a91
Thumb parsing and encoding for STRB.
...
llvm-svn: 138349
2011-08-23 18:43:06 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
...
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
6e546e0725
Thumb parsing and encoding for STR.
...
Not including tSTRspi.
llvm-svn: 138347
2011-08-23 18:33:38 +00:00
d80d169a04
Thumb parsing and encoding for STM.
...
llvm-svn: 138345
2011-08-23 18:15:37 +00:00
7d3effa389
Fix a typo in the test from the previous commit.
...
llvm-svn: 138342
2011-08-23 17:56:54 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
c78e6607b5
Address Duncan's CR request:
...
1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector
llvm-svn: 138340
2011-08-23 17:48:43 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
dcea63236e
Port more assemble tests over to disassembly tests.
...
llvm-svn: 138336
2011-08-23 17:26:35 +00:00
6612e35b0d
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
...
llvm-svn: 138321
2011-08-23 04:36:33 +00:00
2a3ffb5d97
Introduce a pass to insert vzeroupper instructions to avoid AVX to
...
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.
llvm-svn: 138317
2011-08-23 01:14:17 +00:00
cc9d792ec1
Thumb parsing and encoding for SETEND.
...
llvm-svn: 138312
2011-08-22 23:58:02 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
...
llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
...
llvm-svn: 138308
2011-08-22 23:47:13 +00:00
73661b8a37
Thumb parsing and encoding for ROR.
...
llvm-svn: 138304
2011-08-22 23:40:51 +00:00
a9d88df987
Thumb parsing and encoding for REV/REV16/REVSH.
...
llvm-svn: 138303
2011-08-22 23:39:25 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
...
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
...
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
...
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
...
llvm-svn: 138295
2011-08-22 23:17:34 +00:00
096423b6be
Tidy up. Trailing whitespace.
...
llvm-svn: 138293
2011-08-22 23:13:54 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
...
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
40da063178
Thumb parsing and encoding for PUSH.
...
llvm-svn: 138290
2011-08-22 23:05:11 +00:00
5507203262
Fix think-o.
...
llvm-svn: 138288
2011-08-22 23:04:26 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
...
llvm-svn: 138287
2011-08-22 23:01:07 +00:00
0869b900cc
Thumb assembly parsing and encoding for POP.
...
llvm-svn: 138286
2011-08-22 23:00:19 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
...
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
74f090d44c
Add support for breaking 256-bit int VETCC into two 128-bit ones,
...
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.
llvm-svn: 138271
2011-08-22 20:31:04 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
fe29fe431d
Port another swathe of Thumb1 encoding tests over to decoding tests.
...
llvm-svn: 138250
2011-08-22 18:05:49 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
aa42847164
Thumb assembly parsing and encoding for ORR.
...
llvm-svn: 138245
2011-08-22 17:41:44 +00:00
56e1cef705
Constant pointers to objects don't need reference counting.
...
llvm-svn: 138242
2011-08-22 17:29:11 +00:00
bce94fded8
Make a few tests slightly more strict.
...
llvm-svn: 138241
2011-08-22 17:27:02 +00:00
b40654e21d
Testcase for PR10663.
...
llvm-svn: 138231
2011-08-22 10:32:09 +00:00
bd16424f91
Fix AsmParser binary precedence for shift operators.
...
rdar://9976729
llvm-svn: 138208
2011-08-20 16:24:13 +00:00
3322f02a03
Tidy up. Whitespace.
...
llvm-svn: 138207
2011-08-20 16:10:09 +00:00
ad4a70ad3e
Add constant folding support for bitcasts of splat vectors to integers.
...
llvm-svn: 138206
2011-08-20 14:02:29 +00:00
6582dfa7c5
Remove remainder of migrated or obsolete tests from FrontendC and remove
...
the empty directory.
llvm-svn: 138181
2011-08-20 01:04:56 +00:00
c19fd6eadc
Remove migrated or obsolete tests.
...
llvm-svn: 138176
2011-08-20 00:49:30 +00:00
1efe3d9663
Remove obsolete or migrated tests.
...
llvm-svn: 138173
2011-08-20 00:38:20 +00:00
d6641af80c
With the fix in r138164: "Add <imp-def> operands to QQ and QQQQ stack loads."
...
-verify-machineinstrs can be enabled for this test case.
llvm-svn: 138171
2011-08-20 00:34:45 +00:00
c2528a529a
Remove obsoleted test.
...
llvm-svn: 138170
2011-08-20 00:26:30 +00:00
a1124b45d2
Remove tests that were either migrated to clang or are obsolete.
...
llvm-svn: 138168
2011-08-20 00:25:42 +00:00
2f53dc2e05
Remove the rest of the files in FrontendC++ and the directory itself.
...
All tests have been updated and migrated into clang or were obsolete.
llvm-svn: 138165
2011-08-20 00:17:58 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
...
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
74cfab0fbe
Remove migrated or obsolete tests.
...
llvm-svn: 138156
2011-08-20 00:08:36 +00:00
a0b6bc5739
Remove migrated or obsolete tests.
...
llvm-svn: 138149
2011-08-19 23:41:50 +00:00
59e27c5f12
Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly.
...
llvm-svn: 138145
2011-08-19 23:28:12 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
...
The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
67edb5ef36
Remove obsolete test.
...
llvm-svn: 138141
2011-08-19 23:18:12 +00:00
2c16fef036
Remove migrated test.
...
llvm-svn: 138140
2011-08-19 23:18:10 +00:00
8d77bb5f06
Use regex to remove false dependencies on register allocation.
...
llvm-svn: 138137
2011-08-19 23:10:31 +00:00
48f1599b03
Remove obsolete or migrated tests.
...
llvm-svn: 138135
2011-08-19 23:08:41 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
...
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
...
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
...
a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
43d15b98d2
Remove tests migrated to clang.
...
llvm-svn: 138121
2011-08-19 22:26:09 +00:00
1e1cbc5f65
Remove previously migrated test.
...
llvm-svn: 138120
2011-08-19 22:26:06 +00:00
066e9ec1e4
Update tests.
...
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
58ce352d32
Remove tests migrated to clang or are unnecessary.
...
llvm-svn: 138115
2011-08-19 22:17:09 +00:00
fd4de3aeff
Thumb assembly parsing and encoding for MVN.
...
llvm-svn: 138109
2011-08-19 22:09:23 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
...
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
029529369b
Remove this test. The feature and test have already been migrated to clang.
...
llvm-svn: 138101
2011-08-19 21:51:41 +00:00
772aa6c82e
Remove tests migrated to clang.
...
llvm-svn: 138100
2011-08-19 21:51:39 +00:00
981c15ef76
Remove 2009-09-04-modify-crash.cpp as clang doesn't support 32-bit kext.
...
llvm-svn: 138087
2011-08-19 21:21:28 +00:00
05927b0c90
Remove migrated tests.
...
llvm-svn: 138086
2011-08-19 21:21:26 +00:00
e8ad105202
Remove migrated test.
...
llvm-svn: 138085
2011-08-19 21:21:24 +00:00
526162d18e
Remove this test. There are other, duplicates, in the clang test suite.
...
llvm-svn: 138084
2011-08-19 21:21:21 +00:00
8af4e41734
Add file.
...
llvm-svn: 138083
2011-08-19 21:21:20 +00:00
810ed3a7c3
Move 2010-03-22-empty-baseclass.cpp from a frontend+opt test to just
...
an opt test.
llvm-svn: 138082
2011-08-19 21:21:14 +00:00
d07e104844
Add FIXME.
...
llvm-svn: 138077
2011-08-19 20:48:54 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
...
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
1eb6eb0955
Thumb assembly parsing and encoding for LSR.
...
llvm-svn: 138065
2011-08-19 19:34:22 +00:00
3245520ade
Thumb assembly parsing and encoding for LSL(register).
...
llvm-svn: 138064
2011-08-19 19:30:58 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
...
llvm-svn: 138063
2011-08-19 19:29:25 +00:00
7c4739da3c
Thumb assembly parsing and encoding for LDRSB and LDRSH.
...
llvm-svn: 138061
2011-08-19 19:17:58 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
...
llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
...
llvm-svn: 138059
2011-08-19 18:49:59 +00:00
106281f329
Thumb assembly parsing and encoding for LDR(register).
...
llvm-svn: 138056
2011-08-19 18:35:06 +00:00
181d2f92b5
Thumb assembly parsing and encoding for LDR(literal).
...
llvm-svn: 138052
2011-08-19 18:20:48 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
...
llvm-svn: 138050
2011-08-19 18:13:48 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
...
llvm-svn: 138047
2011-08-19 17:55:24 +00:00
ba6c2a52c7
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
...
llvm-svn: 138034
2011-08-19 05:28:50 +00:00
90b6018c8f
Add test case for r138018.
...
llvm-svn: 138033
2011-08-19 04:30:24 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
...
implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
b38940135b
Track a retain+release nesting level independently of the
...
known-incremented level, because the two concepts can be used
to prove the saftey of a retain+release removal in different
ways.
llvm-svn: 138016
2011-08-19 00:26:36 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
...
Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
d7cbd4c518
FastISel: avoid function calls between the materialization of the constant and its use.
...
llvm-svn: 137993
2011-08-18 22:06:10 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
...
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
627021d7c0
More Thumb1 decoding tests.
...
llvm-svn: 137974
2011-08-18 20:05:06 +00:00
0071f8a48e
Add another test.
...
llvm-svn: 137969
2011-08-18 18:50:25 +00:00
f907e78b78
Add test to check type uniquing.
...
llvm-svn: 137968
2011-08-18 18:40:49 +00:00
6cb336cb09
Thumb assembly parsing and encoding for EOR.
...
llvm-svn: 137964
2011-08-18 18:10:38 +00:00
4f240a1fd5
Thumb assembly parsing and encoding for CMP.
...
llvm-svn: 137963
2011-08-18 18:08:29 +00:00
9f9371ccb3
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.
...
llvm-svn: 137960
2011-08-18 18:03:02 +00:00
47bf39d921
Thumb assembly parsing and encoding test for CMN.
...
llvm-svn: 137957
2011-08-18 17:55:03 +00:00
ec3884c50a
Port over BL/BLX to disassembly tests.
...
llvm-svn: 137954
2011-08-18 17:43:52 +00:00
0081879ee7
ARM assembly parsing and encoding test for BX/BLX (register).
...
llvm-svn: 137949
2011-08-18 17:02:28 +00:00
8b7158e557
ARM assembly parsing and encoding test for BL/BLX (immediate).
...
llvm-svn: 137948
2011-08-18 17:00:09 +00:00
56f3b70225
Add intrinsics for SETEV, GETED, GETET.
...
llvm-svn: 137938
2011-08-18 13:00:48 +00:00
3c7d6eb64c
Cleanup vector logical ops in AVX and add use int versions for simple
...
v2i64
llvm-svn: 137919
2011-08-18 02:11:34 +00:00
a90896397b
Port new Thumb1 encoding tests over to decoding tests.
...
llvm-svn: 137902
2011-08-17 23:37:33 +00:00
1b43828958
ARM assembly parsing and encoding test for BKPT.
...
llvm-svn: 137898
2011-08-17 23:11:13 +00:00
e3bdcd0ea8
ARM assembly parsing and encoding test for BIC.
...
llvm-svn: 137895
2011-08-17 23:00:53 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
...
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
...
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
9a468153e1
Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt).
...
llvm-svn: 137888
2011-08-17 22:22:24 +00:00
1a87fcb9ba
Fix PR10688. Add support for spliting 256-bit vector shifts when the
...
shift amount is variable
llvm-svn: 137885
2011-08-17 22:12:20 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
...
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
e2d152016f
Add a couple of FIXMEs.
...
llvm-svn: 137861
2011-08-17 20:35:57 +00:00
35ea5cfd46
Fix test case.
...
llvm-svn: 137847
2011-08-17 18:48:28 +00:00
ae2848ed69
Remove superficial test.
...
llvm-svn: 137846
2011-08-17 18:39:13 +00:00
3fee10b7d2
Robustify test.
...
llvm-svn: 137845
2011-08-17 18:38:44 +00:00
d40d838cc4
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
...
llvm-svn: 137840
2011-08-17 18:21:36 +00:00
d7749be2d7
Silly mistake from r137777; restore significant isStructTy() checks. While here, be a bit more defensive
...
with unknown instructions.
Fixes PR10687.
llvm-svn: 137836
2011-08-17 18:10:43 +00:00
80636b48c0
Thumb assembly parsing and encoding for ADC(register) instruction.
...
llvm-svn: 137833
2011-08-17 17:55:28 +00:00
a806eebe13
Add missing '@' delimiter.
...
llvm-svn: 137832
2011-08-17 17:46:01 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
...
Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
be5e987379
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
...
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
llvm-svn: 137810
2011-08-17 02:29:19 +00:00
3400825b41
Update test to not use the scalar type to splat from a load
...
llvm-svn: 137809
2011-08-17 02:29:15 +00:00
ed786a346e
Now that we have a canonical way to handle 256-bit splats:
...
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!
llvm-svn: 137807
2011-08-17 02:29:10 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
...
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
e1df253200
An additional atomic test; related to r137662.
...
llvm-svn: 137786
2011-08-16 23:29:17 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
...
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
0793eb4c46
A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop
...
making random bad assumptions about instructions which are not explicitly listed.
Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".
llvm-svn: 137777
2011-08-16 22:06:31 +00:00
d56ba41bc3
Remove tests that have been obsoleted or migrated to clang/optimizer tests.
...
llvm-svn: 137775
2011-08-16 21:46:25 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
...
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
56f2f21254
Minor bug in SCCP found by inspection. (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.)
...
llvm-svn: 137755
2011-08-16 21:12:35 +00:00
2c21bf4b43
Add testcase for r137746.
...
llvm-svn: 137754
2011-08-16 21:11:21 +00:00
d3ad0aa413
Tidy up formatting.
...
llvm-svn: 137747
2011-08-16 20:55:41 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
...
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
2e99f1b3aa
Instead of always leaving the work to the generic legalizer when
...
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:
For this shuffle:
shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
<i32 1, i32 0, i32 7, i32 6>
This was expanded to:
vextractf128 $1, %ymm1, %xmm2
vpextrq $0, %xmm2, %rax
vmovd %rax, %xmm1
vpextrq $1, %xmm2, %rax
vmovd %rax, %xmm2
vpunpcklqdq %xmm1, %xmm2, %xmm1
vpextrq $0, %xmm0, %rax
vmovd %rax, %xmm2
vpextrq $1, %xmm0, %rax
vmovd %rax, %xmm0
vpunpcklqdq %xmm2, %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
ret
Now we get:
vshufpd $1, %xmm0, %xmm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vshufpd $1, %xmm1, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
llvm-svn: 137733
2011-08-16 18:21:54 +00:00
7d7bec5acf
Add test case for r137711.
...
llvm-svn: 137725
2011-08-16 17:32:01 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
...
Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
...
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
ac992afd93
Fix test.
...
llvm-svn: 137703
2011-08-16 01:42:56 +00:00
a917d4f9b4
Revert a bit of r137667; the logic in question can safely handle atomic load/store.
...
llvm-svn: 137702
2011-08-16 01:28:22 +00:00
5403862ab7
Migrate this test from llvm/test/FrontendC++/ptr-to-method-devirt.cpp and
...
FileCheckize. It is more properly an optimizer test.
llvm-svn: 137700
2011-08-16 01:17:17 +00:00
0ffdf2ea0b
Update SimplifyCFG for atomic operations.
...
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it. I think the current behavior is correct,
though. Bill, can you double-check that?
llvm-svn: 137691
2011-08-15 23:59:28 +00:00
01a67111d1
Add comments and test for atomic load/store and mem2reg.
...
llvm-svn: 137690
2011-08-15 23:55:52 +00:00
53440984b3
Add a test file for Thumb2 NEON.
...
llvm-svn: 137687
2011-08-15 23:42:20 +00:00
67005029bc
Reorder declarations of vmovmskp* and also put the necessary AVX
...
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
8bc586e770
Update instcombine for atomic load/store.
...
llvm-svn: 137664
2011-08-15 22:09:40 +00:00
cbe7feeab9
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
...
when AVX mode is one. Otherwise is just more work for the type
legalizer.
llvm-svn: 137661
2011-08-15 21:45:54 +00:00
5286bd2d01
Add some more comprehensive VFP decoding tests.
...
llvm-svn: 137657
2011-08-15 21:29:01 +00:00
8c5f3f7624
Fix this test to avoid leaving a temporary file behind.
...
llvm-svn: 137651
2011-08-15 20:55:03 +00:00
91386c7be4
Atomic load/store support in LICM.
...
llvm-svn: 137648
2011-08-15 20:52:09 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
990dd3d0fb
Add an ipsccp test. Migrated from test/FrontendC++.
...
llvm-svn: 137646
2011-08-15 20:50:36 +00:00
944f4923a4
Add a test for Thumb1 LDRSH decoding.
...
llvm-svn: 137645
2011-08-15 20:15:43 +00:00
f746b0ec53
Add testcase for STRH. Patch by James Molloy.
...
llvm-svn: 137644
2011-08-15 20:12:03 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
746e317953
This transform is not safe. Thanks to Eli for pointing that out!
...
llvm-svn: 137575
2011-08-14 04:51:49 +00:00
ae13df60a6
Don't attempt to add 'nsw' when intermediate instructions had no such guarantee.
...
llvm-svn: 137572
2011-08-14 03:41:33 +00:00
de49278c26
Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis
...
when combining add and sub instructions. Patch by Pranav Bhandarkar!
llvm-svn: 137570
2011-08-14 01:45:19 +00:00
9f56acc124
Fix test.
...
llvm-svn: 137556
2011-08-13 17:06:34 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
...
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
02e737b08e
Move "atomic" and "volatile" designations on instructions after the opcode
...
of the instruction.
Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.
llvm-svn: 137527
2011-08-12 22:50:01 +00:00
f15dfe5818
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
...
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
llvm-svn: 137519
2011-08-12 21:48:26 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
ed6d3e813e
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
...
llvm-svn: 137495
2011-08-12 19:42:45 +00:00
2f6b944f56
Test case for 137484
...
llvm-svn: 137486
2011-08-12 18:12:06 +00:00
d1b60f7a6d
Tidy up formatting.
...
llvm-svn: 137471
2011-08-12 17:43:31 +00:00
234317d12a
Tidy up formatting.
...
llvm-svn: 137464
2011-08-12 17:01:02 +00:00
91ea511436
MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does.
...
llvm-svn: 137414
2011-08-12 01:51:29 +00:00
10a18d55ce
Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result
...
is returned through a bitcast.
llvm-svn: 137402
2011-08-12 00:36:31 +00:00
121302772d
Don't let arbitrary calls disrupt nested retain+release pairs if
...
the retains and releases all use the same SSA pointer value.
Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.
llvm-svn: 137399
2011-08-12 00:26:31 +00:00
1978ddf769
Clean up formatting a bit.
...
llvm-svn: 137393
2011-08-11 23:57:17 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
...
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
2d8494a030
A slew of unit tests for the recent LoopInfo::updateUnloop feature
...
checked in at r137276 and r137341.
llvm-svn: 137385
2011-08-11 23:38:09 +00:00
2b6860f0a1
Allow loop unrolling to get known trip counts from ScalarEvolution.
...
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.
This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.
llvm-svn: 137384
2011-08-11 23:36:16 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
...
warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
aa07cb6a98
Fix tests per now-correct encoding as of r137371.
...
llvm-svn: 137376
2011-08-11 22:31:48 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
...
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
8fbf023c9b
Add a dag combine to xform 256-bit shuffles into simple vector
...
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
llvm-svn: 137362
2011-08-11 21:50:44 +00:00
9eb3762e08
Fix the test added by Nadav in r137308. Make it more strict:
...
1) check for the "v" version of movaps
2) add a couple of CHECK-NOT to guarantee the behavior
3) move to a more appropriate test file
llvm-svn: 137361
2011-08-11 21:50:35 +00:00
7db3bfbd45
ARM STRHT assembly parsing and encoding.
...
llvm-svn: 137358
2011-08-11 21:39:41 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
2a50260f2f
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
d0767f37c1
Add FIXME.
...
llvm-svn: 137336
2011-08-11 19:43:42 +00:00
295788756d
ARM STRB assembly parsing and encoding tests.
...
llvm-svn: 137335
2011-08-11 19:42:58 +00:00
14a4164206
Fix a copy/paste error so that LDRB(register) actually gets tested.
...
llvm-svn: 137333
2011-08-11 19:34:23 +00:00
06b7f0c901
ARM STR(register) assembly parsing and encoding tests.
...
llvm-svn: 137332
2011-08-11 19:26:17 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
043c820800
Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.
...
llvm-svn: 137324
2011-08-11 18:59:13 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
e33c95d39b
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
1542d5a00a
[AVX] If the data which is going to be saved is already in two XMM registers
...
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.
Before:
vinsertf128 $1, %xmm3, %ymm0, %ymm3
vinsertf128 $0, %xmm1, %ymm3, %ymm1
vmovaps %ymm1, 416(%rsp)
After:
vmovaps %xmm3, 416+16(%rsp)
vmovaps %xmm1, 416(%rsp)
llvm-svn: 137308
2011-08-11 16:41:21 +00:00
5a2c70cc8f
add missing colon, thanks peter.
...
llvm-svn: 137306
2011-08-11 16:15:10 +00:00
96710b4308
fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
...
It's somewhat surprising anything works without this. Before we would
compile the testcase into:
test: # @test
movl $4, 8(%rdi)
movl 8(%rdi), %eax
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
now we produce:
test: # @test
movl 8(%rdi), %eax
movl $4, 8(%rdi)
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
llvm-svn: 137303
2011-08-11 06:26:54 +00:00
a2d8bb97b9
Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
...
infinite recursive calls in legalize. Fix PR10562
llvm-svn: 137296
2011-08-11 02:49:44 +00:00
572c9aaf53
Use the splat index to generate the desired shuffle. Otherwise we
...
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.
llvm-svn: 137295
2011-08-11 02:49:41 +00:00
3ae39f8ad1
Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
...
Fixes PR9693.
llvm-svn: 137292
2011-08-11 01:48:05 +00:00
94ba2cba6e
ARM tests for LDRSHT assembly parsing and encoding.
...
llvm-svn: 137274
2011-08-10 23:18:30 +00:00
a6ab52bf9f
ARM tests for LDRSH assembly parsing and encoding.
...
llvm-svn: 137272
2011-08-10 23:12:25 +00:00
2953404723
ARM tests for LDRSBT assembly parsing and encoding.
...
llvm-svn: 137271
2011-08-10 23:08:56 +00:00
c11bbf3bda
ARM tests for LDRSB assembly parsing and encoding.
...
llvm-svn: 137270
2011-08-10 23:06:44 +00:00
35cdf36c32
Add FIXME.
...
llvm-svn: 137265
2011-08-10 22:56:43 +00:00
5e0c9711f2
ARM tests for LDRHT assembly parsing and encoding.
...
llvm-svn: 137263
2011-08-10 22:55:38 +00:00
504769fc2f
test/CodeGen/X86/opt-shuff-tstore.ll: Add explicit -mtriple=x86_64-linux.
...
llvm-svn: 137262
2011-08-10 22:52:48 +00:00
7cd4253cc3
ARM tests for LDRH(register) assembly parsing and encoding.
...
llvm-svn: 137261
2011-08-10 22:45:42 +00:00
cd4dd255c0
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
ae1b002fa3
Add FIXME
...
llvm-svn: 137258
2011-08-10 22:20:38 +00:00
1d9d5e93d1
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
37a62058fe
While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.
...
llvm-svn: 137250
2011-08-10 21:25:34 +00:00
5b96b80644
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
d2b071f562
Fix the test. Add cpu target.
...
llvm-svn: 137241
2011-08-10 19:49:19 +00:00
410a11fe82
When performing a truncating store, it is sometimes possible to rearrange the
...
data in-register prior to saving to memory. When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.
llvm-svn: 137238
2011-08-10 19:30:14 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
3ff111c12d
The following X86 pattern is incorrect:
...
def : Pat<(X86Movss VR128:$src1,
(bc_v4i32 (v2i64 (load addr:$src2)))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.
llvm-svn: 137227
2011-08-10 17:45:17 +00:00
36a3abc671
Add support for the R and Q constraints.
...
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
4d0040baf8
Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534.
...
llvm-svn: 137203
2011-08-10 04:29:49 +00:00
278ffd7d8e
Fix a bug in vpermilps mask checking. Fix PR10560
...
llvm-svn: 137194
2011-08-10 01:54:17 +00:00
c6bd551db0
Remove the build_unwind function from the OCaml bindings.
...
llvm-svn: 137193
2011-08-10 01:10:17 +00:00
b72bbe2a92
Fix the LoopUnroller to handle nontrivial loops and partial unrolling.
...
These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.
llvm-svn: 137190
2011-08-10 00:28:10 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
92b942b1b5
Tighten operand checking of register-shifted-register operands.
...
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
72323966c8
Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
...
llvm-svn: 137179
2011-08-09 23:27:13 +00:00
e008931bf6
Tighten operand checking on memory barrier instructions.
...
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
3d2e0e9db6
Tighten operand checking on CPS instructions.
...
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
042619f97d
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
...
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
fc481959d2
Add v16i16 and v32i8 store patterns
...
llvm-svn: 137166
2011-08-09 22:39:53 +00:00
6963062a99
Use fp unpack instructions to unpack int types. Until we have AVX2, this
...
is the best we can do for these patterns. This fix PR10554.
llvm-svn: 137161
2011-08-09 22:18:37 +00:00
4ef2426b87
Fix a couple ridiculous copy-paste errors. rdar://9914773 .
...
llvm-svn: 137160
2011-08-09 22:17:39 +00:00
406dc1755f
ARM Disassembler: sign extend branch immediates.
...
Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
7a2401dbf0
Tighten Thumb1 branch predicate decoding.
...
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
d7f41b7f66
Revert r137134. It breaks some code as Eli pointed out.
...
llvm-svn: 137135
2011-08-09 18:56:35 +00:00
84ec8f65d1
Print out the variable declaration only if it is a declaration. Otherwise, a
...
'static' variable will be emitted twice.
PR10081
llvm-svn: 137134
2011-08-09 18:31:50 +00:00
53910d6aae
Inflate register classes after coalescing.
...
Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class. Examples are:
x86: GR32_ABCD:sub_8bit_hi -> GR32
arm: DPR_VFP2:ssub0 -> DPR
Recompute the register class of any virtual registers that are used by
less instructions after coalescing.
This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:
vadd.f32 d16, d1, d0
vcvt.s32.f32 d0, d16
The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.
llvm-svn: 137133
2011-08-09 18:19:41 +00:00
bed48dc8ff
Reapply a more appropriate solution than in r137114. AVX supports
...
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.
llvm-svn: 137128
2011-08-09 17:39:13 +00:00
24dd1d4a27
Revert r137114
...
llvm-svn: 137127
2011-08-09 17:39:01 +00:00
db05c2b963
PTX: Add initial support for device function calls
...
- Calls are supported on SM 2.0+ for function with no return values
llvm-svn: 137125
2011-08-09 17:36:31 +00:00
ad3453cf2d
Handle sitofp between v4f64 <- v4i32. Fix PR10559
...
llvm-svn: 137114
2011-08-09 05:48:01 +00:00
1155b1eafa
Add support for avx vector fextend
...
llvm-svn: 137105
2011-08-09 03:04:29 +00:00
337a7fdb13
Rename and tidy up tests
...
llvm-svn: 137103
2011-08-09 03:04:23 +00:00
2fc107365b
Add two patterns to match special vmovss and vmovsd cases. Also fix
...
the patterns already there to be more strict regarding the predicate.
This fixes PR10558
llvm-svn: 137100
2011-08-09 01:43:09 +00:00
af6a85484c
Make LowerVSETCC aware of AVX types and add patterns to match them.
...
llvm-svn: 137090
2011-08-09 00:46:57 +00:00
b24a1d29cb
Tidy up these testcases to look more like real code does.
...
llvm-svn: 137085
2011-08-09 00:33:11 +00:00
cab35c0836
ARM parsing and encoding for LDRBT instruction.
...
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
5838c0c47e
ARM parsing and encoding for LDRB instruction.
...
llvm-svn: 137071
2011-08-08 22:37:06 +00:00
f6dbc3a57c
Add FIXME.
...
llvm-svn: 137070
2011-08-08 22:11:33 +00:00
c96953c12a
Add support for several vector shifts operations while in AVX mode. Fix PR10581
...
llvm-svn: 137067
2011-08-08 21:31:08 +00:00
a27da98921
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
...
llvm-svn: 137061
2011-08-08 19:49:37 +00:00
4f0ace5674
Don't clobber pending ST regs when FP regs are killed.
...
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints. It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.
When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.
This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.
This fixes PR10602.
llvm-svn: 137050
2011-08-08 17:15:43 +00:00
6d45a01b67
Made SCEV's UDiv expressions more canonical. When dividing a
...
recurrence, the initial values low bits can sometimes be ignored.
To take advantage of this, added FoldIVUser to IndVarSimplify to fold
an IV operand into a udiv/lshr if the operator doesn't affect the
result.
-indvars -disable-iv-rewrite now transforms
i = phi i4
i1 = i0 + 1
idx = i1 >> (2 or more)
i4 = i + 4
into
i = phi i4
idx = i0 >> ...
i4 = i + 4
llvm-svn: 137013
2011-08-06 07:00:37 +00:00
3d0b3a3a50
ARM load instruction shifted register index operands.
...
Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
c320c85261
ARM indexed load assembly parsing and encoding.
...
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
llvm-svn: 136982
2011-08-05 21:28:30 +00:00
0f2dd284e9
Add ARM LDR parsing tests.
...
llvm-svn: 136977
2011-08-05 20:33:39 +00:00
c0174048a4
We need to map DebugLoc. It leads to Fuction * (through subprogram entry node) which should be appropriately mapped.
...
llvm-svn: 136910
2011-08-04 20:02:18 +00:00
6ddbb2e277
Linke NamedMDNodes after linking global values as comment suggests.
...
llvm-svn: 136909
2011-08-04 19:44:28 +00:00
77dde89b90
Fix the bitwidth of the remaining fields.
...
llvm-svn: 136884
2011-08-04 17:00:11 +00:00
9bc32a96be
print st_shndx with the correct number of bits.
...
llvm-svn: 136880
2011-08-04 15:50:13 +00:00
9528995e3f
print st_other with the correct number of bits.
...
llvm-svn: 136877
2011-08-04 15:38:19 +00:00
96df560ce1
print st_type with the correct number of bits.
...
llvm-svn: 136875
2011-08-04 15:24:00 +00:00
79ef75dc49
Print st_bind with the correct number of bits.
...
llvm-svn: 136874
2011-08-04 15:10:35 +00:00
1848231ad1
Print r_sym with the correct number of bits.
...
llvm-svn: 136873
2011-08-04 14:48:27 +00:00
260af5cef6
Print r_type with the correct number of bits.
...
llvm-svn: 136872
2011-08-04 14:39:30 +00:00
1b282e7e49
Another counter goes decimal.
...
llvm-svn: 136871
2011-08-04 14:27:46 +00:00
65c559c5fb
Change anther counter to decimal.
...
llvm-svn: 136870
2011-08-04 14:01:03 +00:00
cad9e7f094
Don't print a counter in hex.
...
llvm-svn: 136869
2011-08-04 13:39:15 +00:00
69c67d3b18
Print all the bits in the addend.
...
llvm-svn: 136867
2011-08-04 13:00:24 +00:00
e4df09f7ba
Fix http://llvm.org/bugs/show_bug.cgi?id=10568
...
Move the reloc size assert into AsmBackend - where it is more apropos.
llvm-svn: 136855
2011-08-04 00:38:45 +00:00
e234f6ae0c
Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR.
...
Fixes PR10527.
llvm-svn: 136853
2011-08-04 00:32:58 +00:00
d359571120
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
3c7e9ee480
Remove underscore that's breaking linux buildbots.
...
llvm-svn: 136833
2011-08-03 23:13:01 +00:00
15e5b742ad
Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.
...
llvm-svn: 136826
2011-08-03 22:34:43 +00:00
2d3138c112
Remove the LowerSetJmp pass. It wasn't used effectively by any of the targets.
...
This is some of my original LLVM code. *wipes tear*
llvm-svn: 136821
2011-08-03 22:18:20 +00:00
bf69d03382
SCEV: Use AssertingVH to catch dangling BasicBlock* when passes forget
...
to notify SCEV of a change. Add forgetLoop in a couple of those places.
llvm-svn: 136797
2011-08-03 18:32:11 +00:00
da618420ee
Handle IMPLICIT_DEF instructions in X86FloatingPoint.
...
This fixes PR10575.
llvm-svn: 136787
2011-08-03 16:33:19 +00:00
5b82a0ac0c
fix PR10286, a problem with the .ll printer handling block addresses that are out-of-scope.
...
llvm-svn: 136768
2011-08-03 06:15:41 +00:00
dc9cbaaf23
Use byte offset, instead of element number, to access merged global.
...
llvm-svn: 136759
2011-08-03 01:25:46 +00:00
50f4966ceb
Fix logical error when detecting lifetime intrinsics.
...
Don't replace a gep/bitcast with 'undef' because that will form a "free(undef)"
which in turn means "unreachable". What we wanted was a no-op. Instead, analyze
the whole tree and look for all the instructions we need to delete first, then
delete them second, not relying on the use_list to stay consistent.
llvm-svn: 136752
2011-08-03 00:43:35 +00:00
e8ae02dfb9
Teach InstCombine that lifetime intrincs aren't a real user on the result of a
...
malloc call.
llvm-svn: 136732
2011-08-02 22:08:01 +00:00
99890a225f
Lifetime intrinsics on undef are dead.
...
llvm-svn: 136722
2011-08-02 21:19:27 +00:00
c48e10cd54
Assume .cfi_startproc is the first thing in a function. If the function is
...
externally visable, create a local symbol to use in the CFE. If not, use the
function label itself.
Fixes PR10420.
llvm-svn: 136716
2011-08-02 20:24:22 +00:00
5ada908140
Make this kind of lowering to be supported by 256-bit instructions:
...
shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494
llvm-svn: 136691
2011-08-02 16:06:18 +00:00
c4189ff0fc
Remove empty test.
...
llvm-svn: 136675
2011-08-02 02:47:45 +00:00
bddf40e082
Revert r136503 and r136480 in an effort to fix non-determinism in the llvm-gcc buildbots on i386. Devang is looking into the root cause.
...
llvm-svn: 136674
2011-08-02 02:23:42 +00:00
a8e3673816
Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
...
the legalizer. This commit together with the two previous ones fixes
PR10495.
llvm-svn: 136654
2011-08-01 21:54:09 +00:00
7513939ddd
Since vectors with all ones can't be created with a 256-bit instruction,
...
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547
llvm-svn: 136642
2011-08-01 19:51:53 +00:00
0cc000ef29
Fix crash with varargs function with no named parameters.
...
llvm-svn: 136623
2011-08-01 16:45:59 +00:00
a3a44f3fc3
Add a small gep optimization I noticed was missing while reading some IL.
...
llvm-svn: 136585
2011-07-31 04:43:41 +00:00
99d53ff456
Remove InvalidateStructLayoutInfo from the ocaml bindings.
...
llvm-svn: 136582
2011-07-31 01:12:39 +00:00
ad088e6724
Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,
...
r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.
llvm-svn: 136556
2011-07-30 05:42:50 +00:00
5670f850c6
Revert "Don't check liveness of unallocatable registers."
...
The ARM target depends on CPSR liveness being tracked after register
allocation.
llvm-svn: 136548
2011-07-30 00:57:25 +00:00
95cc5440e9
Don't check liveness of unallocatable registers.
...
This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.
While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.
llvm-svn: 136541
2011-07-29 23:36:21 +00:00
aa5030066f
Add support for the 'Q' constraint.
...
Fixes rdar://9866494
llvm-svn: 136523
2011-07-29 21:18:58 +00:00
51726e2147
ARM SRS instruction parsing, diassembly and encoding support.
...
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
3e02522fee
Clean up debug info after reassociation.
...
llvm-svn: 136480
2011-07-29 19:00:35 +00:00
c4dc52cd52
ARM assembly parsing and encoding for RFE instruction.
...
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
llvm-svn: 136479
2011-07-29 18:47:24 +00:00
1c1d2438aa
ARM update tests for CPS instruction.
...
llvm-svn: 136472
2011-07-29 17:39:27 +00:00
65ce5ea3ba
Fix two tests that I crashed in the previous commits. The mask elts
...
on the second half must be reindexed.
llvm-svn: 136454
2011-07-29 02:05:28 +00:00
81eb193f2e
Match VPERMIL masks more strictly and update the target specific mask
...
generation to always catch the weird cases.
llvm-svn: 136453
2011-07-29 01:31:15 +00:00
d23709b18c
Add v8i32 and v4i64 vpermil patterns
...
llvm-svn: 136451
2011-07-29 01:31:07 +00:00
b28ee4115d
Transfer implicit operands in NEONMoveFixPass.
...
Later passes /are/ using this information when running the register
scavenger.
This fixes the second problem in PR10520.
llvm-svn: 136440
2011-07-29 00:27:35 +00:00
9c3badceba
Add -verify-arm-pseudo-expand.
...
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.
The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.
llvm-svn: 136439
2011-07-29 00:27:32 +00:00
530341d748
Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829>
...
llvm-svn: 136435
2011-07-29 00:18:19 +00:00
b9bebc1b03
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
...
llvm-svn: 136408
2011-07-28 21:59:38 +00:00
a03ab0e3dc
ARM assembly parsing and encoding for BLX (immediate).
...
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
llvm-svn: 136406
2011-07-28 21:57:55 +00:00
b16081ce8c
Handle REG_SEQUENCE with implicitly defined operands.
...
Code like that would only be produced by bugpoint, but we should still
handle it correctly.
When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.
Fixes part of PR10520.
llvm-svn: 136401
2011-07-28 21:38:51 +00:00
7f45559e86
Remove obsolete FIXME reference in comment.
...
llvm-svn: 136400
2011-07-28 21:37:05 +00:00
864b609491
ARM assembly parsing and encoding for BFC and BFI.
...
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
llvm-svn: 136399
2011-07-28 21:34:26 +00:00
8b3184e540
ARM parsing and encoding for ADR.
...
The label does not have a '#' prefix. Add parsing and encoding tests.
llvm-svn: 136360
2011-07-28 16:33:54 +00:00
4356636fc0
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
...
llvm-svn: 136358
2011-07-28 16:00:41 +00:00
483354758f
Due to changes coming from the new LLVM type system, you now get
...
bitcasts in this test rather than getelementptr instructions;
llvm-gcc produces two bitcasts, clang produces one.
llvm-svn: 136349
2011-07-28 12:21:47 +00:00
76bc28bac6
Add patterns to generate copies for extract_subvector instead of
...
using vextractf128. This will reduce the number of issued instruction
for several avx codes.
llvm-svn: 136323
2011-07-28 01:26:50 +00:00
eca99c4b5a
Add a few patterns to match allzeros without having to use the fp unit.
...
Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491
llvm-svn: 136321
2011-07-28 01:26:43 +00:00
9e2a301216
Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move
...
a convert pattern close to the instruction definition.
llvm-svn: 136320
2011-07-28 01:26:39 +00:00
4059137f56
ARM parsing and encoding tests.
...
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
llvm-svn: 136312
2011-07-28 00:37:03 +00:00
eda1d4f3ba
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
...
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
2011-07-27 23:22:03 +00:00
e37f7dc349
ARM assembly parsing and encoding for USUB16 and USUB8.
...
llvm-svn: 136289
2011-07-27 23:10:05 +00:00
05f80d3add
ARM assembly parsing and encoding for USAX.
...
llvm-svn: 136288
2011-07-27 23:07:00 +00:00
5ef6c453a6
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
...
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
llvm-svn: 136287
2011-07-27 23:01:50 +00:00
16dd4adcbe
Clean up tabs.
...
llvm-svn: 136286
2011-07-27 22:35:06 +00:00
57e2d3cb84
ARM assembly parsing and encoding support for USAT and USAT16.
...
Use range checked immediate operands for instructions. Add tests.
llvm-svn: 136285
2011-07-27 22:34:17 +00:00
fea7a44a9b
ARM assembly parsing and encoding tests for USAD8 and USADA8.
...
llvm-svn: 136284
2011-07-27 22:23:02 +00:00
1644409b47
ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
...
llvm-svn: 136282
2011-07-27 22:13:08 +00:00
1a3ddffc1c
Fix comment copy/paste-o.
...
llvm-svn: 136281
2011-07-27 22:11:41 +00:00
84ecab228a
ARM assembly parsing and encoding tests for UQASX and UQSAX.
...
llvm-svn: 136280
2011-07-27 22:09:30 +00:00
928f4175c0
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
...
llvm-svn: 136279
2011-07-27 22:08:14 +00:00
39b062bfaa
ARM assembly parsing and encoding for UMULL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136277
2011-07-27 22:01:42 +00:00
0c398b9c7e
ARM assembly parsing and encoding for UMLAL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136274
2011-07-27 21:58:11 +00:00
121c21aba9
ARM assembly parsing and encoding tests for UMAAL.
...
llvm-svn: 136272
2011-07-27 21:53:42 +00:00
7cfd32a006
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
...
llvm-svn: 136267
2011-07-27 21:21:59 +00:00
3f45383ef5
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
...
llvm-svn: 136266
2011-07-27 21:20:45 +00:00
03f56d9de6
ARM parsing and encoding of SBFX and UBFX.
...
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
llvm-svn: 136264
2011-07-27 21:09:25 +00:00
36ce7492a6
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
...
llvm-svn: 136261
2011-07-27 20:43:44 +00:00
542333ea05
ARM assembly parsing and encoding tests for TST instruction.
...
llvm-svn: 136260
2011-07-27 20:38:58 +00:00
f176e1addb
ARM assembly parsing and encoding tests for TEQ instruction.
...
llvm-svn: 136259
2011-07-27 20:37:36 +00:00
fa9e6d43a0
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
...
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
6c923bb8d9
Merge the contents from exception-handling-rewrite to the mainline.
...
This adds the new instructions 'landingpad' and 'resume'.
llvm-svn: 136253
2011-07-27 20:18:04 +00:00
833b9d3353
ARM assembly parsing and encoding for extend instructions.
...
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
llvm-svn: 136252
2011-07-27 20:15:40 +00:00
8ac9ecedfd
Teach the ConstantMerge pass about alignment. Fixes PR10514!
...
llvm-svn: 136250
2011-07-27 19:47:34 +00:00
27a30a7792
The vpermilps and vpermilpd have different behaviour regarding the
...
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.
llvm-svn: 136200
2011-07-27 00:56:34 +00:00
f098ce2757
It is quiet possible that inlined function body is split into multiple chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry.
...
llvm-svn: 136196
2011-07-27 00:34:13 +00:00
d23b96f923
Remove these two directories. The tests can be ported to dragonegg if
...
they're still wanted.
llvm-svn: 136193
2011-07-27 00:07:56 +00:00
4481732015
Remove test/FrontendC, almost all of the tests have been migrated
...
to clang now, the rest are in process (6) or have been deleted.
llvm-svn: 136191
2011-07-26 23:49:39 +00:00
c3bcb02154
Eliminate copies of undefined values during coalescing.
...
These copies would coalesce easily, but the resulting value would be
defined by a deleted instruction. Now we also remove the undefined value
number from the destination register.
This fixes PR10503.
llvm-svn: 136174
2011-07-26 23:00:24 +00:00
a79c1e0589
Update test.
...
llvm-svn: 136170
2011-07-26 22:45:39 +00:00
124ac2b997
Add a neat little two's complement hack for x86.
...
On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.
This code is generated for __builtin_clz and friends.
llvm-svn: 136167
2011-07-26 22:42:13 +00:00
f8fe47bd2b
Recognize unpckh* masks and match 256-bit versions. The new versions are
...
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases
llvm-svn: 136157
2011-07-26 22:03:40 +00:00
93dc04d5ca
Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130.
...
llvm-svn: 136148
2011-07-26 21:02:58 +00:00
73a8393a47
FileCheck'ize test.
...
llvm-svn: 136135
2011-07-26 20:49:44 +00:00
747430417b
XFAIL this test while I investigate it; it's failing for an unexpected reason.
...
llvm-svn: 136131
2011-07-26 20:41:03 +00:00
06b8b571b2
Add obvious missing case to switch. PR10497.
...
llvm-svn: 136130
2011-07-26 20:38:49 +00:00
edaa35ae6f
ARM diagnostics for ldrexd/stredx out of order paired register operands.
...
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
4e895470bd
ARM parsing and encoding tests for load/store exclusive instructions.
...
llvm-svn: 136105
2011-07-26 18:07:21 +00:00
15e8d74231
ARM assembly parsing and encoding for SWP[B] instructions.
...
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
f16378479b
ARM parsing and encoding for SVC instruction.
...
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
2c374c4fb6
ARM assembly parsing and encoding tests for SUB instruction.
...
llvm-svn: 136089
2011-07-26 15:44:05 +00:00
dc45f00cf5
Update ARM STM tests. Fix check: prefix for diagnostic tests.
...
llvm-svn: 136088
2011-07-26 15:41:22 +00:00
d600a0f878
Add 256-bit isel for movsldup/movshdup
...
llvm-svn: 136051
2011-07-26 02:39:32 +00:00
9becc53e32
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
...
llvm-svn: 136013
2011-07-25 23:32:14 +00:00
15e2d90746
Finish adding support for lifetime intrinsics to SROA. Fixes PR10121!
...
llvm-svn: 136008
2011-07-25 23:14:22 +00:00
475c6dbef6
ARM assembly parsing and encoding for SSAT16 instruction.
...
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
9212bf275d
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
...
This also fixes PR10452
llvm-svn: 136004
2011-07-25 23:05:32 +00:00
123dff0f58
- Handle special scalar_to_vector case: splats. Using a native 128-bit
...
shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.
llvm-svn: 136002
2011-07-25 23:05:25 +00:00
442d1b199f
Attempt to fix test failure reported on llvm-commits.
...
llvm-svn: 135995
2011-07-25 22:28:51 +00:00
cbd3ba91b7
Make sure this DAGCombine actually returns an UNDEF of the correct type; PR10476.
...
llvm-svn: 135993
2011-07-25 22:25:42 +00:00
3a9cbeed73
ARM assembly parsing and encoding for SSAT instruction.
...
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
ea8c66fea5
Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask.
...
Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle.
llvm-svn: 135980
2011-07-25 21:36:45 +00:00
38b1ed8ce2
Move some ELF directives into ELF asm parser.
...
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.
rdar://9827089
llvm-svn: 135921
2011-07-25 17:55:35 +00:00
56a56eb80e
Correctly handle <undef> tied uses when rewriting after a split.
...
This fixes PR10463. A two-address instruction with an <undef> use
operand was incorrectly rewritten so the def and use no longer used the
same register, violating the tie constraint.
Fix this by always rewriting <undef> operands with the register a def
operand would use.
llvm-svn: 135885
2011-07-24 20:23:50 +00:00
6320f52ff4
Move the last uses of RetainFunc etc. over to using getRetainCallee() etc.
...
so that a declaration for objc_retain is created when needed if it doesn't
already exist. rdar://9825114.
llvm-svn: 135821
2011-07-22 22:29:21 +00:00
d69b3423a8
Add FIXME
...
llvm-svn: 135819
2011-07-22 22:15:38 +00:00
bc5d709ad9
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
...
llvm-svn: 135818
2011-07-22 22:13:00 +00:00
e7e1e163db
ARM assembly parsing and encoding updates.
...
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
llvm-svn: 135817
2011-07-22 22:06:05 +00:00
999afadffa
ARM assembly parsing and encoding tests.
...
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
llvm-svn: 135810
2011-07-22 21:34:56 +00:00
7a2075511b
Fix test check!
...
llvm-svn: 135802
2011-07-22 20:55:28 +00:00
a89039998d
Fix PR10422 by adding the necessary AVX UCOMISD memory versions to
...
load folding logic
llvm-svn: 135801
2011-07-22 20:53:20 +00:00
5b84e16503
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
...
llvm-svn: 135800
2011-07-22 20:51:24 +00:00
e2220221a2
ARM assembly parsing and encoding tests.
...
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
llvm-svn: 135798
2011-07-22 20:30:40 +00:00
8dfcc0bb92
ARM assembly parsing and encoding of SMLAL instruction.
...
Fix parsing of carry-setting variant SMLALS and add tests.
llvm-svn: 135797
2011-07-22 20:18:21 +00:00
d7c8c35301
ARM encoding and assembly parsing of SMLAD{X} instructions.
...
Fix encoding of destination register. Add tests.
llvm-svn: 135796
2011-07-22 20:11:20 +00:00
0b28f0cca2
ARM testcases for assembly parsing and encoding SMLA* instructions.
...
llvm-svn: 135795
2011-07-22 20:01:34 +00:00
77242dd537
Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64
...
too. Patch by Jeff Muizelaar.
llvm-svn: 135789
2011-07-22 18:56:05 +00:00
d1f8bde10f
ARM assembly parsing and encoding for SMC instruction.
...
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
24ace20824
ARM encoding and assembly parsing tests.
...
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
llvm-svn: 135780
2011-07-22 18:04:48 +00:00
0a547701a4
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
4535b9194a
ARM assembly parsing and encoding tests for SEL instruction.
...
llvm-svn: 135772
2011-07-22 16:59:33 +00:00
612e56174b
-Inspected a AVX code block added by someone in early Feb. This was never used
...
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.
- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.
- Fix a fragile test and make it more useful.
llvm-svn: 135729
2011-07-22 00:15:07 +00:00
14a95bda04
Although we already support this, add testcases for consistency
...
llvm-svn: 135728
2011-07-22 00:15:03 +00:00
91eff5140f
Add a DAGCombine for transforming 128->256 casts into a simple
...
vxorps + vinsertf128 pair of instructions
llvm-svn: 135727
2011-07-22 00:15:00 +00:00
e106aee6f5
Fix MergeInVectorType to check for vector types with the same alloc
...
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.
llvm-svn: 135721
2011-07-21 23:30:09 +00:00
3354674b48
ARM parsing and encoding tests for SBC instruction.
...
llvm-svn: 135718
2011-07-21 23:03:59 +00:00
8dbf59d041
ARM testcases for SADD/SASX parsing and encoding.
...
llvm-svn: 135715
2011-07-21 23:00:49 +00:00
2a0320c877
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135713
2011-07-21 22:56:30 +00:00
17806e6636
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135712
2011-07-21 22:37:43 +00:00
2a22c06267
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
...
llvm-svn: 135710
2011-07-21 22:29:23 +00:00
b31e60b7c6
ARM parsing and encodings tests for saturating arithmetic insns.
...
llvm-svn: 135709
2011-07-21 22:18:28 +00:00
0a8d89242f
ARM assembly parsing POP/PUSH mnemonics.
...
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
llvm-svn: 135702
2011-07-21 19:57:11 +00:00
b2aa2c4a24
Add tests for ARM PKH assembly parsing.
...
llvm-svn: 135696
2011-07-21 19:02:03 +00:00
178fb40612
- Register v16i16 as valid VR256 register class
...
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16
llvm-svn: 135663
2011-07-21 02:24:08 +00:00
b878caa5e2
Add support for 256-bit versions of VPERMIL instruction. This is a new
...
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
llvm-svn: 135662
2011-07-21 01:55:47 +00:00
bd243d0dfe
LSR, correct fix for rdar://9786536. Silly casting bug.
...
llvm-svn: 135654
2011-07-21 01:45:54 +00:00
858e9f083d
LSR must sometimes sign-extend before generating double constants.
...
rdar://9786536
llvm-svn: 135650
2011-07-21 01:05:01 +00:00
8acb434402
LSR crashes on an empty IVUsers list.
...
rdar://9786536
llvm-svn: 135644
2011-07-21 00:40:04 +00:00
bcd50a10d5
While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value.
...
llvm-svn: 135627
2011-07-20 21:57:04 +00:00
0cdc148ab8
Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef.
...
llvm-svn: 135625
2011-07-20 21:37:47 +00:00
ae60b6b008
Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.
...
llvm-svn: 135607
2011-07-20 19:36:11 +00:00
2ea9f25f5f
Add parsing/encoding tests for ARM ORR instruction.
...
llvm-svn: 135602
2011-07-20 18:48:53 +00:00
a3fcb962eb
Consolidate ARM NOP encoding test.
...
llvm-svn: 135600
2011-07-20 18:39:38 +00:00
614e90a126
ARM parsing and encoding tests for MVN
...
llvm-svn: 135599
2011-07-20 18:37:08 +00:00
8d11490771
ARM assembly parsing of MUL instruction.
...
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
llvm-svn: 135596
2011-07-20 18:20:31 +00:00
6ed783228d
PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
...
llvm-svn: 135595
2011-07-20 18:14:33 +00:00
76792992d6
Add MCObjectFileInfo and sink the MCSections initialization code from
...
TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
llvm-svn: 135569
2011-07-20 05:58:47 +00:00
638b355a16
indvars: Added getInsertPointForUses to find a valid place to truncate the IV.
...
llvm-svn: 135568
2011-07-20 05:32:06 +00:00
60648578ba
New pointer rotate test.
...
llvm-svn: 135562
2011-07-20 03:09:11 +00:00
f53622e129
indvars test case for r135558.
...
llvm-svn: 135559
2011-07-20 02:14:37 +00:00
c5dd3e976a
indvars -disable-iv-rewrite fix: derived GEP IVs
...
llvm-svn: 135558
2011-07-20 02:08:58 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
ccf243d56b
Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.
...
llvm-svn: 135535
2011-07-19 23:14:32 +00:00
55d6ccbb79
PR10386: Don't try to split an edge from an indirectbr.
...
llvm-svn: 135534
2011-07-19 22:59:41 +00:00
d25c2cdad7
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
97094d8f06
ARM assembly parsing of MRS instruction.
...
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
llvm-svn: 135527
2011-07-19 21:59:29 +00:00
7d1e5f11ea
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
...
Add range checking to the immediate operands. Update tests accordingly.
llvm-svn: 135521
2011-07-19 20:35:35 +00:00
f3b29992d5
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
...
ANDi, when the instruction does not have any immediate operands.
llvm-svn: 135520
2011-07-19 20:34:00 +00:00
b17d9b12a6
Move mr[r]c[2] ARM tests and tidy up a bit.
...
llvm-svn: 135517
2011-07-19 20:28:56 +00:00
69721dce67
ARM testcases for MOVT.
...
llvm-svn: 135516
2011-07-19 20:23:25 +00:00
5cc3b4cd9a
ARM assembly parsing for MOV (register).
...
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
llvm-svn: 135513
2011-07-19 20:10:31 +00:00
7c09e3c3f3
ARM assembly parsing for MOV (immediate).
...
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
llvm-svn: 135500
2011-07-19 19:13:28 +00:00
20dd6e9fae
Whitespace.
...
llvm-svn: 135499
2011-07-19 19:02:39 +00:00
e450358a21
Remove redundant instructions.
...
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
llvm-svn: 135495
2011-07-19 18:14:26 +00:00
f1b800998a
Add intrinsics for the zext / sext instructions.
...
llvm-svn: 135476
2011-07-19 13:28:50 +00:00
252c43ee88
Add intrinsics for the testct, testwct instructions.
...
llvm-svn: 135475
2011-07-19 13:00:40 +00:00
707f0beae1
Add intrinsics for the peek and endin instructions.
...
llvm-svn: 135474
2011-07-19 12:50:25 +00:00
56e99c7933
Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteed
...
to perform a signed wrap. Don't rely on any particular handling of that case.
llvm-svn: 135471
2011-07-19 08:22:57 +00:00
2129f59637
Introduce MCCodeGenInfo, which keeps information that can affect codegen
...
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
llvm-svn: 135468
2011-07-19 06:37:02 +00:00
9ab3cac694
Revert r135423.
...
llvm-svn: 135454
2011-07-19 00:28:24 +00:00
4d5532a085
FileCheck-ize a couple tests.
...
llvm-svn: 135427
2011-07-18 21:23:42 +00:00
4dc76f2438
During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
...
[take 2]
llvm-svn: 135423
2011-07-18 20:55:23 +00:00
7da2417c8a
indvars: LinearFunctionTestReplace for non-canonical IVs.
...
For -disable-iv-rewrite, perform LFTR without generating a new
"canonical" induction variable. Instead find the "best" existing
induction variable for use in the loop exit test and compute the final
value of that IV for use in the new loop exit test. In short,
convert to a simple eq/ne exit test as long as it's cheap to do so.
llvm-svn: 135420
2011-07-18 20:32:31 +00:00
338879a7f4
Do not treat atomic.load.sub differently than other atomic binary intrinsics.
...
llvm-svn: 135418
2011-07-18 19:58:59 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
...
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
c45d38e14a
Fix a crash when building 177.mesa for armv6.
...
When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.
We need the value number entering the instruction.
<rdar://problem/9793765>
llvm-svn: 135413
2011-07-18 18:47:13 +00:00
4208cace5f
Add AVX 128-bit sqrt versions
...
llvm-svn: 135404
2011-07-18 17:51:40 +00:00
d8921f939c
Delete empty unused file.
...
llvm-svn: 135379
2011-07-18 05:54:06 +00:00
c56b9c75d5
More minor adjustments.
...
llvm-svn: 135342
2011-07-16 07:28:35 +00:00
0318036c4d
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
...
llvm-svn: 135337
2011-07-16 02:41:28 +00:00
4480040191
Add AVX 128-bit patterns for sint_to_fp
...
llvm-svn: 135332
2011-07-16 00:50:20 +00:00
f5a8cc7ef8
Finish propagating %asmtmp->%1 change.
...
llvm-svn: 135330
2011-07-16 00:26:07 +00:00
8b4cf5e8a2
fix rdar://9776316 - type remapping needed for inline asm blobs,
...
fixing some objc llvm-test crashes with LTO.
llvm-svn: 135324
2011-07-15 23:18:40 +00:00
8df9cfc279
Fix a couple of things:
...
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.
2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.
3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.
4) Tidy up code to be more clear and explicit about AVX.
llvm-svn: 135313
2011-07-15 22:24:33 +00:00
3846acc98e
PR10370: Make sure we know how to relax push correctly on x86-64.
...
llvm-svn: 135303
2011-07-15 21:28:39 +00:00
c1e40f8d26
A real testcase for r135286.
...
llvm-svn: 135299
2011-07-15 20:58:38 +00:00
32500bc68b
Update these tests, no longer outputting names for the variables.
...
llvm-svn: 135298
2011-07-15 20:58:16 +00:00
b45111556d
Add testcase for r135286.
...
llvm-svn: 135291
2011-07-15 19:06:58 +00:00
454e1c7abb
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
...
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
03a8a16f32
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
...
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
llvm-svn: 135203
2011-07-14 22:04:21 +00:00
51849920f1
Add some testcases for ARM MLA/MLS instructions.
...
llvm-svn: 135196
2011-07-14 21:43:05 +00:00
26e7449443
ARM MCRR/MCRR2 immediate operand range checking.
...
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
d37d2025e9
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
e336a290a6
Enable some tests we now handle correctly.
...
llvm-svn: 135185
2011-07-14 21:02:23 +00:00
92464be28c
Check register class matching instead of width of type matching
...
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
llvm-svn: 135180
2011-07-14 20:13:52 +00:00
6778597deb
Add 256-bit load/store recognition and matching in several places.
...
llvm-svn: 135171
2011-07-14 18:50:58 +00:00
2f9aeeef3b
Update ARM Assembly of LDM/STM.
...
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
llvm-svn: 135168
2011-07-14 18:35:38 +00:00
d616cf3497
ARM ISB assembly parsing tests.
...
llvm-svn: 135158
2011-07-14 18:02:25 +00:00
b218202586
ARM ISB instruction assembly parsing.
...
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
2011-07-14 18:00:31 +00:00
0c666b4664
Add a testcase for r135123.
...
Part of rdar://9761830
llvm-svn: 135133
2011-07-14 06:23:09 +00:00
15cd5a3f12
Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
...
llvm-svn: 135126
2011-07-14 01:38:42 +00:00
e6f8b1fac6
ARM tests for EOR instruction parsing and encoding.
...
llvm-svn: 135119
2011-07-14 00:22:21 +00:00
f34e35da1c
Remove duplicate tests.
...
llvm-svn: 135117
2011-07-14 00:19:19 +00:00
a0958d7abf
ARM Assembler support for DSB instruction.
...
Add instalias for default 'sy' option. Add tests.
llvm-svn: 135116
2011-07-14 00:18:13 +00:00
44c3f08e85
ARM Assembler support for DMB instruction.
...
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
llvm-svn: 135109
2011-07-13 23:40:38 +00:00
507ba77465
ARM Assembler support for DBG instruction.
...
Add range checking and testing for parsing and encoding of DBG instruction.
llvm-svn: 135102
2011-07-13 22:59:38 +00:00
3c4d652210
We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
...
llvm-svn: 135099
2011-07-13 22:28:55 +00:00
307de01867
ARM parsing and encoding tests for CMN/CMP.
...
llvm-svn: 135098
2011-07-13 22:26:58 +00:00
9559d360e5
Shuffle ARM assembly tests a bit.
...
llvm-svn: 135095
2011-07-13 22:19:10 +00:00
31756c2283
Range checking for CDP[2] immediates.
...
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
9613b64916
Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
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general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.
llvm-svn: 135088
2011-07-13 21:36:51 +00:00
344ec79715
Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
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<rdar://problem/9763308>
llvm-svn: 135084
2011-07-13 21:29:53 +00:00
adb29b6dbb
Fix predicates for Thumb co-processor instructions.
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They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
llvm-svn: 135081
2011-07-13 21:14:23 +00:00
ec8989115d
Testcases for ARM assembly BX/BXJ instructions.
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llvm-svn: 135078
2011-07-13 20:25:46 +00:00
2371a3f14a
Testcases for ARM assembly BLX/BL instructions.
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llvm-svn: 135072
2011-07-13 20:11:04 +00:00
975b641ee8
Range checking for 16-bit immediates in ARM assembly.
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llvm-svn: 135071
2011-07-13 20:10:10 +00:00
4a40a747ba
Change test case, one that actually failed before my commit.
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llvm-svn: 135064
2011-07-13 19:19:44 +00:00
c845e55374
Add tests for ARM parsing of 'BKPT' instruction.
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llvm-svn: 135063
2011-07-13 19:17:36 +00:00
43b45e2790
Fix copy-pasto.
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llvm-svn: 135062
2011-07-13 19:16:30 +00:00
Evan Cheng