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4 Commits

Author SHA1 Message Date
Matt Arsenault 57b5966dad DAG: Handle odd vector sizes in calling conv splitting 
This already worked if only one register piece was used,
but didn't if a type was split into multiple, unequal
sized pieces.

Fixes not splitting 3i16/v3f16 into two registers for
AMDGPU.

This will also allow fixing the ABI for 16-bit vectors
in a future commit so that it's the same for all subtargets.

llvm-svn: 341801
 2018-09-10 11:49:23 +00:00
Matt Arsenault bf07a50a98 AMDGPU: Restrict extract_vector_elt combine to loads 
The intention is to enable the extract_vector_elt load combine,
and doing this for other operations interferes with more
useful optimizations on vectors.

Handle any type of load since in principle we should do the
same combine for the various load intrinsics.

llvm-svn: 341219
 2018-08-31 15:39:52 +00:00
Matt Arsenault cea7c6969d DAG: Check transformed type for forming fminnum/fmaxnum from vselect 
Follow up to r340655 to fix vector types which are split.

llvm-svn: 340766
 2018-08-27 18:11:31 +00:00
Matt Arsenault 5b9ef39bdd DAG: Allow matching fminnum/fmaxnum from vselect 
llvm-svn: 340655
 2018-08-24 21:24:18 +00:00