d9790793d6
[mips][microMIPS] Implement CACHEE and PREFE instructions
...
Differential Revision: http://reviews.llvm.org/D11628
llvm-svn: 247125
2015-09-09 09:10:46 +00:00
2da1437d62
[mips][microMIPS] Implement LLE, LUI, LW and LWE instructions
...
Differential Revision: http://reviews.llvm.org/D1179
llvm-svn: 247017
2015-09-08 15:02:50 +00:00
9eaa30d2bf
[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
...
Differential Revision: http://reviews.llvm.org/D11801
llvm-svn: 246999
2015-09-08 10:18:38 +00:00
68be5f21a9
[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions
...
Differential Revision: http://reviews.llvm.org/D10956
llvm-svn: 246987
2015-09-08 08:25:34 +00:00
7b85682541
[mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions
...
Differential Revision: http://reviews.llvm.org/D11674
llvm-svn: 246968
2015-09-07 13:01:04 +00:00
ada7091812
[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions
...
Differential Revision: http://reviews.llvm.org/D11181
llvm-svn: 246963
2015-09-07 11:56:37 +00:00
14f308e44f
[mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions
...
Differential Revision: http://reviews.llvm.org/D12141
llvm-svn: 246960
2015-09-07 10:31:31 +00:00
89ca2b982e
[mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions
...
Differential Revision: http://reviews.llvm.org/D11978
llvm-svn: 246919
2015-09-05 09:25:30 +00:00
56585d517b
[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions
...
Differential Revision: http://reviews.llvm.org/D10955
llvm-svn: 245554
2015-08-20 11:51:49 +00:00
2fe8466f6e
[mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions
...
Differential Revision: http://reviews.llvm.org/D10953
llvm-svn: 245297
2015-08-18 14:40:43 +00:00
a6593ff613
[mips][microMIPS] Implement SW and SWE instructions
...
Differential Revision: http://reviews.llvm.org/D10869
llvm-svn: 245293
2015-08-18 12:53:08 +00:00
366783e14c
[mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions
...
Differential Revision: http://reviews.llvm.org/D10923
llvm-svn: 244744
2015-08-12 12:45:16 +00:00
1c78ca6a09
[mips] Remap move as or.
...
Summary:
This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.
This patch preserves the disassembly behaviour so that disassembling a old style
(d)addu move still appears as move, but assembling move always gives an or
Patch by Simon Dardis.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11796
llvm-svn: 244579
2015-08-11 08:56:25 +00:00
974d409259
[mips] Added support for the ERETNC instruction.
...
Summary: This required adding the instruction predicate HasMips32r5.
Patch by Scott Egerton.
Reviewers: dsanders, vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11136
llvm-svn: 242666
2015-07-20 12:28:56 +00:00
2a47d08afd
[mips][microMIPS] Implement SLL and NOP instructions
...
http://reviews.llvm.org/D10474
llvm-svn: 241150
2015-07-01 09:54:51 +00:00
b2fa8add82
[mips] Fold duplicate big-endian disassembler tests together.
...
llvm-svn: 240887
2015-06-27 17:56:44 +00:00
abe7d840b9
[mips] Sort big-endian disassembler tests by opcode.
...
llvm-svn: 240885
2015-06-27 16:13:59 +00:00
de692cae9d
[mips] Make little-endian disassembler test filenames consistent.
...
Most are named *-el.txt. Renamed the three that were *-le.txt
llvm-svn: 240884
2015-06-27 15:42:25 +00:00
a3134fae17
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
...
Summary:
Previously it (incorrectly) used GPR's.
Patch by Simon Dardis. A couple small corrections by myself.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10567
llvm-svn: 240883
2015-06-27 15:39:19 +00:00
67e04be640
[mips][microMIPS] Implement BREAK, EHB and EI instructions
...
http://reviews.llvm.org/D10090
llvm-svn: 240531
2015-06-24 10:32:16 +00:00
cdfcbe41f2
[mips][microMIPS] Implement ERET and ERETNC instructions
...
http://reviews.llvm.org/D10091
llvm-svn: 239522
2015-06-11 10:22:46 +00:00
fcecf26092
[mips][microMIPSr6] Change disassembler tests to one line format
...
llvm-svn: 239519
2015-06-11 09:42:10 +00:00
85a53a1ed5
[mips][microMIPSr6] Implement SEB and SEH instructions
...
Differential Revision: http://reviews.llvm.org/D9739
llvm-svn: 238333
2015-05-27 15:39:47 +00:00
888830adfe
[mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions
...
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.
Differential Revision: http://reviews.llvm.org/D10031
llvm-svn: 238325
2015-05-27 14:19:22 +00:00
dde61c00c3
[mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions
...
Differential Revision: http://reviews.llvm.org/D8800
llvm-svn: 237697
2015-05-19 14:12:55 +00:00
299fed6b7d
[mips][microMIPSr6] Implement AND and ANDI instructions
...
Differential Revision: http://reviews.llvm.org/D8772
llvm-svn: 237696
2015-05-19 13:32:31 +00:00
3825261572
[mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions
...
Differential Revision: http://reviews.llvm.org/D8769
llvm-svn: 237685
2015-05-19 11:21:37 +00:00
cc0c0fc926
[mips][microMIPSr6] Implement LSA instruction
...
This patch implements LSA instruction using mapping.
Differential Revision: http://reviews.llvm.org/D8919
llvm-svn: 237634
2015-05-18 23:12:10 +00:00
cbb227b48d
[mips][microMIPSr6] Implement ALIGN and AUI instructions
...
This patch implements ALIGN and AUI instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8782
llvm-svn: 237563
2015-05-18 11:44:30 +00:00
6fec325d10
[mips][microMIPSr6] Implement CLO and CLZ instructions
...
This patch implements CLO and CLZ instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8553
llvm-svn: 237257
2015-05-13 14:18:11 +00:00
38bb81db85
[mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions
...
This patch implements SELEQZ and SELNEZ instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8497
llvm-svn: 237158
2015-05-12 17:39:32 +00:00
8abad7bacc
[mips][microMIPSr6] Implement ALUIPC and AUIPC instructions
...
This patch implements ALUIPC and AUIPC instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8441
llvm-svn: 236858
2015-05-08 14:25:11 +00:00
9ce6e0a926
[mips][microMIPSr6] Implement ADDIUPC and LWPC instructions
...
This patch implements ADDIUPC and LWPC instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8415
llvm-svn: 236852
2015-05-08 13:52:04 +00:00
cf98462818
[mips][microMIPSr6] Implement JIALC and JIC instructions
...
This patch implements JIALC and JIC instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8389
llvm-svn: 236748
2015-05-07 17:12:23 +00:00
4160c802d9
[mips][msa] Test basic operations for the N32 ABI too.
...
Summary:
This required adding instruction aliases for dneg.
N64 will be enabled shortly but requires additional bugfixes.
Reviewers: vkalintiris
Reviewed By: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D9341
llvm-svn: 236489
2015-05-05 08:48:35 +00:00
4d532b5617
[mips] Sorted instructions in mips64r6 disassembly tests. NFC.
...
llvm-svn: 236223
2015-04-30 10:52:42 +00:00
387ce30685
[mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions
...
Differential Revision: http://reviews.llvm.org/D8894
llvm-svn: 236131
2015-04-29 17:23:22 +00:00
cca29e8f6e
[mips][microMIPSr6] Implement SUB and SUBU instructions
...
Differential Revision: http://reviews.llvm.org/D8764
llvm-svn: 236118
2015-04-29 16:22:46 +00:00
5f34d44354
[mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions
...
Differential Revision: http://reviews.llvm.org/D8704
llvm-svn: 236111
2015-04-29 15:11:07 +00:00
8e086cedfa
[mips][microMIPSr6] Implement CACHE and PREF instructions
...
Implement CACHE and PREF instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8893
llvm-svn: 235379
2015-04-21 11:17:25 +00:00
207d248eba
[mips][microMIPSr6] Implement BITSWAP instruction
...
Implement BITSWAP instruction using mapping.
Differential Revision: http://reviews.llvm.org/D8857
llvm-svn: 235321
2015-04-20 18:14:59 +00:00
676d60125c
[mips][microMIPSr6] Implement disassembler support
...
Implement disassembler support for microMIPS32r6.
Differential Revision: http://reviews.llvm.org/D8490
llvm-svn: 235307
2015-04-20 14:40:38 +00:00
1779314e3c
[mips] Add backend support for Mips32r[35] and Mips64r[35].
...
Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: tomatabacu, llvm-commits, atanasyan
Differential Revision: http://reviews.llvm.org/D7381
llvm-svn: 229695
2015-02-18 16:24:50 +00:00
a19216c8f4
[mips] Merge disassemblers into a single implementation.
...
Summary:
Currently we have Mips32 and Mips64 disassemblers and this causes the target
triple to affect the disassembly despite all the relevant information being in
the ELF header. These implementations do not need to be separate.
This patch merges them together such that the appropriate tables are checked
for the subtarget (e.g. Mips64 is checked when GP64 is enabled).
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7498
llvm-svn: 228825
2015-02-11 11:28:56 +00:00
416886793f
[mips][microMIPS] Implement movep instruction
...
Differential Revision: http://reviews.llvm.org/D7465
llvm-svn: 228703
2015-02-10 16:36:20 +00:00
e76eb41c21
[mips][microMIPS] Add disassembler tests for 16-bit instructions BREAK16 and SDBBP16
...
Differential Revision: http://reviews.llvm.org/D7443
llvm-svn: 228687
2015-02-10 13:20:51 +00:00
d68d424abf
[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16
...
Differential Revision: http://reviews.llvm.org/D7436
llvm-svn: 228683
2015-02-10 12:41:13 +00:00
df464ae224
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
...
llvm-svn: 227430
2015-01-29 11:33:41 +00:00
e10a02ecf0
[mips][microMIPS] Implement LWGP instruction
...
Differential Revision: http://reviews.llvm.org/D6650
llvm-svn: 227325
2015-01-28 17:27:26 +00:00
0516a5b686
When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions.
...
llvm-svn: 227084
2015-01-26 10:33:43 +00:00
f4ebbc6825
mips: Fix "XPASS" test results by removing 'not' commands
...
These tests are asserting and crashing for me, and 'not' sees that as a
non-zero exit code instead of a signal code for obscure Windows reasons.
This causes the test to pass, giving me an unclean 'ninja check'.
The test is already XFAILd, so just run the test without 'not' and let
lit handle the failure.
llvm-svn: 226958
2015-01-23 22:55:31 +00:00
5cfebdde2b
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
...
Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226657
2015-01-21 12:39:30 +00:00
2c6d73207e
[mips][microMIPS] Implement ADDIUPC instruction
...
Differential Revision: http://reviews.llvm.org/D6582
llvm-svn: 226656
2015-01-21 12:10:11 +00:00
435cf8a415
[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.
...
llvm-svn: 226652
2015-01-21 10:47:36 +00:00
0d49117769
Reverted revision 226577.
...
llvm-svn: 226595
2015-01-20 19:29:28 +00:00
45f7f9c1ab
[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
...
Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226577
2015-01-20 16:45:27 +00:00
01dce6c931
[mips] 'CHECK :' is not a valid check directive. Fixed.
...
llvm-svn: 226409
2015-01-18 18:43:10 +00:00
0cb9dc6e68
[mips] Make whitespace in disassembler tests more consistent. NFC.
...
The tests for the ISA's should now be approximately diffable. That is, the
output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines
for instructions that were added/removed to/from MIPS-I by MIPS-II. This
doesn't work perfectly at the moment due to ordering differences but it
should be close.
llvm-svn: 226408
2015-01-18 18:38:36 +00:00
46ad7cbfce
[mips] Make whitespace of disassembler tests more consistent by removing blank lines. NFC.
...
llvm-svn: 226407
2015-01-18 18:21:19 +00:00
df3ed1c9d6
Add disassembler tests for mips64r6 platform. There are no functional changes.
...
llvm-svn: 226166
2015-01-15 14:18:12 +00:00
d6d486ddcc
Add disassembler tests for mips32r6 platform. There are no functional changes.
...
llvm-svn: 226165
2015-01-15 14:11:38 +00:00
5dcf17b881
Add disassembler tests for mips64r2 platform. There are no functional changes.
...
llvm-svn: 226164
2015-01-15 14:06:34 +00:00
e993dac523
Add disassembler tests for mips64 platform. There are no functional changes.
...
llvm-svn: 226151
2015-01-15 08:50:20 +00:00
1080666e80
Add disassembler tests for mips32r2 platform. There are no functional changes.
...
llvm-svn: 225980
2015-01-14 11:35:22 +00:00
62dfce3240
Add disassembler tests for mips32r2 platform. There are no functional changes.
...
llvm-svn: 225967
2015-01-14 10:18:56 +00:00
9761e96b01
[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions
...
Differential Revision: http://reviews.llvm.org/D5271
llvm-svn: 225627
2015-01-12 12:03:34 +00:00
ab6d1cce3e
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions
...
Differential Revision: http://reviews.llvm.org/D5204
llvm-svn: 224785
2014-12-23 19:55:34 +00:00
12c6982b3b
[mips][microMIPS] Implement LWSP and SWSP instructions
...
Differential Revision: http://reviews.llvm.org/D6416
llvm-svn: 224771
2014-12-23 16:16:33 +00:00
2deca34803
[mips][microMIPS] Implement SWP and LWP instructions
...
Differential Revision: http://reviews.llvm.org/D5667
llvm-svn: 224338
2014-12-16 14:59:10 +00:00
a489a631ae
Add disassembler tests for mips4 platform. There are no functional changes.
...
llvm-svn: 224335
2014-12-16 13:02:25 +00:00
b736bf3899
Move mips1 tests to test/MC/Disassembler/Mips/mips1
...
This matches the pattern of the mips2 and 3 tests, as well as our normal
conventions.
llvm-svn: 224254
2014-12-15 17:56:02 +00:00
d7ecf49e97
Add disassembler tests for mips3 platform. There are no functional changes.
...
llvm-svn: 224253
2014-12-15 16:19:34 +00:00
19703a0bd6
Add disassembler tests for mips2 platform. There are no functional changes.
...
llvm-svn: 224252
2014-12-15 15:58:20 +00:00
b682ddf33a
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
...
llvm-svn: 223006
2014-12-01 11:12:04 +00:00
c7e220f6e0
[mips][microMIPS] Implement NOP aliases
...
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.
http://reviews.llvm.org/D6440
llvm-svn: 222953
2014-11-29 13:29:24 +00:00
b4484d62ad
[mips] Add synci instruction.
...
Patch by Amaury Pouly
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6421
llvm-svn: 222899
2014-11-27 17:28:10 +00:00
aa2b9278fe
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
...
Differential Revision: http://reviews.llvm.org/D6419
llvm-svn: 222887
2014-11-27 14:41:44 +00:00
315e7eca1b
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16
...
Differential Revision: http://reviews.llvm.org/D6405
llvm-svn: 222847
2014-11-26 18:56:38 +00:00
ea22c4cfbb
[mips][microMIPS] Implement disassembler support for 16-bit instructions
...
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.
Differential Revision: http://reviews.llvm.org/D6149
llvm-svn: 222648
2014-11-24 13:29:59 +00:00
a4c4b5fc01
[mips][micromips] Implement SWM32 and LWM32 instructions
...
Differential Revision: http://reviews.llvm.org/D5519
llvm-svn: 222367
2014-11-19 16:44:02 +00:00
55bb542856
[mips][microMIPS] Add disassembler tests for new microMIPS 32-bit
...
instructions: LWXS, BGEZALS, BLTZALS, BEQZC, BNEZC, JALS and JALRS.
http://reviews.llvm.org/D5413
llvm-svn: 222349
2014-11-19 11:49:57 +00:00
92db6b78f7
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref
...
Fixes PR21015, and PR20993.
Patch by Jun Koi
llvm-svn: 218745
2014-10-01 08:26:55 +00:00
dc06718e0b
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions
...
Summary:
It seems we accidentally read the wrong column of the table MIPS64r6 spec
and used the names for c.cond.fmt instead of cmp.cond.fmt.
Differential Revision: http://reviews.llvm.org/D4387
llvm-svn: 212607
2014-07-09 10:40:20 +00:00
2e03d66453
[mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu.
...
We have detected a documentation bug in the encoding tables of the released
MIPS64r6 specification that has resulted in the wrong encodings being used for
these instructions in LLVM. This commit corrects them.
llvm-svn: 212330
2014-07-04 10:08:27 +00:00
5c14b06940
[mips][mips64r6] Add BLTC and BLTUC instructions
...
Differential Revision: http://reviews.llvm.org/D3923
llvm-svn: 211167
2014-06-18 14:36:00 +00:00
00463119a5
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
...
Summary:
There is no change to the restrictions, just the result register is stored
once in the encoding rather than twice. The rt field is zero in
MIPS32r6/MIPS64r6.
Depends on D4119
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4120
llvm-svn: 211019
2014-06-16 13:18:59 +00:00
6a803f6162
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.
...
Summary:
The linked-load, store-conditional operations have been re-encoded such
that have a 9-bit offset instead of the 16-bit offset they have prior to
MIPS32r6/MIPS64r6.
While implementing this, I noticed that the atomic load/store pseudos always
emit a sign extension using sll and sra. I have improved this to use seb/seh
when they are available (MIPS32r2/MIPS64r2 and above).
Depends on D4118
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4119
llvm-svn: 211018
2014-06-16 13:13:03 +00:00
28a0ca0759
[mips][mips64r6] Add bgec and bgeuc instructions
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Differential Revision: http://reviews.llvm.org/D4017
llvm-svn: 210770
2014-06-12 11:47:44 +00:00
595fcab2d0
[mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).
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Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format.
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D4019
llvm-svn: 210654
2014-06-11 15:05:56 +00:00
d3d017cf00
Reduce verbiage of lit.local.cfg files
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We can just split targets_to_build in one place and make it immutable.
llvm-svn: 210496
2014-06-09 22:42:55 +00:00
2855142ac5
[mips][mips64r6] Add LDPC instruction
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Differential Revision: http://reviews.llvm.org/D3822
llvm-svn: 210460
2014-06-09 09:49:51 +00:00
5c582b2f6d
[mips][mips64r6] Add b[on]vc
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Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.
* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
* Also made non-functional change to DecodeBranchTarget and
DecodeBranchTargetMM to keep implementation style consistent between
them.
* Difficult encodings are handled by a custom decode method on the most
general encoding in the group. This method will convert the MCInst to a
different opcode if necessary.
DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.
jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.
Depends on D3760
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3761
llvm-svn: 209415
2014-05-22 11:23:21 +00:00
c0437c7782
[mips] Move disassembler test (test_2r_msa64) into correct folder.
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llvm-svn: 208594
2014-05-12 16:59:34 +00:00
440000d6ec
[mips] Move disassembler test (Mips MSA test_vec) into correct folder.
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llvm-svn: 208592
2014-05-12 16:31:45 +00:00
36c426e491
[mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct folder.
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llvm-svn: 208590
2014-05-12 16:26:53 +00:00
cfc8871596
[mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.
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llvm-svn: 208589
2014-05-12 16:23:45 +00:00
04092f5bc5
[mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct folder.
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llvm-svn: 208588
2014-05-12 16:20:46 +00:00
7fd9339e38
[mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.
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llvm-svn: 208587
2014-05-12 16:16:59 +00:00
38a9a8b675
[mips] Move disassembler test (Mips MSA test_bit) into correct folder.
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llvm-svn: 208586
2014-05-12 16:10:00 +00:00
b4fce72b32
[mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into
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correct folder.
llvm-svn: 208584
2014-05-12 16:03:20 +00:00
43e978234a
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
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llvm-svn: 202706
2014-03-03 13:12:59 +00:00
7d63392da9
LL and SC decoder method fix.
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llvm-svn: 199316
2014-01-15 13:17:33 +00:00
d4cb61cf0e
Added support for LWU microMIPS instruction.
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llvm-svn: 199315
2014-01-15 13:01:18 +00:00
ccb70caa13
Support for microMIPS trap instruction with immediate operands.
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llvm-svn: 194569
2013-11-13 13:15:03 +00:00
c18b6d1083
Support for microMIPS trap instructions 1.
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llvm-svn: 194205
2013-11-07 14:35:24 +00:00
8a80aa76c8
Support for microMIPS branch instructions.
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llvm-svn: 193992
2013-11-04 14:53:22 +00:00
507e084a18
Support for microMIPS jump instructions
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llvm-svn: 193623
2013-10-29 16:38:59 +00:00
8a37f63714
Mips: Disassemble sign-extended 64 bit immediates properly.
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This doesn't change the meaning of the output, but makes look right. PR17539.
llvm-svn: 192483
2013-10-11 19:05:08 +00:00
fc26cfcde7
Fixed bug when generating Load Upper Immediate microMIPS instruction.
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llvm-svn: 190746
2013-09-14 07:35:41 +00:00
3671a5441a
Support for microMIPS DIV instructions.
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llvm-svn: 190745
2013-09-14 07:15:21 +00:00
ab85278137
Support for misc microMIPS instructions.
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llvm-svn: 190744
2013-09-14 06:49:25 +00:00
b936da159e
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
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llvm-svn: 190154
2013-09-06 13:08:00 +00:00
457ba56b05
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
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llvm-svn: 190152
2013-09-06 12:53:21 +00:00
e0fbb44a48
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
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llvm-svn: 190148
2013-09-06 12:41:17 +00:00
dde3d582a2
This patch adds support for microMIPS disassembler and disassembler make check tests.
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llvm-svn: 190144
2013-09-06 12:30:36 +00:00
9bfa2e2e7f
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
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Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
9efbedfd35
[tests] Cleanup initialization of test suffixes.
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- Instead of setting the suffixes in a bunch of places, just set one master
list in the top-level config. We now only modify the suffix list in a few
suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).
- Aside from removing the need for a bunch of lit.local.cfg files, this enables
4 tests that were inadvertently being skipped (one in
Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
XFAILED).
- This commit also fixes a bunch of config files to use config.root instead of
older copy-pasted code.
llvm-svn: 188513
2013-08-16 00:37:11 +00:00
8bce21c154
[mips] Fix FP conditional move instructions to have explicit FP condition code
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register operands.
llvm-svn: 187242
2013-07-26 20:51:20 +00:00
1fb1b8b811
[mips] Fix FP branch instructions to have explicit FP condition code register
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operands.
llvm-svn: 187238
2013-07-26 20:13:47 +00:00
53900e5124
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
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instructions "beqz", "bnez" and "move", when possible.
beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or $2, $3, $zero => move $2, $3
llvm-svn: 187229
2013-07-26 18:34:25 +00:00
263c6af8f3
[mips] Increase the number of floating point control registers available to 32.
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Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
llvm-svn: 185373
2013-07-01 20:31:44 +00:00
253777fdc3
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
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function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
llvm-svn: 185026
2013-06-26 22:23:32 +00:00
59bfaf774b
[mips] DSP-ASE move from HI/LO register instructions.
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llvm-svn: 179739
2013-04-18 00:52:44 +00:00
334c7bc7eb
Use object file specific section type for initial text section
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llvm-svn: 179494
2013-04-14 21:18:36 +00:00
2a74a87b71
This is a resubmittal. For some reason it broke the bots yesterday
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but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
llvm-svn: 172685
2013-01-17 00:28:20 +00:00
5619f91bf7
reverting 172579
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llvm-svn: 172594
2013-01-16 01:29:10 +00:00
e0c1e1a47e
Akira,
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Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
llvm-svn: 172579
2013-01-16 00:07:45 +00:00
0c4468b5e6
Remove DOS line endings.
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llvm-svn: 167968
2012-11-14 20:18:34 +00:00
d0836fd20a
[mips] Fix disassembler test cases.
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llvm-svn: 167326
2012-11-02 22:20:10 +00:00
a13cd0666e
Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.
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Patch by Vladimir Medic.
llvm-svn: 160143
2012-07-12 21:19:32 +00:00
9bf2b5677d
Reapply r158846.
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Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
llvm-svn: 159953
2012-07-09 18:46:47 +00:00
b577ff116d
revert r159851.
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llvm-svn: 159854
2012-07-06 20:16:48 +00:00
cfa35fa0ff
Reapply r158846.
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Include file MipsGenRegisterInfo.inc.
llvm-svn: 159851
2012-07-06 19:29:11 +00:00
87505f46ac
Revert r158846.
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llvm-svn: 158855
2012-06-20 21:19:39 +00:00
da448fe0b1
In MipsDisassembler.cpp, instead of defining register class tables, use the ones
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that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
llvm-svn: 158846
2012-06-20 20:39:23 +00:00
c13ed945aa
Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
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llvm-svn: 157725
2012-05-31 00:49:56 +00:00
71928e681b
Add disassembler to MIPS.
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Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
d19f025374
Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler.
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llvm-svn: 153926
2012-04-03 03:01:13 +00:00
55059262aa
Revert r153924. There were buildbot failures.
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llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
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Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
Zoran Jovanovic