Commit Graph

7 Commits

Author SHA1 Message Date
Guillaume Chatelet 12ca74e5f0 [llvm-exegesis] Fix broken build bots.
Reviewers: javed.absar

Subscribers: tschuett, courbet, llvm-commits

Differential Revision: https://reviews.llvm.org/D52302

llvm-svn: 342646
2018-09-20 13:37:04 +00:00
Guillaume Chatelet c96a97bac7 [llvm-exegesis] Improve Register Setup (roll forward of D51856).
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.

Reviewers: courbet, javed.absar

Subscribers: llvm-commits, tschuett, mgorny

Differential Revision: https://reviews.llvm.org/D52297

llvm-svn: 342644
2018-09-20 12:22:18 +00:00
Simon Pilgrim 0242689725 Revert rL342466: [llvm-exegesis] Improve Register Setup.
rL342465 is breaking the MSVC buildbots, but I need to revert this dependent revision as well.

Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.

Reviewers: courbet, javed.absar

Subscribers: mgorny, tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D51856

llvm-svn: 342489
2018-09-18 15:35:49 +00:00
Guillaume Chatelet 937f3fedec [llvm-exegesis] Improve Register Setup.
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.

Reviewers: courbet, javed.absar

Subscribers: mgorny, tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D51856

llvm-svn: 342466
2018-09-18 11:26:48 +00:00
Guillaume Chatelet 5ad2909e52 Improve Register Setup
llvm-svn: 342464
2018-09-18 11:26:27 +00:00
John Brawn b371ccc661 [llvm-exegesis] Adjust AArch64 unit test
The signature of setRegToConstant changed in r336171, so adjust the AArch64
unit test in a similar way to how the X86 unit test was changed in that commit.

llvm-svn: 336188
2018-07-03 10:52:20 +00:00
John Brawn c4ed60042f [llvm-exegesis] Add an AArch64 target
The target does just enough to be able to run llvm-exegesis in latency mode for
at least some opcodes.

Differential Revision: https://reviews.llvm.org/D48780

llvm-svn: 336187
2018-07-03 10:10:29 +00:00