Running the ARM instruction emulation test on a big-endian system
would fail, since the code doesn't respect endianness properly.
In EmulateInstructionARM::TestEmulation, code assumes that an
instruction opcode read in from the test file is in target byte
order, but it was in fact read in in host byte order.
More difficult to fix, the EmulationStateARM structure models
the overlapping sregs and dregs by a union in _sd_regs. This
only works correctly if the host is a little-endian system.
I've removed the union in favor of a simple array containing
the 32 sregs, and changed any code accessing dregs to explicitly
use the correct two sregs overlaying that dreg in the proper
target order.
Also, the EmulationStateARM::ReadPseudoMemory and WritePseudoMemory
track memory as a map of uint32_t values in host byte order, and
implement 64-bit memory accessing by splitting them up into two
uint32_t ones. However, callers expect memory contents to be
provided in the form of a byte array (in target byte order).
This means the uint32_t contents need to be byte-swapped on
BE systems, and when splitting up a 64-bit access into two 32-bit
ones, byte order has to be respected.
Differential Revision: http://reviews.llvm.org/D18984
llvm-svn: 266314
in thumb mode into one method in ArchSpec, replace checks for
specific cores in the disassembler with calls to this. Also call
this from the arm instruction emulation code.
The determination of whether a given ArchSpec is thumb-only is still
a bit of a hack, but at least the hack is consolidated into a single
place. In my original version of this patch http://reviews.llvm.org/D13578
I was calling into llvm's feature arm feature tables to make this
determination, like
#include "llvm/Support/TargetRegistry.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/../../lib/Target/ARM/ARMGenRegisterInfo.inc"
#include "llvm/../../lib/Target/ARM/ARMFeatures.h"
[...]
std::string triple (GetTriple().getTriple());
const char *cpu = "";
const char *features_str = "";
const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple.c_str(), Error);
std::unique_ptr<llvm::MCSubtargetInfo> subtarget_info_up (curr_target->createMCSubtargetInfo(triple.c_str(), cpu, features_str));
if (subtarget_info_up->getFeatureBits()[llvm::ARM::FeatureNoARM])
{
return true;
}
but those tables are post-llvm-build generated and linking against them
for all of our different build system methods was a big hiccup that I
haven't had time to revisit convincingly.
I'll keep that reviews.llvm.org patch around to remind myself that I
need to take another run at linking against the necessary tables
again in llvm.
<rdar://problem/23022803>
llvm-svn: 265377
The IT instruction can specify condition code for up to 4 consecutive
instruction and it is used quite often by clang in epilogues causing
an issue when trying to unwind from locations covered by the IT
instruction and for locatins inmediately after the IT instruction.
Changes made to fix it:
* Introduce the concept of conditional instruction block what is a list
of consecutive instructions with the same condition. We update the
unwind information during the conditional instruction block and when
we reach the end of it (first instruction with a differemt condition)
then we restore the unwind information we had before the condition.
* Fix a bug in the ARM instruction emulator where neither PC nor the
ITSTATE was advanced when we reached an instruction what we can't
decode.
After the change we have no regression on android-arm running the
regular test suit and TestStandardUnwind also passes when running it
with clang as the compiler (previously it failed on an IT instruction).
Differential revision: http://reviews.llvm.org/D16814
llvm-svn: 260368
The ARM instruction emulator had 2 bugs related to the handling of the
IT instruction causing an error in single stepping:
* We haven't initialized the IT mask from the CPSR so if the last
instruction of the IT block is a branch and the condition is false
then the emulator evaluated the branch what resulted in an incorrect
pc for the next instruction.
* The ITSTATE was advanced before the execution of each instruction. As
a result the emulator was using the condition of following instruction
in every case. The ITSTATE should be edvanced after the execution of
an instruction except after an IT instruction.
Differential revision: http://reviews.llvm.org/D16772
llvm-svn: 259509
The incorrect instruction emulation caused issues in the stack unwinding
code when strd was used to push 2 register to the stack with writeback.
llvm-svn: 256000
in places where we check for Triple::IOS. They're mostly the same as far
as lldb is conerned.
.
Also add a base cass implementation for Process::IsAlive - Greg added this
last year but it didn't get upstreamed.
llvm-svn: 252227
It is a new function added to the llvm::Triple class to simplify the
checking if we are targeting android to clean up the confusion between
android being an OS or an environment.
llvm-svn: 250286
Change the way EmulateInstruction::eContextPopRegisterOffStack handled
in UnwindAssemblyInstEmulation::WriteRegister to accomodate for
additional cases when eContextPopRegisterOffStack (pop PC/FLAGS).
llvm-svn: 245690
On ARM there is no difference petween a pop and a load instruction so
a register can be loaded multiple times during the function. Add check
to threat the load as a restore only if it do the restore from the
same location where the register was saved.
Differential revision: http://reviews.llvm.org/D11947
llvm-svn: 245546
Don't chane the CFI information when a conditional instruction
is emulated (eg.: popeq {r0, pc}) because the CFI for the next
instruction should be the same as the CFI for the current instruction.
Differential revision: http://reviews.llvm.org/D11258
llvm-svn: 242519
* Add and fix the emulation of several instruction.
* Disable frame pointer usage on Android.
* Specify return address register for the unwind plan instead of explict
tracking the value of RA.
* Replace prologue detection heuristics (unreliable in several cases)
with a logic to follow the branch instructions and restore the CFI
value based on them. The target address for a branch should have the
same CFI as the source address (if they are in the same function).
* Handle symbols in ELF files where the symbol size is not specified
with calcualting their size based on the next symbol (already done
in MachO files).
* Fix architecture in FuncUnwinders with filling up the inforamtion
missing from the object file with the architecture of the target.
* Add code to read register wehn the value is set to "IsSame" as it
meanse the value of a register in the parent frame is the same as the
value in the current frame.
Differential revision: http://reviews.llvm.org/D10447
llvm-svn: 240533
The condition detection code is calculating the result of the condition
based on the first 3 bit of the condition and then negate it if the LSB
of the condition is set. It works for the normal conditions but 0b1110
and 0b1111 are special as both of them should evaluate to true
independently the value of CPSR. This CL removes the negating logic from
those cases.
Differential revision: http://reviews.llvm.org/D9219
llvm-svn: 235715
In the previous ordering some "blx <label>" instruction was recognised
as "b #imm24" instructions causing a failure in the instruction
emulator.
Differential revision: http://reviews.llvm.org/D9218
llvm-svn: 235714
Write the new cpsr value into the cpsr register if the BL or the BLX
instruction change the instruction set on arm.
Differential revision: http://reviews.llvm.org/D9188
llvm-svn: 235585
Summary:
This change refactors UnwindPlan::Row to be able to store the fact that the CFA is value is set
by evaluating a dwarf expression (DW_CFA_def_cfa_expression). This is achieved by creating a new
class CFAValue and moving all CFA setting/getting code there. Note that code using the new
CFAValue::isDWARFExpression is not yet present and will be added in a follow-up patch. Therefore,
this patch should not change the functionality in any way.
Test Plan: Ran tests on Mac and Linux. No regressions detected.
Reviewers: jasonmolenda, clayborg
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D7755
llvm-svn: 230210
Replace adhoc inline implementation of llvm::array_lengthof in favour of the
implementation in LLVM. This is simply a cleanup change, no functional change
intended.
llvm-svn: 211868
and EmulateInstructionARM::GetFramePointerDWARFRegisterNumber to recognize
the Apple arm convention (of using r7 for the frame pointer, regardless of
thumb or arm) even if the OS does not match Darwin/MacOSX/iOS. Also
corrects the behavior for thumb code on non-Apple platforms.
<rdar://problem/14661537>
llvm-svn: 198648
Previously, an opcode set via SetOpcode32 (for example) was later
extracted via GetData() as a byte sequence in host order rather than
target order.
Review: http://llvm-reviews.chandlerc.com/D1838
llvm-svn: 196808
<rdar://problem/13594769>
Main changes in this patch include:
- cleanup plug-in interface and use ConstStrings for plug-in names
- Modfiied the BSD Archive plug-in to be able to pick out the correct .o file when .a files contain multiple .o files with the same name by using the timestamp
- Modified SymbolFileDWARFDebugMap to properly verify the timestamp on .o files it loads to ensure we don't load updated .o files and cause problems when debugging
The plug-in interface changes:
Modified the lldb_private::PluginInterface class that all plug-ins inherit from:
Changed:
virtual const char * GetPluginName() = 0;
To:
virtual ConstString GetPluginName() = 0;
Removed:
virtual const char * GetShortPluginName() = 0;
- Fixed up all plug-in to adhere to the new interface and to return lldb_private::ConstString values for the plug-in names.
- Fixed all plug-ins to return simple names with no prefixes. Some plug-ins had prefixes and most ones didn't, so now they all don't have prefixed names, just simple names like "linux", "gdb-remote", etc.
llvm-svn: 181631
Full UnwindPlan is trying to do an impossible unwind; in that case
invalidate the Full UnwindPlan and replace it with the architecture
default unwind plan.
This is a scenario that happens occasionally with arm unwinds in
particular; the instruction analysis based full unwindplan can
mis-parse the functions and the stack walk stops prematurely. Now
we can do a simpleminded frame-chain walk to find the caller frame
and continue the unwind. It's not ideal but given the complicated
nature of analyzing the arm functions, and the lack of eh_frame
information on iOS, it is a distinct improvement and fixes some
long-standing problems with the unwinder on that platform.
This is fixing <rdar://problem/12091421>. I may re-use this
invalidate feature in the future if I can identify other cases where
the full unwindplan's unwind information is clearly incorrect.
This checkin also includes some cleanup for the volatile register
definition in the arm ABI plugin for <rdar://problem/10652166>
although work remains to be done for that bug.
llvm-svn: 166757
- no setting auto completion
- very manual and error prone way of getting/setting variables
- tons of code duplication
- useless instance names for processes, threads
Now settings can easily be defined like option values. The new settings makes use of the "OptionValue" classes so we can re-use the option value code that we use to set settings in command options. No more instances, just "does the right thing".
llvm-svn: 162366
a shared pointer to ease some memory management issues with a patch
I'm working on.
The main complication with using SPs for these objects is that most
methods that build up an UnwindPlan will construct a Row to a given
instruction point in a function, then add additional regsaves in
the next instruction point to that row and push it again. A little
care is needed to not mutate the previous instruction point's Row
once these are switched to being held behing shared pointers.
llvm-svn: 160214
Switch over to the "*-apple-macosx" for desktop and "*-apple-ios" for iOS triples.
Also make the selection process for auto selecting platforms based off of an arch much better.
llvm-svn: 156354
For EmulateInstructionARM::EmulatePUSH(), fix the logical branch for when pc is pushed to behave
like the other cases where:
context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
is called to inform of the operation to set a register value to a memory location calculated from
a base register plus an offset.
llvm-svn: 152670
For the default case (illegal encoding type), just return false instead of break.
A8.6.84 LDRSH (register)
A8.6.309 VLD1 (single element to all lanes)
llvm-svn: 137699
Ulrich Weigand