Commit Graph

25370 Commits

Author SHA1 Message Date
Richard Sandiford be133a8757 [SystemZ] Extend memcmp support to all constant lengths
This uses the infrastructure added for memcpy and memmove in r189331.

llvm-svn: 189458
2013-08-28 09:01:51 +00:00
Alexey Samsonov a3a037df63 Fix use of uninitialized value added in r189400 (found by MemorySanitizer)
llvm-svn: 189456
2013-08-28 08:30:47 +00:00
Eric Christopher 62caa709fe Remove support for the .debug_inlined section. No known software
in use supports it.

llvm-svn: 189439
2013-08-28 04:04:28 +00:00
NAKAMURA Takumi 19675898da X86JITInfo.cpp: Apply x64 version of X86CompilationCallback() to Cygwin64.
For now, (defined(X86_64_JIT) && defined(__CYGWIN__)) satisfies Cygwin64.

llvm-svn: 189437
2013-08-28 03:04:09 +00:00
NAKAMURA Takumi 9ea7c6d463 X86Subtarget.h: Recognize x86_64-cygwin.
In the LLVM side, x86_64-cygwin is almost as same as x86_64-mingw32.

llvm-svn: 189436
2013-08-28 03:04:02 +00:00
Akira Hatanaka 9bfa2e2e7f [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.

llvm-svn: 189432
2013-08-28 00:55:15 +00:00
Akira Hatanaka 37e9b0dbb2 [mips] Clean up definitions of move word from/to coprocessor instructions.
No functionality change.

llvm-svn: 189431
2013-08-28 00:42:50 +00:00
Akira Hatanaka 62005d69a7 [mips] Set isAllocatable and CoveredBySubRegs.
llvm-svn: 189430
2013-08-28 00:34:17 +00:00
David Majnemer aa34d79ab5 [ms-inline asm] Support offsets after segment registers
Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'

Reviewers: craig.topper, rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1470

llvm-svn: 189407
2013-08-27 21:56:17 +00:00
Joerg Sonnenberger b822af4721 Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.

llvm-svn: 189400
2013-08-27 20:23:19 +00:00
Jack Carter 4e07b95daf Changed comment
llvm-svn: 189396
2013-08-27 19:45:28 +00:00
Joey Gouly e6d165ccb4 [ARMv8] Add MC support for the new load/store acquire/release instructions.
llvm-svn: 189388
2013-08-27 17:38:16 +00:00
Elena Demikhovsky 93eeb47d49 AVX-512: added conversion instructions.
llvm-svn: 189349
2013-08-27 13:54:04 +00:00
Joey Gouly a710d810f5 [ARMv8] Add some negative tests for the recent VFP/NEON instructions.
Fix two issues I found while writing these tests.

llvm-svn: 189341
2013-08-27 11:24:16 +00:00
Tim Northover 449d390f40 ARM: add natural patterns for vaddhl and vsubhl.
These instructions aren't particularly complicated and it's well worth having
patterns for some reasonably useful LLVM IR that will match them. Soon we
should be able to switch Clang over to producing this natural version.

llvm-svn: 189335
2013-08-27 10:31:36 +00:00
Daniel Sanders b8bce4d935 [mips][msa] Added spill/reload support
llvm-svn: 189332
2013-08-27 10:04:21 +00:00
Richard Sandiford 5e318f0bfe [SystemZ] Extend memcpy and memset support to all constant lengths
Lengths up to a certain threshold (currently 6 * 256) use a series of MVCs.
Lengths above that threshold use a loop to handle X*256 bytes followed
by a single MVC to handle the excess (if any).  This loop will also be
needed in future when support for variable lengths is added.

Because the same tablegen classes are used to define MVC and CLC,
the patch also has the side-effect of defining a pseudo loop instruction
for CLC.  That instruction isn't used yet (and wouldn't be handled correctly
if it were).  I'm planning to use it soon though.

llvm-svn: 189331
2013-08-27 09:54:29 +00:00
Daniel Sanders 70835f6025 [mips][msa] Added bitconverts for vector types for big and little-endian
llvm-svn: 189330
2013-08-27 09:40:30 +00:00
Elena Demikhovsky 12f24673e0 AVX-512: Added FMA instructions.
llvm-svn: 189326
2013-08-27 08:39:25 +00:00
Charles Davis 1827bd8a6c Revert "Fix the build broken by r189315." and "Move everything depending on Object/MachOFormat.h over to Support/MachO.h."
This reverts commits r189319 and r189315. r189315 broke some tests on what I
believe are big-endian platforms.

llvm-svn: 189321
2013-08-27 05:38:30 +00:00
Charles Davis 0c6f71b40d Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
llvm-svn: 189315
2013-08-27 05:00:43 +00:00
Jim Grosbach 667b147dba ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

llvm-svn: 189274
2013-08-26 20:22:05 +00:00
Bill Schmidt 8c3976eca1 Dummy code to silence warning from 4189266
llvm-svn: 189272
2013-08-26 20:11:46 +00:00
Jim Grosbach 5f71aab12e ARM: FastISel verifier error cleanup.
Constant pool and global value reference instructions need more
restricted register classes than plain GPR.

rdar://12594152

llvm-svn: 189270
2013-08-26 20:07:29 +00:00
Jim Grosbach 08aa534239 ARM: Fix ELF global base reg intialization.
The create machine code wasn't properly in SSA, which the machine verifier
properly complains about. Now that fast-isel is closer to verifier clean,
errors like this show up more clearly.

Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb
mode functions, which is obviously wrong. Fix that along the way.

Test case is part of the following commit which will finish making an
additional fast-isel test verifier clean an enable it for the
regression test suite. This commit is separate since its not just
a verifier cleanup, but an actual correctness issue.

rdar://12594152 (for the fast-isel verifier aspects)

llvm-svn: 189269
2013-08-26 20:07:25 +00:00
Bill Schmidt d89f678cfd [PowerPC] More fast-isel chunks (returns and integer extends)
Incremental improvement to fast-isel for PPC64.  This allows us to
select on ret, sext, and zext.  Filling in sext/zext improves some of
the existing logic in handling compare-immediates that needed extends.

A simplified return convention for fast-isel is also added to the
PPC64 calling conventions.  All call/return processing for DAG
selection is handled with custom code, so there isn't an existing CC
to rely on here.  The include of PPCGenCallingConv.inc causes compiler
warnings due to the 32-bit calling conventions that are not used, so
the dummy function "usePPC32CCs()" is added here to silence those.

Test cases for the return and extend logic are added.

llvm-svn: 189266
2013-08-26 19:42:51 +00:00
Tom Stellard 35bb18c2a7 R600: Add support for vector local memory loads
llvm-svn: 189226
2013-08-26 15:06:04 +00:00
Tom Stellard c6f4a29ed5 R600: Add support for i8 and i16 local memory loads
llvm-svn: 189225
2013-08-26 15:05:59 +00:00
Tom Stellard f3d166aa1e R600: Add support for i8 and i16 local memory stores
llvm-svn: 189223
2013-08-26 15:05:49 +00:00
Tom Stellard 2ffc330673 R600: Add support for v4i32 and v2i32 local stores
llvm-svn: 189222
2013-08-26 15:05:44 +00:00
Tom Stellard fd155828ed SelectionDAG: Use correct pointer size when lowering function arguments v2
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes.  The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.

This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.

v2:
  - Add more helper functions to TargetLoweringBase
  - Use CHECK-LABEL for tests

llvm-svn: 189221
2013-08-26 15:05:36 +00:00
Elena Demikhovsky 0a2b6290f1 AVX-512: Added shuffle instructions -
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.

llvm-svn: 189215
2013-08-26 12:45:35 +00:00
Vladimir Medic 8277c1874a This patch implements trap instructions for mips. The test cases are added.
llvm-svn: 189213
2013-08-26 10:02:40 +00:00
Craig Topper 6269f49505 Make sure x86 instructions using ssmem/sdmem operand types are only able to parse memory operands of the proper size in Intel syntax. Primarily affects some of sse cvt instructions.
llvm-svn: 189206
2013-08-26 00:39:04 +00:00
Craig Topper 5500d83793 Remove some unnecessary PredicateMethod overrides. Add RenderMethod overrides to remove forwarding in the X86AsmParser code itself. No functional change.
llvm-svn: 189205
2013-08-26 00:13:09 +00:00
Craig Topper 8c26c424c6 Put some of the AVX-512 parsing stuff in a more consistent place with the existing functions.
llvm-svn: 189204
2013-08-25 23:18:05 +00:00
Bill Schmidt 0300813d6a [PowerPC] Add fast-isel branch and compare selection.
First chunk of actual fast-isel selection code.  This handles direct
and indirect branches, as well as feeding compares for direct
branches.  PPCFastISel::PPCEmitIntExt() is just roughed in and will be
expanded in a future patch.  This also corrects a problem with
selection for constant pool entries in JIT mode or with small code
model.

llvm-svn: 189202
2013-08-25 22:33:42 +00:00
Craig Topper 1885417372 First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.

Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.

llvm-svn: 189201
2013-08-25 22:23:38 +00:00
Venkatraman Govindaraju 35e0c382d5 [Sparc] Add long double (f128) instructions to sparc backend.
llvm-svn: 189198
2013-08-25 18:30:06 +00:00
Venkatraman Govindaraju 12d8089b8e [Sparc] Added V9's extra floating point registers and their aliases.
llvm-svn: 189195
2013-08-25 17:03:02 +00:00
Elena Demikhovsky f8f478b19d AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors
llvm-svn: 189189
2013-08-25 12:54:30 +00:00
Reed Kotler 7d0fb7ebd5 Start to add the LLVM builtins to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted

Resubmit this patch. The target triple needs to be added to the test so that 
clang does not tell the backend the wrong target when the host is BSD. There
is a clang bug in here somewhere that I need to track down. At Mips this
has been filed internally as a bug.

llvm-svn: 189186
2013-08-25 02:40:25 +00:00
Craig Topper 0714d51cba Add hasSideEffects/mayLoad/mayStore flags to the X86 moffs8/moffs16/moffs32/moffs64 versions of move.
llvm-svn: 189182
2013-08-24 20:31:14 +00:00
Craig Topper 092e2fe426 Remove trailing whitespace.
llvm-svn: 189178
2013-08-24 19:50:11 +00:00
Shuxin Yang b64ab41936 Revert 189161
llvm-svn: 189176
2013-08-24 17:53:16 +00:00
Reed Kotler e531cbaa86 Start to add the builtind to the mips16 exclusion lists for fp.
I need to add the rest of these to the list or else to delay putting
out the actual stub until later in code generation when I know if
the external function ever got emitted.

llvm-svn: 189161
2013-08-24 01:24:44 +00:00
Justin Holewinski aaa8b6e355 [NVPTX] Re-enable assembly printing support for inline assembly
This support was removed by accident during the MC conversion

llvm-svn: 189160
2013-08-24 01:17:23 +00:00
Rafael Espindola 94a2c5642d Rename features to match what gcc and clang use.
There is no advantage in being different and using the same names simplifies
clang a bit.

llvm-svn: 189141
2013-08-23 20:21:34 +00:00
Jim Cownie b09bb1ce19 Checking commit access; added one space
llvm-svn: 189111
2013-08-23 15:51:37 +00:00
Joey Gouly c7cda1c59e [ARM] Fix another ARM FastISel -verify-machineinstrs issue.
llvm-svn: 189109
2013-08-23 15:20:56 +00:00