The old approach (dedicated ExecXXX for each instruction) is not flexible and results in duplicated code when RVC kicks in.
According to the spec, every compressed instruction can be decoded to a non-compressed one. So we can lower compressed instructions to instructions we already had, which requires a decoupling between the decoder and executor.
This patch:
- use llvm::Optional and its combinators AMAP.
- use template constraints on common instruction.
- make instructions strongly-typed (no uint32_t everywhere bc it is error-prone and burdens the developer when lowering the RVC) with the help of algebraic datatype (std::variant).
Note:
(NFC) because this is more of a refactoring in preparation for RVC.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D135015
We have some 500 ish uses of the bool plus ref version
so changing them all at once isn't a great idea.
This adds an overload that doesn't take a RegisterInfo&
and returns an optional.
Once I'm done switching all the existing callers I'll
remove the original function.
Benefits of optional over bool plus ref:
* The intent of the function is clear from the prototype.
* It's harder to forget to check if the return is valid,
and if you do you'll get an assert.
* You don't hide ununsed variables, which happens because
passing by ref marks a variable used.
* You can't forget to reset the RegisterInfo in between
calls.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D134536
Add:
- most of instructions from RVI base instructions set.
- some instruction decode tests from objdump.
Further work:
- implement riscv imac extension.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D132789
This patch fixes:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h:34:5:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
and:
lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:194:21:
error: comparison of integers of different signs: 'int' and 'size_t'
(aka 'unsigned long') [-Werror,-Wsign-compare]
Add:
- `EmulateInstructionRISCV`, which can be used for riscv32 and riscv64.
- Add unittests for EmulateInstructionRISCV.
Note: Compressed instructions set (RVC) was still not supported in this patch.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D131759
Emmmer