Commit Graph

116 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 6a8cfe9a72 [Hexagon] Use shifts by scalar for funnel shifts by scalar
HVX has vector shifts by a scalar register. Use those in the expansions
of funnel shifts where profitable.
2022-10-18 09:49:17 -07:00
Krzysztof Parzyszek 9fde8e907b [Hexagon] Fix MULHS lowering for HVX v60
The carry bit from an intermediate addition was not properly propagated.
For example mulhs(7fffffff, 7fffffff) was evaluated as 3ffeffff, while
the correct result is 3fffffff.
2022-10-18 07:54:38 -07:00
Krzysztof Parzyszek 705e77abed [Hexagon] Lower funnel shifts for HVX
HVX v62+ has bidirectional shifts, which do not mask the shift amount to
the bit width. Instead, the shift amount is sign-extended from the log(BW)
bit value, and a negative value causes a shift in the other direction.
For the shift amount being -log(BW), this reversed shift will shift all
bits out, inserting 0s or sign bits depending on the type and direction.
2022-10-14 14:13:18 -07:00
Krzysztof Parzyszek 7f4ce3f1eb [Hexagon] Introduce PS_vsplat[ir][bhw] pseudo instructions
HVX v60 only has splats that take a 32-bit word as input, while v62+
has splats that take 8- or 16-bit value. This makes writing output
patterns that need to use a splat annoying, because the entire output
pattern needs to be replicated for various versions of HVX.
To avoid this, the patterns will always use the pseudos, and then the
pseudos will be handled using a post-ISel hook.
2022-10-14 12:03:13 -07:00
Fangrui Song 8805e5d1b7 [Hexagon] Fix -Wunused-variable in non-assertion builds after f6e7ad5604 2022-09-21 14:14:45 -07:00
Krzysztof Parzyszek f6e7ad5604 [Hexagon] Revamp type legalization of ext/trunc/sat in HVX
Resizing operations (e.g. sign extension) in DAG can go from any width
to any other width, e.g. i8 -> i32. If the input and the result differ
by a factor larger than 2, the operation cannot be legal in HVX, since
the only two legal vector sizes in HVX are a single vector and a pair
of vectors.
To simplify the legalization, such operations are expanded into steps
that only double/halve the type size, so that each such step can be fully
legalized on its own. The complication is that DAG will automatically
fold these steps back into one, e.g. sext(sext) -> sext. To prevent that
new HexagonISD nodes are introduced: TL_EXTEND and TL_TRUNCATE. Once
legalized, these nodes are replaced with the original opcodes.

The type legalization is now common to aext/sext/zext/trunc and Hexagon-
specific ssat/usat nodes.
2022-09-21 11:25:27 -07:00
Simon Pilgrim 0015edeefd Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI. 2022-09-20 14:24:07 +01:00
Simon Pilgrim 70582bc4d3 Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warnings. NFCI. 2022-09-20 10:35:32 +01:00
Haojian Wu eec19987c0 Fix one more unused warning in release build, NFC 2022-09-19 20:56:39 +02:00
Haojian Wu 20822e2d42 Fix an unused warning in release build, NFC 2022-09-19 20:45:51 +02:00
Krzysztof Parzyszek 94a71361d6 [Hexagon] Implement [SU]INT_TO_FP and FP_TO_[SU]INT for HVX 2022-09-19 11:11:20 -07:00
Krzysztof Parzyszek ec51e38062 [Hexagon] Add HVX patterns for ISD::ABS 2022-09-19 10:12:15 -07:00
Krzysztof Parzyszek 3eee45cdc8 [Hexagon] Rework SplitHvxPairOp to be a general vector splitting utiity
Enable creating an idiom: V -> opJoin(SplitVectorOp(V))
2022-09-19 09:42:13 -07:00
Krzysztof Parzyszek e5844462f6 [Hexagon] Use proper output chain when widening HVX loads 2022-09-19 09:04:13 -07:00
Shao-Ce SUN 662b9fa02c [NFC][CodeGen] Add a setTargetDAGCombine use ArrayRef
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D122557
2022-03-29 09:53:24 +08:00
Krzysztof Parzyszek 0792161c00 [Hexagon] Fix operation actions for v128f16
There were more cases of operations that should have been "Custom" for
v128f16, but ended up "Legal" (e.g. load and store).
2022-02-08 15:28:37 -08:00
Krzysztof Parzyszek 7403c02f06 [Hexagon] Fix crash with shuffle_vector of v128f16 2022-02-08 13:05:22 -08:00
Mikael Holmen e2078d56ed [Hexagon] Fix warning about unused variable when compiling without asserts 2022-01-05 08:35:16 +01:00
Krzysztof Parzyszek 78f5014fea [Hexagon] Conversions to/from FP types, HVX and scalar
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
Co-authored-by: Sumanth Gundapaneni <sgundapa@quicinc.com>
2022-01-04 11:03:51 -08:00
Krzysztof Parzyszek db83e3e507 [Hexagon] Generate HVX/FP arithmetic instructions
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
Co-authored-by: Sumanth Gundapaneni <sgundapa@quicinc.com>
Co-authored-by: Joshua Herrera <joshherr@quicinc.com>
2021-12-30 12:47:30 -08:00
Krzysztof Parzyszek 9e6afbedb0 [Hexagon] Generate HVX/FP compare instructions
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
2021-12-30 12:17:22 -08:00
Krzysztof Parzyszek eb574259b6 [Hexagon] Handle HVX/FP {masked,wide} loads/stores
Co-authored-by: Rahul Utkoor <quic_rutkoor@quicinc.com>
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
2021-12-30 10:14:00 -08:00
Krzysztof Parzyszek 23423638cc [Hexagon] Handle HVX/FP shuffles, insertion and extraction
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
2021-12-30 08:44:10 -08:00
Krzysztof Parzyszek 95c7dd8810 Revert "[Hexagon] Don't build two halves of HVX vector in parallel"
This reverts commit ba07f300c6.

A build-vector sequence is made of pairs: rotate+insert. When constructing
a single vector, this results in a chain of 2*N instructions. The rotate
operation is a permute operation, but the insert uses a multiplication
resource: insert and rotate can execute in the same cycle, but obviously
they cannot operate on the same vector. The original halving idea is still
beneficial since it does allow for insert/rotate overlap, and for hiding
insert's latency.
2021-12-30 07:57:11 -08:00
Krzysztof Parzyszek ba07f300c6 [Hexagon] Don't build two halves of HVX vector in parallel
There can only be one permute operations per packet, so this actually
pessimizes the code (due to the extra "or").
2021-12-29 11:00:01 -08:00
Joshua Herrera 505d57486e [Hexagon] Improve BUILD_VECTOR codegen
For vectors with repeating values, old codegen would rotate and insert
every duplicate element. This patch replaces that behavior with a splat
of the most common element, vinsert/vror only occur when needed.
2021-12-29 10:18:21 -08:00
Krzysztof Parzyszek 4df2aba294 [Hexagon] Calling conventions for floating point vectors
They are the same as for the other HVX vectors, but types need to be
listed explicitly. Also, add a detailed codegen testcase.

Co-authored-by: Abhikrant Sharma <quic_abhikran@quicinc.com>
2021-12-29 09:01:07 -08:00
Krzysztof Parzyszek 2ce586bc49 [Hexagon] Handle floating point splats
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
2021-12-29 06:52:24 -08:00
Krzysztof Parzyszek 6a6ac3b36f [Hexagon] Support BUILD_VECTOR of floating point HVX vectors
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
Co-authored-by: Ankit Aggarwal <aankit@quicinc.com>
2021-12-28 14:59:08 -08:00
David Green 32b6c17b29 [SDAG] Use UnknownSize for masked load/store MMO size
A masked load or store will load a potentially unknown number of bytes
from a memory location - that is not generally known at compile time.
They do not necessarily load/store the entire vector width, and treating
them as such can lead to incorrect aliasing information (for example, if
the underlying object is smaller than the size of the vector).

This makes sure that the MMO is given an unknown size to represent this.
which is less accurate that "may load/store from up to 16 bytes", but
less incorrect that "will load/store from 16 bytes".

Differential Revision: https://reviews.llvm.org/D113888
2021-11-23 09:47:56 +00:00
Ankit Aggarwal a72763af67 [Hexagon] Handle bitcast of i64/i128 -> v64i1/v128i1 2021-09-13 18:52:30 -05:00
Craig Topper 9af8f1b18e [SelectionDAG] Add isZero/isAllOnes methods to ConstantSDNode.
Soft deprecrate isNullValue/isAllOnesValue and update in tree
callers. This matches the changes to the APInt interface from
D109483.

Reviewed By: lattner

Differential Revision: https://reviews.llvm.org/D109535
2021-09-09 13:28:30 -07:00
Krzysztof Parzyszek 280678122d [Hexagon] Avoid infinite loops in type legalization when lowering SETCC
Only widen SETCC if the operands can be widened. Not checking that caused
infinite widen-split loops in legalization.
2021-04-15 13:34:37 -05:00
Kazu Hirata 054444177b [Target] Use llvm::append_range (NFC) 2021-01-24 12:18:56 -08:00
Kazu Hirata e4847a7fcf Revert "[Target] Use llvm::append_range (NFC)"
This reverts commit cc7a238286.

The X86WinEHState.cpp hunk seems to break certain builds.
2021-01-23 11:25:27 -08:00
Kazu Hirata cc7a238286 [Target] Use llvm::append_range (NFC) 2021-01-23 10:56:31 -08:00
Krzysztof Parzyszek a2e6506c47 [Hexagon] Improve legalizing of ISD::SETCC result 2021-01-13 12:29:22 -06:00
Krzysztof Parzyszek a90214760d [Hexagon] Custom-widen SETCC's operands
The result cannot be widened, unfortunately, because widening vNi1
would depend on the context in which it appears (i.e. the type alone
is not sufficient to tell if it needs to be widened).
2021-01-11 12:21:49 -06:00
Kazu Hirata 913515e465 [Target] Use llvm::is_contained (NFC) 2020-12-13 19:35:10 -08:00
Simon Pilgrim c4628460b7 [Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns
Followup to D92112 now that I've learnt about HVX type splitting.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.

Differential Revision: https://reviews.llvm.org/D92169
2020-11-27 15:46:11 +00:00
Krzysztof Parzyszek 1b5baa42bc [Hexagon] Handle selection between HVX vector predicates
Make sure that (select i1 q0 q1) is handled properly.
2020-10-23 18:22:03 -05:00
Krzysztof Parzyszek 9237e73ae8 [Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR
This removes VSPLAT and VZERO. VZERO is now SPLAT_VECTOR of (i32 0).

Included is also a testcase for the previous (target-independent)
commit.
2020-10-10 19:49:47 -05:00
Krzysztof Parzyszek 6fd994b4b7 [Hexagon] Remove ISD node VSPLATW, use VSPLAT instead
This is a step towards improving HVX codegen for splat.
2020-10-09 15:38:02 -05:00
Krzysztof Parzyszek f528816d58 [Hexagon] Move selection of HVX multiply from lowering to patterns
Also, change i32*i32 to V6_vmpyieoh + V6_vmpyiewuh_acc, which works
on V60 as well.
2020-10-02 16:04:34 -05:00
David Sherwood b8ce6a6756 [SVE][CodeGen] Add new EVT/MVT getFixedSizeInBits() functions
When we know that a particular type is always going to be fixed
width we have so far been writing code like this:

  getSizeInBits().getFixedSize()

Since we are doing this in quite a few places now it seems to make
sense to add a new helper function that allows us to replace
these calls with a single getFixedSizeInBits() call.

Differential Revision: https://reviews.llvm.org/D88649
2020-10-02 07:47:31 +01:00
Krzysztof Parzyszek 3185839bcf [Hexagon] Avoid crash on CONCAT_VECTORS with illegal element types
Legal vector element types may not be legal as scalar types. When
CONCAT_VECTORS is converted to BUILD_VECTOR, the individual vector
elements become standalone operands to the build operation. If they
have illegal (scalar) types, they need to be made legal. In doing
so, the case of TRUNCATE was not handled, causing an assertion to
fail.
2020-09-24 20:05:23 -05:00
Krzysztof Parzyszek bb877d1af2 [Hexagon] Widen loads and handle any-/sign-/zero-extensions 2020-09-14 18:10:23 -05:00
Krzysztof Parzyszek 6352381039 [Hexagon] Some HVX DAG combines
1. VINSERTW0 x, undef -> x
2. VROR (VROR x, a), b) -> VROR x, a+b
2020-09-14 18:10:23 -05:00
Krzysztof Parzyszek 9d300bc8d2 [Hexagon] Avoid widening vectors with non-HVX element types 2020-09-12 20:26:54 -05:00
Krzysztof Parzyszek 783e28a508 [Hexagon] Split pair-based masked memops 2020-09-10 14:24:42 -05:00