Commit Graph

3 Commits

Author SHA1 Message Date
ZHU Zijia d51581ff2c [RISCV][TableGen] Mark MachineInstr with FrameIndex as not compressible
If a MachineInstr's operand should be Reg in compiler's output but is
currently FrameIndex, `isCompressibleInst()` will terminate at
`MachineOperandType::getReg()`.

This patch adds `.isReg()` checks to make `isCompressibleInst()` return
false for these MachineInstr, allowing `getInstSizeInBytes()` to return
a value and `EstimateFunctionSizeInBytes()` to work as intended.

See https://reviews.llvm.org/D129999#3694222 for details.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D129999
2022-08-24 13:23:38 +08:00
serge-sans-paille 2dde5c9734 Cleanup llvm/utils/TableGen headers
Based on the output of include-what-you-use.
It's an utility directory, so no much impact on other code areas.

clang++ -E  -Iinclude -I../llvm/include ../llvm/utils/TableGen/*.cpp -std=c++14 -fno-rtti -fno-exceptions | wc -l
before: 4327274
after:  4316190

Related discourse thread: https://llvm.discourse.group/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D118466
2022-01-31 11:16:28 +01:00
Zi Xuan Wu 24d1673c8b [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
Not only RISCV but also other target such as CSKY, there are compressed instructions mixed with normal instructions.
To reuse the basic infra to compress/uncompress and predict instruction, we need reconstruct the RISCVCompressInstEmitter
and make it more general and suitable for other target.

Differential Revision: https://reviews.llvm.org/D113475
2021-11-18 11:14:27 +08:00