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3 Commits

Author SHA1 Message Date
dfukalov 6e8251046b [AMDGPU] Fix bug introduced in 47a5c36b37 
Summary: [AMDGPU] Fix bug introduced in 47a5c36b37

Reviewers: foad, arsenm

Reviewed By: arsenm

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69915
 2019-11-07 11:50:14 +03:00
dfukalov 47a5c36b37 [AMDGPU] Improve code size cost model (part 2) 
Summary: Added estimations for ShuffleVector, some cast and arithmetic instructions

Reviewers: rampitec

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, zzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69629
 2019-11-06 13:55:48 +03:00
Matt Arsenault 3c5e4237c6 AMDGPU: Make some packed shuffles free 
VOP3P instructions can encode access to either
half of the register.

llvm-svn: 302730
 2017-05-10 21:29:33 +00:00