Commit Graph

3 Commits

Author SHA1 Message Date
Sanjay Patel f24900b934 [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates
The transform performs a bitwise logic op in a wider type followed by
truncate when both inputs are truncated from the same source type:
logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)

There are a bunch of other checks that should prevent doing this when 
it might be harmful.

We already do this transform for scalars in this spot. The vector 
limitation was shared with a check for the case when the operands are 
extended. I'm not sure if that limit is needed either, but that would 
be a separate patch.

Differential Revision: https://reviews.llvm.org/D55448

llvm-svn: 349303
2018-12-16 14:57:04 +00:00
Krzysztof Parzyszek 840b02bccf [Hexagon] Add patterns for accumulating HVX compares
llvm-svn: 333009
2018-05-22 18:27:02 +00:00
Krzysztof Parzyszek e8a0ae7346 [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns
llvm-svn: 332525
2018-05-16 21:00:24 +00:00