69f1d7e370
[Hexagon] Handle lowering of SETCC via setCondCodeAction
...
It was expanded directly into instructions earlier. That was to avoid
loads from a constant pool for a vector negation: "xor x, splat(i1 -1)".
Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of
all true and all false values, and handle setcc with negations through
selection patterns.
llvm-svn: 324348
2018-02-06 14:16:52 +00:00
02947b7112
[Hexagon] Use V6_vmpyih for halfword multiplication
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Unlike V6_vmpyhv, it produces the result in the exact form that is
expected without the need for a shuffle.
llvm-svn: 324241
2018-02-05 15:40:06 +00:00
1108ee2496
[Hexagon] Implement HVX codegen for vector shifts
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llvm-svn: 323914
2018-01-31 20:49:24 +00:00
9eb085e6cf
[Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering
...
llvm-svn: 323912
2018-01-31 20:48:11 +00:00
b843f75179
[Hexagon] Handle SETCC on vector pairs in lowering
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llvm-svn: 323911
2018-01-31 20:46:55 +00:00
82a83391d3
[Hexagon] Handle BUILD_VECTOR from undef values in buildHvxVectorReg
...
llvm-svn: 323889
2018-01-31 16:52:15 +00:00
8cc636c592
[Hexagon] Only process bitcasts of vsplats when selecting const vectors
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Selecting of constant HVX vectors involves some "manual processing",
which mishandled an unrelated BITCAST operation causing a selection
error.
llvm-svn: 323887
2018-01-31 16:48:20 +00:00
90ca4e8b0c
[Hexagon] Generate constant splats instead of loads from constant pool
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llvm-svn: 323568
2018-01-26 21:54:56 +00:00
cf3ad5841b
[Hexagon] Run late copy propagation and dead code elimination passes
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llvm-svn: 323346
2018-01-24 17:48:11 +00:00
d5e8a260bb
[Hexagon] Add patterns for sext_inreg of HVX vector types
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llvm-svn: 323250
2018-01-23 19:56:16 +00:00
3780a0e1fa
[Hexagon] Implement basic vector operations on vectors vNi1
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In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.
llvm-svn: 323229
2018-01-23 17:53:59 +00:00
4ef6cfff6a
[Hexagon] Cast elements to correct type when creating constant vector
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llvm-svn: 322301
2018-01-11 18:03:23 +00:00
b0b52618c0
[Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors
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Recommit r321897 with updated testcases.
llvm-svn: 321908
2018-01-05 22:31:11 +00:00
4ed8ef6f8e
Revert r321894: it requires a part of another commit that is not ready yet
...
Commit message:
[Hexagon] Add patterns for sext_inreg of HVX vector types
llvm-svn: 321904
2018-01-05 21:57:43 +00:00
f9d01a12d1
[Hexagon] Add patterns for truncating HVX vector types
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Only non-bool vectors.
llvm-svn: 321895
2018-01-05 20:48:03 +00:00
9d0c6355a0
[Hexagon] Add patterns for sext_inreg of HVX vector types
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llvm-svn: 321894
2018-01-05 20:46:41 +00:00
cfe4a3616f
[Hexagon] Fix generation of vector sign extensions
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llvm-svn: 321650
2018-01-02 15:28:49 +00:00
e4ce92cabf
[Hexagon] Allow construction of HVX vector predicates
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Handle BUILD_VECTOR of boolean values.
llvm-svn: 321220
2017-12-20 20:49:43 +00:00
e704583f23
[Hexagon] Cache loads to select to avoid traversing mutating DAG
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llvm-svn: 321034
2017-12-18 23:13:27 +00:00
6b589e593d
[Hexagon] Generate HVX code for vector sign-, zero- and any-extends
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Implement any-extend as zero-extend.
llvm-svn: 321004
2017-12-18 18:32:27 +00:00
266d6f03a1
[Hexagon] Handle concat_vectors of all allowed HVX types
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llvm-svn: 320865
2017-12-15 21:23:12 +00:00
470760533a
[Hexagon] Generate HVX code for comparisons and selects
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llvm-svn: 320744
2017-12-14 21:28:48 +00:00
2eda05db87
[Hexagon] Relax some checks in testcases, NFC
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llvm-svn: 320529
2017-12-12 21:44:04 +00:00
edcd9dcbc4
[Hexagon] Better detection of identity and undef masks in shuffles
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llvm-svn: 320523
2017-12-12 20:23:12 +00:00
40a605f1be
[Hexagon] Fix wrong order of operands for vmux
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Shuffle generation uses vmux to collapse vectors resulting from two
individual shuffles into one. The indexes of the elements selected
from the first operand were indicated by 0xFF in the constant vector
used in the compare instruction, but the compare (veqb) set the bits
corresponding to the 0x00 elements, thus inverting the selection.
Reverse the order of operands to vmux to get the correct output.
llvm-svn: 320516
2017-12-12 19:32:41 +00:00
152414595b
[Hexagon] Crash in instruction selection for insert_vector_elt for HVX
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A wrong type was passed to insertVector, causing an out-of-bounds value
to be added an an operand to HexagonISD::INSERT. This later failed in
instruction selection.
llvm-svn: 320369
2017-12-11 14:46:06 +00:00
039d4d9286
[Hexagon] Generate HVX code for basic arithmetic operations
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Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.
llvm-svn: 320063
2017-12-07 17:37:28 +00:00
d2967868be
[Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specifically
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llvm-svn: 319978
2017-12-06 22:41:49 +00:00
64533cf630
[Hexagon] Handle perfect shuffles on single vectors
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llvm-svn: 319965
2017-12-06 21:25:03 +00:00
7d37dd8902
[Hexagon] Generate HVX code for vector construction and access
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Support for:
- build vector,
- extract vector element, subvector,
- insert vector element, subvector,
- shuffle.
llvm-svn: 319901
2017-12-06 16:40:37 +00:00
Krzysztof Parzyszek