llvm-project

Commit Graph

Author	SHA1	Message	Date
Craig Topper	a0ebac52df	[X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode. In 16-bit mode we can encode a 32-bit address using 0x67 prefix. We were failing to do this when the index register was a 32-bit register, the base register was not present, and the displacement fit in 16-bits. Fixes PR46866.	2020-07-27 21:11:42 -07:00
Nirav Dave	6477ce2697	Add support for Code16GCC [X86] The .code16gcc directive parses X86 assembly input in 32-bit mode and outputs in 16-bit mode. Teach parser to switch modes appropriately. Reviewers: dwmw2, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20109 llvm-svn: 282430	2016-09-26 19:33:36 +00:00

Author

SHA1

Message

Date

Craig Topper

a0ebac52df

[X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode.

In 16-bit mode we can encode a 32-bit address using 0x67 prefix.
We were failing to do this when the index register was a 32-bit
register, the base register was not present, and the displacement
fit in 16-bits.

Fixes PR46866.

2020-07-27 21:11:42 -07:00

Nirav Dave

6477ce2697

Add support for Code16GCC

[X86] The .code16gcc directive parses X86 assembly input in 32-bit mode and
outputs in 16-bit mode. Teach parser to switch modes appropriately.

Reviewers: dwmw2, craig.topper

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20109

llvm-svn: 282430

2016-09-26 19:33:36 +00:00

2 Commits