6 Commits

Author	SHA1	Message	Date
Reid Kleckner	39970069b1	[X86][AsmParser] Treat '%' as the modulo operator under Intel syntax ... It can't be a register prefix, anyway. This is consistent with the masm docs on MSDN: https://msdn.microsoft.com/en-us/library/t4ax90d2.aspx This is a straight-forward extension of our support for "MOD" implemented in https://reviews.llvm.org/D33876 / r306425 llvm-svn: 317011	2017-10-31 16:47:38 +00:00
Coby Tayree	41a5b55f50	[X86][AsmParser][MS-compatability] Binary/Unary operators enhancements ... Introducing MOD binary operator https://msdn.microsoft.com/en-us/library/hha180wt.aspx Enhancing unary operators NEG and NOT, to support more complex patterns Differential Revision: https://reviews.llvm.org/D33876 llvm-svn: 306425	2017-06-27 16:58:27 +00:00
Coby Tayree	2cb497afa4	[X86][MS-compatability]Allow named synonymous for MS-assembly operators ... This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability MASM reference: https://msdn.microsoft.com/en-us/library/94b6khh4.aspx Differential Revision: D31277 llvm-svn: 299439	2017-04-04 14:43:23 +00:00
Michael Kuperstein	e3de07a529	Add support for parsing the XOR operator in Intel syntax inline assembly. ... Differential Revision: http://reviews.llvm.org/D10385 Patch by marina.yatsina@intel.com llvm-svn: 239695	2015-06-14 12:59:45 +00:00
Kevin Enderby	d6b107136a	Update the X86 assembler for .intel_syntax to accept ... the << and >> bitwise operators. rdar://15975725 llvm-svn: 200896	2014-02-06 01:21:15 +00:00
Kevin Enderby	2e13b1c7f1	Update the X86 assembler for .intel_syntax to accept ... the | and & bitwise operators. rdar://15570412 llvm-svn: 199323	2014-01-15 19:05:24 +00:00