3 Commits

Author	SHA1	Message	Date
Sanjay Patel	5d67d81f48	[InstCombine] prevent crashing/assert on shift constant expression (PR44028) ... The binary operator cast implies an instruction, but the matcher for shift does not: https://bugs.llvm.org/show_bug.cgi?id=44028	2019-11-17 17:31:09 -05:00
Sanjay Patel	d9ccb6367a	[InstCombine] canonicalize shift+logic+shift to reduce dependency chain ... shift (logic (shift X, C0), Y), C1 --> logic (shift X, C0+C1), (shift Y, C1) This is an IR translation of an existing SDAG transform added here: rL370617 So we again have 9 possible patterns with a commuted IR variant of each pattern: https://rise4fun.com/Alive/VlI https://rise4fun.com/Alive/n1m https://rise4fun.com/Alive/1Vn Part of the motivation is to allow easier recognition and subsequent canonicalization of bswap patterns as discussed in PR43146: https://bugs.llvm.org/show_bug.cgi?id=43146 We had to delay this transform because it used to allow the SLP vectorizer to create awful reductions out of simple load-combines. That problem was fixed with: rL375025 (we'll bring back load combining in IR someday...) The backend is also better equipped to deal with these patterns now using hooks like TLI.getShiftAmountThreshold(). The only remaining potential controversy is that the -reassociate pass tends to reverse this kind of pattern (to help GVN?). But since -reassociate doesn't do anything with these specific patterns, there is no conflict currently. Finally, there's a new pass proposal at D67383 for general tree-height-reduction reassociation, and it could use a cost model to decide how to optimally rearrange these kinds of ops for a target. That patch appears to be stalled. Differential Revision: https://reviews.llvm.org/D69842	2019-11-07 12:09:45 -05:00
Sanjay Patel	3ce0c78501	[InstCombine] add tests for shift-logic-shift; NFC ... This is based on existing CodeGen test files for x86 and AArch64. The corresponding potential transform is shown in: rL370617	2019-11-05 08:18:50 -05:00