llvm-project

Commit Graph

Author	SHA1	Message	Date
Tom Stellard	cc4c8718ed	[AMDGPU] Rename $dst operand to $vdst for VOP instructions. Summary: This change renames output operand for VOP instructions from dst to vdst. This is needed to enable decoding named operands for disassembler. Reviewers: vpykhtin, tstellarAMD, arsenm Subscribers: arsenm, llvm-commits, nhaustov Projects: #llvm-amdgpu-spb Differential Revision: http://reviews.llvm.org/D16920 llvm-svn: 260986	2016-02-16 18:14:56 +00:00
Matt Arsenault	3add6439d0	AMDGPU: Add MachineInstr overloads for instruction format tests llvm-svn: 250797	2015-10-20 04:35:43 +00:00
Matt Arsenault	e0b44040aa	AMDGPU: Simplify debug printing llvm-svn: 247345	2015-09-10 21:51:19 +00:00
Matt Arsenault	4635915504	AMDGPU/SI: Remove VCCReg llvm-svn: 244380	2015-08-08 00:41:48 +00:00
Matt Arsenault	6942d1a034	AMDGPU/SI: Remove source uses of VCCReg llvm-svn: 244379	2015-08-08 00:41:45 +00:00
Tom Stellard	e48fe2a27a	AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11061 llvm-svn: 242146	2015-07-14 14:15:03 +00:00
Tom Stellard	db5a11f698	AMDGPU/SI: Select mad patterns to v_mac_f32 The two-address instruction pass will convert these back to v_mad_f32 if necessary. Differential Revision: http://reviews.llvm.org/D11060 llvm-svn: 242038	2015-07-13 15:47:57 +00:00
Tom Stellard	ab6e9c0f94	AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use This is convered by existing testcases and will be exposed by a future commit. llvm-svn: 241817	2015-07-09 16:30:36 +00:00
Tom Stellard	45bb48ea19	R600 -> AMDGPU rename llvm-svn: 239657	2015-06-13 03:28:10 +00:00

9 Commits