llvm-project

Commit Graph

Author	SHA1	Message	Date
Zi Xuan Wu (Zeson)	08db089124	[CSKY] Fix the testcase error due to the verifyInstructionPredicates - Test cases for arch only has 16-bit instruction such as ck801/ck802 need compile with -mattr=+btst16 - Fix the GPR copy instruction with MOV16 for 16-bit only arch.	2022-07-21 15:53:50 +08:00
Zi Xuan Wu	a190fcdfcc	[CSKY] Add inline asm constraints and related codegen support There are kinds of inline asm constraints and corresponding register class or register as following. 'b': mGPRRegClass 'v': sGPRRegClass 'w': sFPR32RegClass or sFPR64RegClass 'c': C register 'z': R14 register 'h': HI register 'l': LO register 'y': HI or LO register It also adds codegen test for inline-asm including constraints, clobbers and abi names.	2022-02-07 17:45:37 +08:00

Author

SHA1

Message

Date

Zi Xuan Wu (Zeson)

08db089124

[CSKY] Fix the testcase error due to the verifyInstructionPredicates

- Test cases for arch only has 16-bit instruction such as ck801/ck802 need
compile with -mattr=+btst16
- Fix the GPR copy instruction with MOV16 for 16-bit only arch.

2022-07-21 15:53:50 +08:00

Zi Xuan Wu

a190fcdfcc

[CSKY] Add inline asm constraints and related codegen support

There are kinds of inline asm constraints and corresponding register class or register as following.

 'b': mGPRRegClass
 'v': sGPRRegClass
 'w': sFPR32RegClass or sFPR64RegClass
 'c': C register
 'z': R14 register
 'h': HI register
 'l': LO register
 'y': HI or LO register

It also adds codegen test for inline-asm including constraints, clobbers and abi names.

2022-02-07 17:45:37 +08:00

2 Commits