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2021 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky 485c539391 [AMDGPU][MC][GFX11] Disable non-null src0 for s_waitcnt_*cnt 
Differential Revision: https://reviews.llvm.org/D134809
 2022-09-29 19:56:03 +03:00
Jay Foad 3822a01e0b [AMDGPU] Add GFX11 ds_bvh_stack_rtn_b32 instruction 
Differential Revision: https://reviews.llvm.org/D133928
 2022-09-15 16:46:14 +01:00
Dmitry Preobrazhensky 405b19bb67 [AMDGPU][MC][GFX11] Add disassembler tests for v_readfirstlane_b32 
Differential Revision: https://reviews.llvm.org/D133437
 2022-09-15 18:18:33 +03:00
Dmitry Preobrazhensky b0eea8f440 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for MIMG instructions 
Differential Revision: https://reviews.llvm.org/D133411
 2022-09-15 18:04:34 +03:00
Antonio Frighetto c63e05dc07 [AArch64InstPrinter] Introduce register markup tags emission 
AArch64 assembly syntax emission now leverages markup tags for registers, if enabled.

Reviewed By: MaskRay, david-arm

Differential Revision: https://reviews.llvm.org/D129870
 2022-09-13 20:52:02 -07:00
Dmitry Preobrazhensky 6d63a531e2 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPD instructions 
Differential Revision: https://reviews.llvm.org/D133414
 2022-09-09 13:10:55 +03:00
Dmitry Preobrazhensky c07ea46f21 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3P instructions 
Differential Revision: https://reviews.llvm.org/D133412
 2022-09-09 13:06:44 +03:00
Dmitry Preobrazhensky efa65ef281 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3 instructions 
Differential Revision: https://reviews.llvm.org/D133350
 2022-09-07 13:55:27 +03:00
Dmitry Preobrazhensky a95b45d380 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP8 instructions 
Differential Revision: https://reviews.llvm.org/D133353
 2022-09-07 13:51:31 +03:00
Dmitry Preobrazhensky c777c8f022 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP16 instructions 
Differential Revision: https://reviews.llvm.org/D133356
 2022-09-07 13:47:55 +03:00
Fangrui Song 1b726f0a4c [AArch64InstPrinter] Add some `<reg:...>` for llvm-mc --mdis output 2022-09-01 21:34:56 -07:00
Antonio Frighetto f0c50447f6 [X86InstPrinter] Introduce markup tags emission 
x86 assembly syntax emission now leverages markup tags, if enabled.

Differential Revision: https://reviews.llvm.org/D129869
 2022-09-01 21:04:35 -07:00
Antonio Frighetto 4e99079774 [AArch64InstPrinter] Introduce immediate markup tags emission 
AArch64 assembly syntax emission now leverages markup tags for immediates, if enabled.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D129871
 2022-09-01 20:58:42 -07:00
Antonio Frighetto cbb2141f7f [MipsInstPrinter] Introduce markup tags emission 
MIPS assembly syntax emission now leverages markup tags, if enabled.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D129867
 2022-09-01 20:52:09 -07:00
Dmitry Preobrazhensky 67d148b63c [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPC and VOPC.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132737
 2022-08-26 21:38:55 +03:00
Dmitry Preobrazhensky 35e2107842 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP2 and VOP2.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132733
 2022-08-26 21:32:55 +03:00
Dmitry Preobrazhensky ad39f1fa8c [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP1 and VOP1.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132731
 2022-08-26 21:30:08 +03:00
Dmitry Preobrazhensky 8ff3cea076 [AMDGPU][MC][GFX11][NFC] Add missing tests for SOP instructions 
Differential Revision: https://reviews.llvm.org/D132404
 2022-08-24 13:45:20 +03:00
Dmitry Preobrazhensky 5e7d43ffef [AMDGPU][MC][GFX11][NFC] Update tests for FLAT instructions 
Differential Revision: https://reviews.llvm.org/D132402
 2022-08-24 13:38:09 +03:00
Dmitry Preobrazhensky badf8aed30 [AMDGPU][MC][NFC] Rename disassembler tests 
Make test names more uniform.

Differential Revision: https://reviews.llvm.org/D132472
 2022-08-24 13:26:57 +03:00
Dmitry Preobrazhensky 8f3c160b8b [AMDGPU][MC][GFX8][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132469
 2022-08-24 13:13:22 +03:00
Dmitry Preobrazhensky 4b9016da0a [AMDGPU][MC][GFX9][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132409
 2022-08-23 13:13:36 +03:00
Dmitry Preobrazhensky 0a8dd8ef79 [AMDGPU][MC][GFX10][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132235
 2022-08-22 19:53:56 +03:00
Dmitry Preobrazhensky e99f6df726 [AMDGPU][MC][GFX9][NFC] Split large test file 
Split gfx9_dasm_all.txt by instruction encoding.

Differential Revision: https://reviews.llvm.org/D132124
 2022-08-19 14:01:42 +03:00
Dmitry Preobrazhensky bdb859c9a7 [AMDGPU][MC][GFX8][NFC] Split large test file 
Split gfx8_dasm_all.txt by instruction encoding.

Differential Revision: https://reviews.llvm.org/D132126
 2022-08-19 13:54:56 +03:00
Dmitry Preobrazhensky 7e29d5c04b [AMDGPU][MC][GFX10][NFC] Split large test 
Split gfx10_dasm_all.txt by encoding.

Differential Revision: https://reviews.llvm.org/D132044
 2022-08-18 12:39:34 +03:00
Dmitry Preobrazhensky 4e68834add [AMDGPU][MC][GFX11][NFC] Add tests for VOP1 and VOP2 16 bit opcodes 
Differential Revision: https://reviews.llvm.org/D131588
 2022-08-11 17:12:13 +03:00
Dmitry Preobrazhensky eda6e49aa8 [AMDGPU][MC][GFX11][NFC] Correct tests for 16-bit VOP2 opcodes which use v128 or higher VGPRs 
Differential Revision: https://reviews.llvm.org/D131564
 2022-08-11 15:55:58 +03:00
Dmitry Preobrazhensky 9d1eeefbfe [AMDGPU][MC][GFX11][NFC] Rename tests 
Make test names more uniform.

Differential Revision: https://reviews.llvm.org/D131398
 2022-08-09 13:56:05 +03:00
Dmitry Preobrazhensky fc4c1a86f3 [AMDGPU][MC][GFX11][NFC] Split large tests 
Differential Revision: https://reviews.llvm.org/D131397
 2022-08-09 13:24:23 +03:00
Sheng 64d326c33c [M68k] Add MC support for link/unlk 
Reviewers: myhsu

Differential Revision: https://reviews.llvm.org/D125444
 2022-08-08 11:00:11 +08:00
Dmitry Preobrazhensky 05b3aadfff [AMDGPU][MC][GFX11] Correct v_dot2_f16_f16 and v_dot2_bf16_bf16 
Enable SGPRs for the following operands of these opcodes:

- src operands of VOP3 variant.
- src2 operand of DPP variants.

Differential Revision: https://reviews.llvm.org/D130989
 2022-08-03 15:08:23 +03:00
Dmitry Preobrazhensky ae553f9e49 [AMDGPU][MC][GFX10] Correct encoding of VOP3 v_cmpx* opcodes 
Encode dst=EXEC but allow disassembler accept any dst value.

Differential Revision: https://reviews.llvm.org/D130978
 2022-08-03 15:03:44 +03:00
Dmitry Preobrazhensky bb901dcc5a [AMDGPU][MC][GFX940] Correct disassembly of MFMA opcodes 
Add a decoder table for GFX940 MFMA opcodes.

Differential Revision: https://reviews.llvm.org/D130759
 2022-08-01 16:00:47 +03:00
Petar Avramovic e8d260753e [AMDGPU] gfx11 allow dlc for MUBUF atomics 
Add MC support for dlc in gfx11 MUBUF atomic instructions.

Differential Revision: https://reviews.llvm.org/D129075
 2022-08-01 12:18:01 +02:00
Mirko Brkusanin 6a1aa627fa [AMDGPU] Enable image_gather4h instruction for gfx10 and gfx11 
Differential Revision: https://reviews.llvm.org/D130764
 2022-07-29 15:42:06 +02:00
Dmitry Preobrazhensky 0eb9f18520 [AMDGPU][MC][GFX11] Correct encoding of VOP3/VOP3_DPP v_cmpx* opcodes 
Encode dst=EXEC but allow disassembler accept any dst value.

Differential Revision: https://reviews.llvm.org/D130345
 2022-07-26 17:36:22 +03:00
Simon Tatham ae16b2ed98 [llvm-objdump,ARM] Fix a lot more tests. 
When I changed the output format of llvm-objdump for Arm and AArch64
in D130358, I hadn't realised llvm-objdump was used so much in the
plain MC tests as well as tests of itself and lld. Sorry!
 2022-07-26 10:22:02 +01:00
Petar Avramovic 8de1f04c77 [AMDGPU] gfx11 Fix VOP3 dot instructions 
Fix src modifiers for operands with bf16 type.
op_sel[0:1] are ignored.

Differential Revision: https://reviews.llvm.org/D129084
 2022-07-22 11:43:35 +02:00
Stanislav Mekhanoshin 523a99c0eb [AMDGPU] Support for gfx940 fp8 smfmac 
Differential Revision: https://reviews.llvm.org/D129908
 2022-07-18 12:12:41 -07:00
Stanislav Mekhanoshin 2695f0a688 [AMDGPU] Support for gfx940 fp8 mfma 
Differential Revision: https://reviews.llvm.org/D129906
 2022-07-18 11:49:56 -07:00
Stanislav Mekhanoshin 9fa5a6b7e8 [AMDGPU] Support for gfx940 fp8 conversions 
Differential Revision: https://reviews.llvm.org/D129902
 2022-07-18 11:48:43 -07:00
Dmitry Preobrazhensky 2a6532d542 [AMDGPU][MC][GFX11] Correct disassembly of *_e64_dpp opcodes which support op_sel 
These opcodes cannot be disassembled because op_sel operand is missing - it must be added manually.
See https://github.com/llvm/llvm-project/issues/56512 for detailed issue analysis.

Differential Revision: https://reviews.llvm.org/D129637
 2022-07-15 13:11:59 +03:00
Paul Robinson 08e4fe6c61 [X86] Add RDPRU instruction 
Add support for the RDPRU instruction on Zen2 processors.

User-facing features:

- Clang option -m[no-]rdpru to enable/disable the feature
- Support is implicit for znver2/znver3 processors
- Preprocessor symbol __RDPRU__ to indicate support
- Header rdpruintrin.h to define intrinsics
- "rdpru" mnemonic supported for assembler code

Internal features:

- Clang builtin __builtin_ia32_rdpru
- IR intrinsic @llvm.x86.rdpru

Differential Revision: https://reviews.llvm.org/D128934
 2022-07-06 07:17:47 -07:00
David Spickett 20741c74c5 [llvm][AArch64] Fix "+all" feature for sysreg aliases 
For example the predres extension adds one instruction that
is a sys alias. Previously this wasn't disassembled properly
with "+all".

This was because a check for "+all" was added to haveFeatures
in AArch64SysReg but not in SysAlias.

Reviewed By: MaskRay, lenary

Differential Revision: https://reviews.llvm.org/D129147
 2022-07-06 08:41:53 +00:00
Fangrui Song 45f3a5aae7 [AArch64] Add target feature "all" 
This is used by disassemblers: `llvm-mc -disassemble -mattr=` and `llvm-objdump --mattr=`.
The main use case is for llvm-objdump to disassemble all known instructions
(D128030).

In user-facing tools, "all" is intentionally not supported in producers:
integrated assembler (`.arch_extension all`), clang -march (`-march=armv9.3a+all`).
Due to the code structure, `llvm-mc -mattr=+all` `llc -mattr=+all` are not
rejected (they are internal tool). Add `llvm/test/CodeGen/AArch64/mattr-all.ll`
to catch behavior changes.

AArch64SysReg::SysReg::haveFeatures: check `FeatureAll` to print
`AArch64SysReg::SysReg::AltName` for some system registers (e.g. `ERRIDR_EL1, RNDR`).

AArch64.td: add `AssemblerPredicateWithAll` to additionally test `FeatureAll`.
Change all `AssemblerPredicate` (except `UseNegativeImmediates`) to `AssemblerPredicateWithAll`.

utils/TableGen/{DecoderEmitter,SubtargetFeatureInfo}.cpp: support arbitrarily
nested all_of, any_of, and not.

Note: A predicate supports all_of, any_of, and not. For a target (though
currently not for AArch64) an encoding may be disassembled differently with
different target features.
Note: AArch64MCCodeEmitter::computeAvailableFeatures is not available to
the disassembler.

Reviewed By: peter.smith, lenary

Differential Revision: https://reviews.llvm.org/D128029
 2022-06-30 10:37:58 -07:00
Piotr Sobczak 4874838a63 [AMDGPU] gfx11 WMMA instruction support 
gfx11 introduces new WMMA (Wave Matrix Multiply-accumulate)
instructions.

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D128756
 2022-06-30 11:13:45 -04:00
Joe Nash 07b7fada73 [AMDGPU] gfx11 VOPD instructions MC support 
VOPD is a new encoding for dual-issue instructions for use in wave32.
This patch includes MC layer support only.

A VOPD instruction is constituted of an X component (for which there are
13 possible opcodes) and a Y component (for which there are the 13 X
opcodes plus 3 more). Most of the complexity in defining and parsing
a VOPD operation arises from the possible different total numbers of
operands and deferred parsing of certain operands depending on the
constituent X and Y opcodes.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D128218
 2022-06-24 11:08:39 -04:00
Dmitry Preobrazhensky dcb24f93af [AMDGPU][MC][GFX11] Correct disassembly of VOP3.DPP8 opcodes 
Fix bug #56163.
Add W32/W64 tests for all VOP3.DPP opcodes.

Differential Revision: https://reviews.llvm.org/D128369
 2022-06-23 13:07:45 +03:00
Dmitry Preobrazhensky 485e8b4f63 [AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes 
Fix bugs https://github.com/llvm/llvm-project/issues/56091, https://github.com/llvm/llvm-project/issues/56065.

Differential Revision: https://reviews.llvm.org/D128075
 2022-06-20 14:23:07 +03:00