d5cfca1e3d
Nuke dead isCodeGenOnly annotation and extraneous comment.
...
llvm-svn: 120338
2010-11-29 22:40:58 +00:00
1883d94630
tidy up.
...
llvm-svn: 120335
2010-11-29 22:38:48 +00:00
7ec3d34553
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
...
instructions. This simplifies instruction printing and disassembly.
llvm-svn: 120333
2010-11-29 22:37:40 +00:00
81af4f9eb1
Rename t2 TBB and TBH instructions to reference that they encode the jump table
...
data. Next up, pseudo-izing them.
llvm-svn: 120320
2010-11-29 21:28:32 +00:00
ba3a8fa7ab
Improving the factoring of several instruction encodings.
...
llvm-svn: 120317
2010-11-29 20:38:48 +00:00
e9608b3f01
Thumb2 encodings for MSR and MRS.
...
llvm-svn: 120309
2010-11-29 19:29:15 +00:00
2fdf32fa2c
Thumb2 encodings for system instructions.
...
llvm-svn: 120307
2010-11-29 19:22:08 +00:00
b044bc67f4
Thumb2 encodings for branches and IT blocks.
...
llvm-svn: 120306
2010-11-29 18:54:38 +00:00
2bb49e15a6
Remove trailing whitespace.
...
llvm-svn: 119806
2010-11-19 17:11:02 +00:00
336021f758
Fix decoding ambiguities of stdrex and ldrex.
...
llvm-svn: 119801
2010-11-19 13:11:50 +00:00
0eb2994626
Fix an obvious oversight.
...
llvm-svn: 119792
2010-11-19 06:15:10 +00:00
f53e4d9fd1
Provide Thumb2 encodings for strex and ldrex.
...
llvm-svn: 119768
2010-11-19 00:28:38 +00:00
3517585249
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
...
llvm-svn: 119755
2010-11-18 23:29:56 +00:00
10839cb62c
Provide Thumb2 encodings for mov's that come from MOVCC SDNodes.
...
llvm-svn: 119744
2010-11-18 21:46:31 +00:00
3fec5ff14b
More Thumb2 encodings.
...
llvm-svn: 119737
2010-11-18 21:15:19 +00:00
3625098459
Fill out the set of Thumb2 multiplication operator encodings.
...
llvm-svn: 119733
2010-11-18 20:32:18 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
d127e7174b
Try again at providing Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119601
2010-11-18 01:08:42 +00:00
28883834e1
Revert r119593 while I figure out my testing disagrees with the buildbot.
...
llvm-svn: 119597
2010-11-18 00:42:51 +00:00
64aaddcd64
Provide correct Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119593
2010-11-18 00:19:10 +00:00
55425e7f78
Second attempt at correct encodings for Thumb2 bitfield instructions.
...
llvm-svn: 119575
2010-11-17 22:16:31 +00:00
6c37ceb182
Revert r119551, which broke buildbots.
...
llvm-svn: 119555
2010-11-17 20:48:51 +00:00
7464116bde
Provide Thumb2 encodings for bitfield instructions.
...
llvm-svn: 119551
2010-11-17 20:35:29 +00:00
7f8ab6ee8b
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
bced7ae046
More miscellaneous Thumb2 encodings.
...
llvm-svn: 119546
2010-11-17 19:57:38 +00:00
a8974af320
Use the correct variable names so that the encodings will be correct.
...
llvm-svn: 119403
2010-11-16 23:44:49 +00:00
5aa33ca29d
L_bit doesn't work here.
...
llvm-svn: 119325
2010-11-16 02:20:22 +00:00
3bd60eff26
- Remove dead patterns.
...
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
llvm-svn: 119323
2010-11-16 02:08:45 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
05a8daee21
Add Thumb2 encodings for mov and friends.
...
llvm-svn: 119295
2010-11-16 00:29:56 +00:00
ea96321781
Attempt to provide encodings for some miscellaneous Thumb2 encodings.
...
llvm-svn: 119187
2010-11-15 21:30:39 +00:00
7d97a99f4c
Provide Thumb2 encodings for sxtb and friends.
...
llvm-svn: 119185
2010-11-15 21:12:05 +00:00
2a3c22efba
Add Thumb2 encodings for comparison and shift operators.
...
llvm-svn: 119176
2010-11-15 19:58:36 +00:00
0e7d728327
Add correct Thumb2 encodings for mvn and friends.
...
llvm-svn: 119170
2010-11-15 18:45:17 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
e0f6b41618
Second attempt at providing correct encodings for Thumb2 binary operators.
...
llvm-svn: 119029
2010-11-14 05:37:38 +00:00
9430eb489c
Comment out the defms until they're activated.
...
llvm-svn: 119000
2010-11-13 11:20:05 +00:00
705ec77ab5
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
...
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
c4c642832d
Convert the modes to lower case.
...
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
e69afc6bb7
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
79ff5238e9
Conditional moves are slightly more expensive than moves.
...
llvm-svn: 118985
2010-11-13 05:14:20 +00:00
2bcb8daa44
Add conditional move of large immediate.
...
llvm-svn: 118968
2010-11-13 02:25:14 +00:00
7cd724ae7d
Revert r118939 while I work out why it broke some buildbots.
...
llvm-svn: 118942
2010-11-12 23:36:03 +00:00
0003a296ad
Attemt to provide correct encodings for Thumb2 binary operators.
...
llvm-svn: 118939
2010-11-12 23:18:11 +00:00
0fc8084a64
Add conditional mvn instructions.
...
llvm-svn: 118935
2010-11-12 22:42:47 +00:00
8fdd172502
First stab at providing correct Thumb2 encodings, start with adc.
...
llvm-svn: 118924
2010-11-12 21:12:40 +00:00
21acf9fb38
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
...
llvm-svn: 118237
2010-11-04 05:19:35 +00:00
8740ee3637
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
...
llvm-svn: 118160
2010-11-03 06:34:55 +00:00
6f36042557
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
...
llvm-svn: 118152
2010-11-03 05:14:24 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
...
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
5b373341fc
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
...
patterns as such
llvm-svn: 117923
2010-11-01 15:59:52 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
...
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
33fc3e095b
reapply r117858 with apparent editor malfunction fixed (somehow I
...
got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
e59eef3dd1
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
7ed597149b
Overhaul memory barriers in the ARM backend. Radar 8601999.
...
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
llvm-svn: 117756
2010-10-30 00:54:37 +00:00
069f38d1bf
Remove hard tab characters.
...
llvm-svn: 117742
2010-10-29 23:23:15 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
...
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
...
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
e6fe1a03c7
imm12 operands aren't Thumb2 only, so rename the printer helper function.
...
llvm-svn: 117291
2010-10-25 20:00:01 +00:00
3b1db392fc
Remove unused ARMISD::AND selection DAG node.
...
llvm-svn: 116566
2010-10-15 04:34:40 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
340cd5174b
A few 80 column fixes.
...
llvm-svn: 116451
2010-10-13 23:34:31 +00:00
5b255c2dd6
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
24ab1ce8c2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
fae8305e2b
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
4a9cb8f10e
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
4a010fd1ea
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
...
pipeline forwarding path.
llvm-svn: 115098
2010-09-29 22:42:35 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
...
llvm-svn: 115010
2010-09-29 00:49:25 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
...
llvm-svn: 115008
2010-09-29 00:27:46 +00:00
e37da03e60
More pseudo instruction scheduling itinerary fixes.
...
llvm-svn: 114768
2010-09-24 22:41:41 +00:00
1d35ad62cc
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
...
llvm-svn: 114766
2010-09-24 22:03:46 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
0e023ea02a
fix a long standing wart: all the ComplexPattern's were being
...
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
2010-09-21 20:31:19 +00:00
722cd122dc
Fix LDM_RET schedule itinery.
...
llvm-svn: 113435
2010-09-08 22:57:08 +00:00
f43cb302ca
remove some dead code. t2addrmode_imm8s4 is never used in a
...
pattern, so there is no need to define a matching function.
llvm-svn: 113122
2010-09-05 22:51:11 +00:00
39eccb4754
temporarily revert r112664, it is causing a decoding conflict, and
...
the testcases should be merged.
llvm-svn: 112711
2010-09-01 16:00:50 +00:00
6789f8b6ae
We have a chance for an optimization. Consider this code:
...
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
llvm-svn: 112664
2010-08-31 22:41:22 +00:00
87bb14c566
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
...
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
llvm-svn: 112538
2010-08-30 22:05:23 +00:00
fef37287a8
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
...
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
llvm-svn: 112503
2010-08-30 19:49:58 +00:00
f8dfa461fa
Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the
...
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.
llvm-svn: 112462
2010-08-30 01:47:35 +00:00
df9ec17d53
- Add a parameter to T2I_bin_irs for those patterns which set the S bit.
...
- Create T2I_bin_sw_irs to be like T2I_bin_w_irs, but that it sets the S bit.
llvm-svn: 112399
2010-08-29 03:55:31 +00:00
b0dc465c04
Name ANDflag to ANDS, which is less stupid.
...
llvm-svn: 112395
2010-08-29 03:06:09 +00:00
0a65116cce
Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but
...
it sets the CPSR register.
llvm-svn: 112393
2010-08-29 03:02:11 +00:00
074d22e1ac
Restrict the register to tGPR to make sure the str instruction will be
...
encodable as a 16-bit wide instruction.
llvm-svn: 112195
2010-08-26 17:02:47 +00:00
10b20b2b81
Revert r112176; it broke test/CodeGen/Thumb2/thumb2-cmn.ll.
...
llvm-svn: 112191
2010-08-26 15:50:25 +00:00
a9a0599b39
There seems to be a (potential) hardware bug with the CMN instruction and
...
comparison with 0. These two pieces of code should give identical results:
rsbs r1, r1, 0
cmp r0, r1
mov r0, #0
it ls
mov r0, #1
and:
cmn r0, r1
mov r0, #0
it ls
mov r0, #1
However, the CMN gives the *opposite* result when r1 is 0. This is because the
carry flag is set in the CMP case but not in the CMN case. In short, the CMP
instruction doesn't perform a truncate of the (logical) NOT of 0 plus the value
of r0 and the carry bit (because the "carry bit" parameter to AddWithCarry is
defined as 1 in this case, the carry flag will always be set when r0 >= 0). The
CMN instruction doesn't perform a NOT of 0 so there is never a "carry" when this
AddWithCarry is performed (because the "carry bit" parameter to AddWithCarry is
defined as 0).
The AddWithCarry in the CMP case seems to be relying upon the identity:
~x + 1 = -x
However when x is 0 and unsigned, this doesn't hold:
x = 0
~x = 0xFFFF FFFF
~x + 1 = 0x1 0000 0000
(-x = 0) != (0x1 0000 0000 = ~x + 1)
Therefore, we should disable *all* versions of CMN, especially when comparing
against zero, until we can limit when the CMN instruction is used (when we know
that the RHS is not 0) or when we have a hardware fix for this.
(See the ARM docs for the "AddWithCarry" pseudo-code.)
This is related to <rdar://problem/7569620>.
llvm-svn: 112176
2010-08-26 09:07:33 +00:00
768d3b510c
Add the "isCompare" attribute to the defm instead of each individual instr.
...
llvm-svn: 111481
2010-08-19 00:05:48 +00:00
e2cbaf6ed7
Don't call tablegen'ed Predicate_* functions in the ARM target.
...
llvm-svn: 111277
2010-08-17 20:39:04 +00:00
62800a990b
80 column cleanup.
...
llvm-svn: 111266
2010-08-17 18:39:16 +00:00
942b10f511
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
llvm-svn: 111251
2010-08-17 17:23:19 +00:00
804f6159f1
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
...
that the high halfword is zero. The shift need not be exactly 16 bits.
llvm-svn: 111196
2010-08-16 22:26:55 +00:00
481d7a9ab4
Rename sat_shift operand to shift_imm, in preparation for using it for other
...
instructions besides saturate instructions. No functional changes.
llvm-svn: 111168
2010-08-16 18:27:34 +00:00
bffc757df7
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
...
llvm-svn: 111068
2010-08-14 03:18:29 +00:00
4577f37d49
Add a Thumb2 t2RSBrr instruction for disassembly only.
...
This fixes another part of PR7792.
llvm-svn: 111057
2010-08-13 23:24:25 +00:00
15b3c3d0ac
Move the Thumb2 SSAT and USAT optional shift operator out of the
...
instruction opcode. This fixes part of PR7792.
llvm-svn: 111047
2010-08-13 21:48:10 +00:00
91033bed94
Really control isel of barrier instructions with cpu feature.
...
llvm-svn: 110787
2010-08-11 06:36:31 +00:00
6e809de90c
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
...
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
llvm-svn: 110785
2010-08-11 06:22:01 +00:00
740c50385c
ARM: Quote $p in an asm string.
...
llvm-svn: 110780
2010-08-11 04:46:10 +00:00
5415713d9a
CBZ and CBNZ are implemented.
...
llvm-svn: 110745
2010-08-10 23:27:11 +00:00
fa16acae44
Delete some unused instructions.
...
llvm-svn: 110710
2010-08-10 19:36:22 +00:00
798617b1ab
Use the "isCompare" machine instruction attribute instead of calling the
...
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.
This pass is will eventually be folded into the Machine CSE pass.
llvm-svn: 110539
2010-08-08 05:04:59 +00:00
b128824b60
Move newlines before inline jumptables from the asm strings in .td files to
...
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
d343166a0b
Many Thumb2 instructions can reference the full ARM register set (i.e.,
...
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
llvm-svn: 109842
2010-07-30 02:41:01 +00:00
c4a96c0e8c
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
...
llvm-svn: 109813
2010-07-29 22:48:09 +00:00
7010a71ac4
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
...
Behave identically to __qadd & __qsub RealView instruction intrinsics.
llvm-svn: 109770
2010-07-29 17:56:55 +00:00
716a596cf7
Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
...
llvm-svn: 109693
2010-07-28 23:17:45 +00:00
3680f70c9d
Using BIC for immediates needs an extra bump for its complexity to get
...
instruction selection to prefer it when possible. rdar://7903972
llvm-svn: 108844
2010-07-20 16:07:04 +00:00
11013eda5a
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
...
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
llvm-svn: 108570
2010-07-16 23:05:05 +00:00
a90af1ba38
Improve 64-subtraction of immediates when parts of the immediate can fit
...
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
llvm-svn: 108339
2010-07-14 17:45:16 +00:00
1aef53403f
Add missing address register update to t2LDM_RET instruction.
...
Patch by Brian Lucas. PR7636.
llvm-svn: 108332
2010-07-14 16:02:13 +00:00
b59dd8f10a
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
...
llvm-svn: 107122
2010-06-29 05:38:36 +00:00
246c41d93e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
...
llvm-svn: 106770
2010-06-24 18:20:04 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
2d51c7c592
Allow ARM if-converter to be run after post allocation scheduling.
...
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
llvm-svn: 106344
2010-06-18 23:09:54 +00:00
84511e1526
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
0b20fdaff0
Cosmetic cleanup. No functional change.
...
llvm-svn: 104974
2010-05-28 17:51:20 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
...
llvm-svn: 104967
2010-05-28 17:37:40 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
4f48499d2c
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
llvm-svn: 104583
2010-05-25 04:51:47 +00:00
debbbe3fd9
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
llvm-svn: 104582
2010-05-25 04:43:08 +00:00
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
...
instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
...
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
0106063556
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
...
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
llvm-svn: 100892
2010-04-09 20:41:18 +00:00
d6243b49d4
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
947f04bad0
Change ARM ld/st multiple instructions to have variant instructions for
...
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
c1d1229d78
Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
...
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.
llvm-svn: 98285
2010-03-11 21:02:50 +00:00
f5e81aeba5
Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
...
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).
llvm-svn: 98217
2010-03-11 01:13:36 +00:00
9a3e2398ae
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
...
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
15804db55c
MSR (Move to Special Register from ARM core register) requires a mask to specify
...
what fields of the CPSR or SPSR are affected.
llvm-svn: 98085
2010-03-09 21:39:34 +00:00
0bfbd9b68c
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
...
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
llvm-svn: 98001
2010-03-08 22:56:15 +00:00
70e01cd001
Trivial comment change.
...
llvm-svn: 97776
2010-03-05 01:45:46 +00:00
ece1797542
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
...
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
llvm-svn: 97760
2010-03-04 22:24:41 +00:00
334db0ce7f
Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
...
Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0 ]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
llvm-svn: 97731
2010-03-04 17:40:44 +00:00
f1e25c7163
Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
...
and STRHT for disassembly only.
llvm-svn: 97655
2010-03-03 18:45:36 +00:00
f1ea86b567
Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
...
for disassembly only.
llvm-svn: 97632
2010-03-03 02:09:43 +00:00
d8c50c67dc
Eliminate unused instruction classes.
...
llvm-svn: 97617
2010-03-03 00:43:15 +00:00
334af68052
Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
...
disassembly only.
llvm-svn: 97614
2010-03-03 00:16:28 +00:00
7041f2cef6
Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
...
llvm-svn: 97595
2010-03-02 22:11:06 +00:00
9dc2105478
Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
...
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.
llvm-svn: 97582
2010-03-02 19:38:59 +00:00
44908a5e17
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
...
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
llvm-svn: 97573
2010-03-02 18:14:57 +00:00
0dae1cbf1c
AL is an optional mnemonic extension for always, except in IT instructions.
...
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.
Ref: A8.3 Conditional execution
llvm-svn: 97571
2010-03-02 17:57:15 +00:00
8c5d683aa9
The mayHaveSideEffects flag is no longer used.
...
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
38e7bb6f34
Added the follwoing 32-bit Thumb instructions for disassembly only:
...
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
llvm-svn: 97276
2010-02-26 22:04:29 +00:00
3adff378cc
Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
...
and SRS.
llvm-svn: 97164
2010-02-25 20:25:24 +00:00
871e5b0926
Added the 32-bit Thumb instructions (BXJ) for disassembly only.
...
llvm-svn: 97163
2010-02-25 19:05:29 +00:00
e285f70a42
Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
...
llvm-svn: 97159
2010-02-25 18:46:43 +00:00
3e2cad3b1a
80 column cleanup
...
llvm-svn: 96393
2010-02-16 21:23:02 +00:00
fba7fce5be
Remove trailing whitespace
...
llvm-svn: 96388
2010-02-16 21:07:46 +00:00
2284ddab56
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
...
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
llvm-svn: 96384
2010-02-16 20:42:29 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
8487d65ea2
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
...
llvm-svn: 95112
2010-02-02 19:31:58 +00:00
267430f74d
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
...
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
6c0fb92c03
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
...
llvm-svn: 93829
2010-01-19 00:44:15 +00:00
8546ec9c14
Patch by David Conrad:
...
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
llvm-svn: 93758
2010-01-18 19:58:49 +00:00
ab6e6819b2
Minor change, change the order of two "let Inst{...}" stmts within multiclass
...
T2I_bin_ii12rs definition.
llvm-svn: 93006
2010-01-08 17:41:33 +00:00
567945636f
Undo r92785, it caused test failure.
...
llvm-svn: 92796
2010-01-05 22:37:28 +00:00
a9f39bdbb6
Add Rt2 to the asm format string for 32-bit Thumb load/store register dual
...
instructions. Thumb does not have the restriction that t2 = t+1.
llvm-svn: 92785
2010-01-05 21:51:46 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
...
llvm-svn: 91555
2009-12-16 19:44:06 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
...
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
...
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
...
llvm-svn: 91329
2009-12-14 21:24:16 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
...
llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
...
llvm-svn: 91310
2009-12-14 18:56:47 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
...
llvm-svn: 89718
2009-11-24 00:20:27 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
...
llvm-svn: 89694
2009-11-23 20:35:53 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
...
llvm-svn: 85965
2009-11-03 23:13:34 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
...
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
...
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
...
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
...
This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
a6b9cab822
Enable pre-regalloc load / store multiple pass for Thumb2.
...
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
5f582b7290
RRX reads CPSR.
...
llvm-svn: 80699
2009-09-01 18:32:09 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
...
llvm-svn: 80350
2009-08-28 06:59:37 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
...
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
dd406177de
Fix revsh pattern.
...
llvm-svn: 79318
2009-08-18 05:43:23 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
...
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
eba70d85cf
Add missing defs of R2 and D1.
...
llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
608d92c943
Remove an Darwin assembler workaround.
...
llvm-svn: 78777
2009-08-12 01:56:42 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
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llvm-svn: 78701
2009-08-11 19:42:21 +00:00
d4d352c663
80 column violation.
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llvm-svn: 78657
2009-08-11 08:47:46 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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llvm-svn: 78550
2009-08-10 02:37:24 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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llvm-svn: 78410
2009-08-07 21:19:10 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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llvm-svn: 78030
2009-08-04 01:41:15 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
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llvm-svn: 77781
2009-08-01 06:13:52 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
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llvm-svn: 77764
2009-08-01 01:43:45 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
9eb3f88048
Thumb2 movcc need .w suffix.
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llvm-svn: 77743
2009-07-31 22:21:55 +00:00
0bfc8312c2
Darwin assembler now recognizes "orn", so remove workaround.
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llvm-svn: 77627
2009-07-30 21:51:41 +00:00
ce774e2383
Darwin assembler now supports "rrx", so remove workaround.
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llvm-svn: 77625
2009-07-30 21:38:40 +00:00
cab137d294
Add missing D* register clobbers for Thumb-2 call.
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llvm-svn: 77611
2009-07-30 18:01:09 +00:00
175bd14967
Make sure Thumb2 uses the right call instructions.
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llvm-svn: 77507
2009-07-29 21:26:42 +00:00
0d98d8b8b3
- Fix an obvious copy and paste error.
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- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
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llvm-svn: 77422
2009-07-29 02:18:14 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
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llvm-svn: 77364
2009-07-28 20:53:24 +00:00
68bb69d6e3
Remove support for ORN to workaround <rdar://problem/7096522>.
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llvm-svn: 77363
2009-07-28 20:51:25 +00:00
865c6298d7
Add workaround for <rdar://problem/7098328>.
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llvm-svn: 77340
2009-07-28 18:15:38 +00:00
e82862e24e
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
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llvm-svn: 77329
2009-07-28 17:06:49 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
57b51d9f82
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
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llvm-svn: 77275
2009-07-27 23:34:12 +00:00
007031d1b4
Thumb-2 does not have RSC.
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llvm-svn: 77201
2009-07-27 16:39:05 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
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llvm-svn: 77199
2009-07-27 16:31:55 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
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Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
c64ce30c67
Uh. It would be useful to actually print the operand.
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llvm-svn: 77004
2009-07-24 20:47:38 +00:00
666c912ce3
Make sure thumb2 jumptable entries are aligned.
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llvm-svn: 76986
2009-07-24 18:20:44 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
dc99f07113
Thumb2 does not allow the use of "pc" register as part of the load / store address.
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llvm-svn: 76909
2009-07-23 23:09:51 +00:00
95a73e2eab
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
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Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
llvm-svn: 76889
2009-07-23 18:26:03 +00:00
6deba28c6f
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
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llvm-svn: 76883
2009-07-23 17:06:46 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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llvm-svn: 76803
2009-07-22 22:03:29 +00:00
4b02b2f79c
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
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llvm-svn: 76729
2009-07-22 06:46:53 +00:00
711b9e809c
CMP and TST define CPSR, not use it.
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llvm-svn: 76489
2009-07-20 22:13:31 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
0f9cce7951
Add a thumb2 pass to insert IT blocks.
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llvm-svn: 75218
2009-07-10 01:54:42 +00:00
1622d7b429
Fix ldm / stm unified syntax; add t2LDM_RET.
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llvm-svn: 75188
2009-07-09 22:58:39 +00:00
7591d02c84
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
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Note, we are not yet generating these instructions.
llvm-svn: 75181
2009-07-09 22:21:59 +00:00
ad93707e16
Correct comment.
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llvm-svn: 75172
2009-07-09 20:40:44 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
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llvm-svn: 75048
2009-07-08 21:03:57 +00:00
03ab0bbb24
Generalize opcode selection in ARMBaseRegisterInfo.
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llvm-svn: 75036
2009-07-08 20:28:28 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
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llvm-svn: 74946
2009-07-07 20:39:03 +00:00
d0f6324cdc
Add Thumb2 pkhbt / pkhtb.
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llvm-svn: 74895
2009-07-07 05:35:52 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
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llvm-svn: 74889
2009-07-07 01:17:28 +00:00
40398233b7
Add bfc to armv6t2.
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llvm-svn: 74868
2009-07-06 22:23:46 +00:00
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
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llvm-svn: 74755
2009-07-03 01:43:10 +00:00
6d9041100b
Add Thumb2 load / store multiple instructions. Not used yet.
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llvm-svn: 74749
2009-07-03 00:18:36 +00:00
f30ee8820a
t2LDR_PRE etc are loads.
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llvm-svn: 74741
2009-07-03 00:08:19 +00:00
53cdf022b6
Added indexed stores.
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llvm-svn: 74740
2009-07-03 00:06:39 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
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llvm-svn: 74736
2009-07-02 23:16:11 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
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llvm-svn: 74577
2009-07-01 00:01:13 +00:00
a83100f687
Thumb-2 load and store double description. But nothing yet creates them.
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llvm-svn: 74566
2009-06-30 22:50:01 +00:00
d0890a2bad
Add thumb-2 store word, halfword, and byte.
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llvm-svn: 74555
2009-06-30 22:11:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
76b37950ca
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
eab9ca7ea6
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
5d8b6eef5a
Remove outdated comment.
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llvm-svn: 74357
2009-06-26 23:39:02 +00:00
5285817490
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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llvm-svn: 74355
2009-06-26 23:13:13 +00:00
35ee722d42
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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llvm-svn: 74321
2009-06-26 20:45:56 +00:00
5960e6d974
ADC used to implement adde should use "adcs" opcode instead of "adc".
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llvm-svn: 74293
2009-06-26 18:07:25 +00:00
0377f737ff
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
...
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
5bf9011c2d
Mark a bunch of instructions commutable.
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llvm-svn: 74237
2009-06-26 00:19:44 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
16f357cccf
Use MVN for ~t2_so_imm immediates.
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llvm-svn: 74223
2009-06-25 23:11:21 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
d76f0be844
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
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llvm-svn: 74158
2009-06-25 02:08:06 +00:00
6ea7ad0351
Add thumb2 add sp.
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llvm-svn: 74156
2009-06-25 01:21:30 +00:00
83f979a48b
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
7d80d29187
Test instructions operands were printed in the wrong order.
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llvm-svn: 73990
2009-06-23 19:56:37 +00:00
4983e4550e
Proper patterns for thumb2 shift and rotate instructions.
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llvm-svn: 73987
2009-06-23 19:39:13 +00:00
e379107cdc
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
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llvm-svn: 73975
2009-06-23 18:14:38 +00:00
b45cebabc9
Obvious typo.
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llvm-svn: 73967
2009-06-23 17:54:26 +00:00
431cf567de
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
...
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
022a726a25
Replace isTwoAddress with operand constraint.
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llvm-svn: 73947
2009-06-23 05:23:49 +00:00
5658086052
Fix asm string from MOVi16
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llvm-svn: 73661
2009-06-17 23:43:36 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
b6f4538683
Add placeholder for thumb2 stuff
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llvm-svn: 72593
2009-05-29 23:41:08 +00:00
Jim Grosbach