5e152182a4
Invoke setTargetDAGCombine for SELECT.
...
llvm-svn: 152290
2012-03-08 03:26:37 +00:00
7dd7c08419
Swap the operands of a select node if the false (the second) operand is 0.
...
For example, this pattern
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)
This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.
llvm-svn: 152285
2012-03-08 02:14:24 +00:00
956dd2261e
Set minimum function alignment to 3 if target is Mips64.
...
llvm-svn: 152282
2012-03-08 01:59:33 +00:00
0b2fa914f0
This patch eliminates redundant instructions that produce 0.
...
For example, the first instruction in the code below can be eliminated if the
use of $vr0 is replaced with $zero:
addiu $vr0, $zero, 0
add $vr2, $vr1, $vr0
add $vr2, $vr1, $zero
llvm-svn: 152280
2012-03-08 01:51:59 +00:00
fd93a59557
Make MCRegisterInfo available to the the MCInstPrinter.
...
Used to allow context sensitive printing of super-register or sub-register
references.
llvm-svn: 152043
2012-03-05 19:33:20 +00:00
4b02a29eba
Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
...
llvm-svn: 152016
2012-03-05 05:37:41 +00:00
1d32658877
Use uint16_t to store register overlaps to reduce static data.
...
llvm-svn: 152001
2012-03-04 10:43:23 +00:00
420525ce3b
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
...
llvm-svn: 151996
2012-03-04 03:33:22 +00:00
5350c24509
Changes for migrating to using register mask operands.
...
llvm-svn: 151847
2012-03-01 22:27:29 +00:00
6bbe1f0d10
Fix bugs which were introduced when support for base+index floating point loads
...
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
llvm-svn: 151843
2012-03-01 22:12:30 +00:00
1ee768db53
Pass endian information to constructors. Define separate functions to create
...
objects for big endian and little endian targets.
Patch by Jack Carter.
llvm-svn: 151788
2012-03-01 01:53:15 +00:00
65f9d19c4f
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
...
llvm-svn: 151645
2012-02-28 18:51:51 +00:00
ee7b899343
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
...
llvm-svn: 151630
2012-02-28 15:36:07 +00:00
f54f60f3ce
remove blanks, and some code format
...
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
87c7b09d8d
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
...
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
llvm-svn: 151623
2012-02-28 06:42:03 +00:00
b2b980e628
Add comments.
...
llvm-svn: 151615
2012-02-28 03:18:43 +00:00
b8a8e0c262
Do not reserve $gp as a dedicated global base register if the target ABI is not O32.
...
llvm-svn: 151614
2012-02-28 03:17:38 +00:00
330d901ce3
Add support for floating point base register + offset register addressing mode
...
load and store instructions.
llvm-svn: 151611
2012-02-28 02:55:02 +00:00
b260f206d2
Remove unnecessary template parameters.
...
llvm-svn: 151540
2012-02-27 19:17:53 +00:00
3c5cab4730
Fix instruction predicates that were not set correctly.
...
llvm-svn: 151538
2012-02-27 19:09:08 +00:00
f6de2daf13
delete useless comment&blank
...
llvm-svn: 151512
2012-02-27 02:21:34 +00:00
60f7a8e710
Add definitions of floating point multiply add/sub and negative multiply
...
add/sub instructions.
llvm-svn: 151415
2012-02-25 00:21:52 +00:00
b049aef2d1
Add an option to use a virtual register as the global base register instead of
...
reserving a physical register ($gp or $28) for that purpose.
This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.
example:
.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...
llvm-svn: 151402
2012-02-24 22:34:47 +00:00
683f8fffcf
comment fix
...
llvm-svn: 151341
2012-02-24 02:17:26 +00:00
74aa025d68
some comment fix
...
llvm-svn: 151340
2012-02-24 02:15:57 +00:00
9d2d2adc25
replace a balnk with -
...
llvm-svn: 151337
2012-02-24 02:05:28 +00:00
19b0c8244b
80 columns of Mips InstPrinter Makefile
...
llvm-svn: 151332
2012-02-24 01:47:01 +00:00
760b134ffa
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
...
llvm-svn: 151134
2012-02-22 05:59:10 +00:00
a7721f6b4d
Use a function in MathExtras to do sign extension.
...
llvm-svn: 151107
2012-02-22 00:16:54 +00:00
636a3d618c
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
...
llvm-svn: 150918
2012-02-19 11:37:01 +00:00
9f6101191b
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
...
llvm-svn: 150805
2012-02-17 08:55:11 +00:00
d608bac682
Do not promote i32 arguments to i64. This was causing unnecessary sign extension
...
instructions to be emitted.
llvm-svn: 150782
2012-02-17 02:20:26 +00:00
dd6c1cd4e8
add Emacs tag and fix some comment error in file headers
...
llvm-svn: 150775
2012-02-17 01:23:50 +00:00
b4d2ccf2ab
Remove comment.
...
llvm-svn: 150739
2012-02-16 22:52:29 +00:00
4705b0cc1c
Remove trailing whitespace. Add newline.
...
llvm-svn: 150706
2012-02-16 17:48:20 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
...
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
c4965bce14
Convert assert(0) to llvm_unreachable
...
llvm-svn: 149814
2012-02-05 07:21:30 +00:00
f8ea108c05
TargetPassConfig: confine the MC configuration to TargetMachine.
...
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.
Sorry for the target header churn. Attempting to stabilize them.
llvm-svn: 149754
2012-02-04 02:56:59 +00:00
ccb673659a
Added TargetPassConfig. The first little step toward configuring codegen passes.
...
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.
llvm-svn: 149672
2012-02-03 05:12:41 +00:00
f0b08445f6
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is
...
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.
llvm-svn: 149668
2012-02-03 04:33:00 +00:00
961883c1cf
Set the correct stack pointer register.
...
llvm-svn: 149585
2012-02-02 03:17:04 +00:00
f029537e68
Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and
...
selector registers.
llvm-svn: 149584
2012-02-02 03:13:40 +00:00
d9fef17749
Add DWARF numbers of 64-bit registers.
...
llvm-svn: 149583
2012-02-02 02:56:14 +00:00
b47489d4ef
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
...
Fixes PR11877
llvm-svn: 149180
2012-01-28 15:58:32 +00:00
012f041bce
Mark 64-bit register RA_64 unused too.
...
llvm-svn: 148918
2012-01-25 04:19:22 +00:00
01d3c42f90
Modify MipsFrameLowering::emitPrologue and emitEpilogue.
...
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
instructions which store callee-saved registers have been emitted.
llvm-svn: 148917
2012-01-25 04:12:04 +00:00
d1d4b3efcf
Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to
...
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.
llvm-svn: 148916
2012-01-25 03:55:10 +00:00
6c421ea484
MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.
...
inttypes.h is not supplied in msvc.
llvm-svn: 148912
2012-01-25 03:34:41 +00:00
96a21dcea3
Target/Mips: Unbreak CMake build.
...
llvm-svn: 148909
2012-01-25 03:15:46 +00:00
86d5fadd57
Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
...
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.
llvm-svn: 148908
2012-01-25 03:01:35 +00:00
ff36fd3de3
Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
...
load an immediate.
llvm-svn: 148900
2012-01-25 01:43:36 +00:00
d7970f9e4b
Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
...
which is what N32/64 does.
llvm-svn: 148875
2012-01-24 23:18:43 +00:00
7e6c195c11
Pass CCState by reference.
...
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
77dbd786c8
Pattern for f32 to i64 conversion.
...
llvm-svn: 148869
2012-01-24 22:05:25 +00:00
9f7ec1538f
64-bit sign extension in register instructions.
...
llvm-svn: 148862
2012-01-24 21:41:09 +00:00
d845d9d9e9
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
...
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
...
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
f1fb1d2375
Ignore register mask operands when lowering instructions to MC.
...
This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.
llvm-svn: 148437
2012-01-18 23:52:19 +00:00
aba3de99c0
Tidy up. MCAsmBackend naming conventions.
...
llvm-svn: 148400
2012-01-18 18:52:16 +00:00
f43b599550
Add a CoveredBySubRegs property to Register descriptions.
...
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
llvm-svn: 148363
2012-01-18 00:16:39 +00:00
486df738c3
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
...
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)
llvm-svn: 148262
2012-01-16 23:24:27 +00:00
647841b181
Add big endian mips support. Based on a patch by Jack Carter.
...
llvm-svn: 147924
2012-01-11 04:04:14 +00:00
870c4e92b9
Add the skeleton of an asm parser for mips.
...
llvm-svn: 147923
2012-01-11 03:56:41 +00:00
6898db6269
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
...
llvm-svn: 147738
2012-01-07 19:42:13 +00:00
a3d90a9467
Fix uninitialized variable warning.
...
llvm-svn: 147676
2012-01-06 20:02:49 +00:00
aac3e06bf7
Enable -soft-float for MIPS.
...
llvm-svn: 147541
2012-01-04 19:29:11 +00:00
3b775b8cc3
Rename immLUiOpnd.
...
llvm-svn: 147519
2012-01-04 03:09:26 +00:00
b89a4bfe41
- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit
...
versions derive from them.
- JALR64 is not needed since N64 does not emit jal.
- Add template parameter to BranchLink that sets the rt field.
- Fix the set of temporary registers for O32 and N64.
llvm-svn: 147518
2012-01-04 03:02:47 +00:00
c669d7a6db
Have getRegForInlineAsmConstraint return the correct register class when target
...
is Mips64.
llvm-svn: 147516
2012-01-04 02:45:01 +00:00
cd1d447d62
Cleanup Mips code and rename some variables. Patch by Jack Carter
...
llvm-svn: 147383
2011-12-30 21:09:41 +00:00
d5b2834fb7
Improve Mips JIT.
...
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.
Patch by Sasa Stankovic
llvm-svn: 147382
2011-12-30 21:04:30 +00:00
1cf7576707
Add MachineMemOperands to instructions generated in storeRegToStackSlot or
...
loadRegFromStackSlot.
llvm-svn: 147235
2011-12-24 03:11:18 +00:00
6f54a46133
Detect unaligned loads/stores that have been added for Mips64 support.
...
llvm-svn: 147234
2011-12-24 03:07:37 +00:00
695d113adc
If target ABI is N64, LEA should be daddiu.
...
llvm-svn: 147232
2011-12-24 02:59:27 +00:00
1dc45d8df4
Move the Mips only bits of the ELF writer to lib/Target/Mips.
...
llvm-svn: 147133
2011-12-22 03:03:17 +00:00
e2eed9649e
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
...
ELF relocations.
Patch by Jack Carter.
llvm-svn: 147118
2011-12-22 01:05:17 +00:00
1ad4095d6b
Reduce the exposure of Triple::OSType in the ELF object writer. This will
...
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
2011-12-21 17:00:36 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
...
The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
1d8efaba7e
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
...
case for DCLO and DCLZ.
llvm-svn: 147022
2011-12-21 00:20:27 +00:00
410ce9cb44
Expand 64-bit CTPOP and CTTZ.
...
llvm-svn: 147021
2011-12-21 00:14:05 +00:00
91c052c4d8
Expand 64-bit atomic load and store.
...
llvm-svn: 147019
2011-12-21 00:02:58 +00:00
4706ac9715
Add definition of DSBH (Double Swap Bytes within Halfwords) and
...
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
llvm-svn: 147017
2011-12-20 23:56:43 +00:00
43c1ff4db3
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
...
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
llvm-svn: 147015
2011-12-20 23:47:44 +00:00
79aed157e7
64-bit uint-fp conversion nodes are expanded.
...
llvm-svn: 147014
2011-12-20 23:40:56 +00:00
2bb8d068f5
Enable custom lowering DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 147013
2011-12-20 23:35:46 +00:00
8e2c02e2d6
Set the correct stack pointer register that should be saved or restored.
...
llvm-svn: 147012
2011-12-20 23:28:36 +00:00
cb2a85bc22
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
...
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
llvm-svn: 147008
2011-12-20 23:10:57 +00:00
2c8d1734f8
Fix indentation.
...
llvm-svn: 147007
2011-12-20 22:58:01 +00:00
cf10f08825
64-bit data directive.
...
llvm-svn: 147005
2011-12-20 22:52:19 +00:00
494fdf1499
32-to-64-bit sext_inreg pattern.
...
llvm-svn: 147004
2011-12-20 22:40:40 +00:00
8756816e6f
Add 64-bit extload patterns.
...
llvm-svn: 147003
2011-12-20 22:36:08 +00:00
0cee2045c9
Add patterns for matching extloads with 64-bit address. The patterns are enabled
...
only when the target ABI is N64.
llvm-svn: 147001
2011-12-20 22:33:53 +00:00
dac1d48d8d
Add code in MipsDAGToDAGISel for selecting constant +0.0.
...
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
llvm-svn: 146999
2011-12-20 22:25:50 +00:00
14468c6cb6
Revert part of r146995 that was accidentally commmitted.
...
llvm-svn: 146996
2011-12-20 22:09:36 +00:00
4e210691c0
32-to-64-bit sign extension pattern.
...
llvm-svn: 146995
2011-12-20 22:06:20 +00:00
9b9bd1cc15
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
...
only when the target ABI is N64.
llvm-svn: 146992
2011-12-20 21:50:49 +00:00
e805b16e3d
Fix up the CMake build for the new files added in r146960, they're
...
likely to stay either way that discussion ends up resolving itself.
llvm-svn: 146966
2011-12-20 08:42:11 +00:00
a379b18173
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
...
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
...
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
...
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
2a232d81f6
Remove definitions of double word shift plus 32 instructions. Assembler or
...
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
llvm-svn: 146893
2011-12-19 19:44:09 +00:00
c4db30e358
Remove unused predicate.
...
llvm-svn: 146889
2011-12-19 19:32:20 +00:00
3c9f336361
Remove the restriction on the first operand of the add node in SelectAddr.
...
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
llvm-svn: 146888
2011-12-19 19:28:37 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
...
emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
5e9d16cb53
Expand .cprestore directive to multiple instructions if the offset does not fit
...
in a 16-bit field.
llvm-svn: 146469
2011-12-13 03:09:05 +00:00
637cc6a8aa
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
...
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
llvm-svn: 146466
2011-12-13 01:56:10 +00:00
8889bb08b8
LLVMBuild: Introduce a common section which currently has a list of the
...
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
llvm-svn: 146436
2011-12-12 22:45:54 +00:00
5d5e0d819d
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
...
-relocation-model=static.
llvm-svn: 146432
2011-12-12 22:39:35 +00:00
faa88c0add
Fix indentation.
...
llvm-svn: 146431
2011-12-12 22:38:19 +00:00
27a7489a03
LLVMBuild: Remove trailing newline, which irked me.
...
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
64ba50a972
Mips: Don't create a dangling IR function just to get the address of a symbol.
...
llvm-svn: 146340
2011-12-11 12:21:34 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
8e16aac534
jalr should use t9 ($25) for indirect calls regardless of the relocation model
...
specified.
llvm-svn: 146229
2011-12-09 01:45:12 +00:00
f10ee84956
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
...
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
llvm-svn: 146183
2011-12-08 21:05:38 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
...
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
66232aa19d
Add newline.
...
llvm-svn: 146100
2011-12-07 23:26:03 +00:00
36d2198dae
Add 64-bit HWR29 register.
...
llvm-svn: 146099
2011-12-07 23:23:52 +00:00
9778e7a67c
32 to 64-bit anyext pattern.
...
llvm-svn: 146097
2011-12-07 23:21:19 +00:00
ae378af667
32 to 64-bit zext pattern.
...
llvm-svn: 146096
2011-12-07 23:14:41 +00:00
56b70de01b
Variable cleanup. Based on past patch submittals variable names have
...
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
llvm-svn: 146088
2011-12-07 22:35:30 +00:00
b2e05cb6b1
64-bit WrapperPICPat patterns.
...
llvm-svn: 146086
2011-12-07 22:11:43 +00:00
6820eebde1
Define base class for WrapperPICPat.
...
llvm-svn: 146081
2011-12-07 21:54:54 +00:00
c5b5a8d8b1
Modify LowerFCOPYSIGN to handle Mips64.
...
llvm-svn: 146080
2011-12-07 21:48:50 +00:00
4f864b78e6
Fix comment.
...
llvm-svn: 146063
2011-12-07 20:15:01 +00:00
d16e926a6b
Fix comment.
...
llvm-svn: 146062
2011-12-07 20:13:53 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
7f8e563a69
Add bundle aware API for querying instruction properties and switch the code
...
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
llvm-svn: 146026
2011-12-07 07:15:52 +00:00
61e6d987bf
Add a few moreLocal/Global R_MIPS_GOT related fixups and
...
make the addend fixup code a bit more generic
Patch by Jack Carter.
llvm-svn: 145998
2011-12-07 00:28:57 +00:00
2a81dd4a3c
First chunk of MachineInstr bundle support.
...
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
llvm-svn: 145975
2011-12-06 22:12:01 +00:00
0c24d8a406
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
...
llvm-svn: 145912
2011-12-06 03:34:48 +00:00
1b1a122b4c
Add register HWR29 numbering. Patch by Jack Carter
...
llvm-svn: 145910
2011-12-06 03:34:36 +00:00
d3002490bf
MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.
...
llvm-svn: 145894
2011-12-06 01:48:32 +00:00
25b63fa117
Move target-specific logic out of generic MCAssembler.
...
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
llvm-svn: 145881
2011-12-06 00:47:03 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
...
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
...
them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
...
O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
dc25f9f38a
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
...
tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
llvm-svn: 145451
2011-11-29 23:08:41 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
...
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
049e9e4d22
This patch makes the following changes necessary for MIPS' direct code emission.
...
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).
llvm-svn: 145113
2011-11-23 22:19:28 +00:00
f5ddf13f79
This patch addresses gp relative fixups/relocations for jump tables.
...
llvm-svn: 145112
2011-11-23 22:18:04 +00:00
b31abde0f3
Lower 64-bit constant pool node.
...
llvm-svn: 144849
2011-11-16 22:44:38 +00:00
eb42071721
Lower 64-bit block address.
...
llvm-svn: 144847
2011-11-16 22:42:10 +00:00
7b8547c4d0
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
...
nodes.
llvm-svn: 144841
2011-11-16 22:39:56 +00:00
6d617ceca2
64-bit jump register instruction.
...
llvm-svn: 144840
2011-11-16 22:36:01 +00:00
ecb2908bf9
Sink codegen optimization level into MCCodeGenInfo along side relocation model
...
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
2011-11-16 08:38:26 +00:00
6ee8fc88c7
Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
...
registers and instructions when ABI is N64.
llvm-svn: 144666
2011-11-15 18:53:55 +00:00
494913270e
Set nomacro before emitting the sequence of instructions that set global pointer
...
register.
llvm-svn: 144665
2011-11-15 18:44:44 +00:00
66a14c0650
Simplify function PassByValArg64.
...
llvm-svn: 144664
2011-11-15 18:42:25 +00:00
b7796ae938
Delete files.
...
llvm-svn: 144655
2011-11-15 18:22:48 +00:00
1c0590c5da
Remove MipsMCSymbolRefExpr.
...
llvm-svn: 144654
2011-11-15 18:20:08 +00:00
319904cc7e
Unbreak Release builds.
...
llvm-svn: 144560
2011-11-14 19:51:48 +00:00
f93b3f46f8
32-to-64-bit extended load.
...
llvm-svn: 144554
2011-11-14 19:06:14 +00:00
0b8bc00424
AnalyzeCallOperands function for N32/64.
...
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.
llvm-svn: 144553
2011-11-14 19:02:54 +00:00
52359363f2
Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.
...
llvm-svn: 144552
2011-11-14 19:01:09 +00:00
d673cfe027
Remove variable that keeps the size of area used to save byval or variable
...
argument registers on the callee's stack frame, along with functions that set
and get it.
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.
llvm-svn: 144549
2011-11-14 18:56:20 +00:00
77733535eb
Fix typo.
...
llvm-svn: 144453
2011-11-12 02:38:12 +00:00
19891f843c
Implement Mips64's handling of byval arguments in LowerCall.
...
llvm-svn: 144452
2011-11-12 02:34:50 +00:00
fb9bae34da
Implement Mips64's handling of byval arguments in LowerFormalArguments.
...
llvm-svn: 144449
2011-11-12 02:29:58 +00:00
5ed07c03f4
64-bit arbitrary immediate pattern.
...
llvm-svn: 144448
2011-11-12 02:25:00 +00:00
202f6400ef
Function for handling byval arguments.
...
llvm-svn: 144447
2011-11-12 02:20:46 +00:00
52823cc91c
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
...
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
7f89f4c91c
CMake: Fix CMake build for new Mips tblgen file.
...
llvm-svn: 144423
2011-11-11 23:12:56 +00:00
c85e3ff334
Mips MC object code emission improvements:
...
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
4a63d1c0f0
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
...
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
llvm-svn: 144373
2011-11-11 04:18:21 +00:00
21cbc25bbb
64-bit atomic instructions.
...
llvm-svn: 144372
2011-11-11 04:14:30 +00:00
9189d7127f
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
...
llvm-svn: 144371
2011-11-11 04:11:56 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
...
llvm-svn: 144370
2011-11-11 04:06:38 +00:00
0009dc2088
64-bit versions of jal, jalr and bal.
...
llvm-svn: 144368
2011-11-11 04:03:54 +00:00
11521863da
Emit Mips64's sequence of instructions that set global register in prologue.
...
llvm-svn: 144367
2011-11-11 04:00:29 +00:00
aa1f4c7986
Fix printing of MCSymbolRegExpr. Needs three closing parentheses for
...
VK_Mips_GPOFF_HI/LO.
llvm-svn: 144366
2011-11-11 03:58:36 +00:00
6d617b48c7
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
...
llvm-svn: 144344
2011-11-11 00:23:56 +00:00
233c9304a8
llvm-build: Add --native-target and --enable-targets options, and add logic to
...
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
82219ad4dc
llvm-build: Add an explicit component type to represent targets.
...
- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
d5edb3847a
Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts.
...
Patch by Jack Carter.
llvm-svn: 144139
2011-11-08 22:26:47 +00:00
82cd9e81fc
Added invariant field to the DAG.getLoad method and changed all calls.
...
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
71133fe9c6
This patch handles unaligned loads and stores in Mips JIT. Mips backend
...
implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).
Patch by Petar Jovanovic and Sasa Stankovic.
llvm-svn: 144081
2011-11-08 12:47:11 +00:00
2216f73676
Various Mips64 floating point instruction patterns.
...
llvm-svn: 144019
2011-11-07 21:38:58 +00:00
b2d37760a2
Add definition of the base class for floating point comparison instructions
...
and add Mips64's version too.
llvm-svn: 144018
2011-11-07 21:37:33 +00:00
81c14002dc
Add code needed for copying between 64-bit integer and floating pointer
...
registers.
llvm-svn: 144017
2011-11-07 21:35:45 +00:00
1537e297e1
Add definitions of 64-bit instructions which move data between integer and
...
floating pointer registers.
llvm-svn: 144016
2011-11-07 21:32:58 +00:00
2b8d1f163f
Add definition of 64-bit load upper immediate.
...
llvm-svn: 143994
2011-11-07 19:10:49 +00:00
2f4480046b
Include RegSaveAreaSize in the computation of stack size.
...
llvm-svn: 143993
2011-11-07 19:07:35 +00:00
7bcecd486f
Define functions that get or set the size of area on callee's stack frame which
...
is used to save va_arg or byval arguments passed in registers.
llvm-svn: 143992
2011-11-07 19:06:10 +00:00
d9c2e46cfb
Use array_lengthof to compute the number of iterations of a loop.
...
llvm-svn: 143991
2011-11-07 19:03:40 +00:00
cf7e5b0976
Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted
...
when shift amount is larger than 32.
llvm-svn: 143990
2011-11-07 19:01:49 +00:00
770f0646db
Make the type of shift amount i32 in order to reduce the number of shift
...
instruction definitions.
llvm-svn: 143989
2011-11-07 18:59:49 +00:00
d5c1329078
Add 64-bit to 32-bit trunc pattern.
...
llvm-svn: 143988
2011-11-07 18:57:41 +00:00
20baffb257
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
...
llvm-svn: 143891
2011-11-06 20:37:06 +00:00
4a9c6426ff
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just
...
added a layer of indirection with no value (not even conciseness).
llvm-svn: 143727
2011-11-04 19:04:23 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
...
llvm-svn: 143634
2011-11-03 18:53:17 +00:00
104b7e3f2c
Make changes necessary in LowerFormalArguments to support Mips64.
...
llvm-svn: 143218
2011-10-28 19:55:48 +00:00
b20a325baf
Make changes necessary in LowerCall to support Mips64.
...
llvm-svn: 143217
2011-10-28 19:49:00 +00:00
7989f15d37
Add variable IsO32 to MipsTargetLowering.
...
llvm-svn: 143213
2011-10-28 18:47:24 +00:00
c0ecd1f7ed
Corrects previously incorrect $sp change in MipsCompilationCallback.
...
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned
Patch by Petar Jovanovic.
llvm-svn: 142930
2011-10-25 17:30:47 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
...
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
2b7a1ff77f
Coding style cleanups. No functionality change.
...
llvm-svn: 142341
2011-10-18 07:40:22 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
...
llvm-svn: 142332
2011-10-18 03:17:34 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
...
llvm-svn: 142220
2011-10-17 18:43:19 +00:00
3634f34659
Revert change made in r142205.
...
llvm-svn: 142217
2011-10-17 18:33:24 +00:00
33fe8f908c
Redefine count-leading 0s and 1s instructions.
...
llvm-svn: 142216
2011-10-17 18:26:37 +00:00
8c446be204
Redefine mfhi/lo and mthi/lo instructions.
...
llvm-svn: 142214
2011-10-17 18:24:15 +00:00
0317b65367
Redefine multiply and divide instructions.
...
llvm-svn: 142211
2011-10-17 18:21:24 +00:00
2736bbc09e
Add definition of a base class for logical shift/rotate instructions with two
...
source registers and redefine 32-bit and 64-bit instructions.
llvm-svn: 142210
2011-10-17 18:17:58 +00:00
73081309c3
Add definition of a base class for logical shift/rotate immediate instructions
...
and have 32-bit and 64-bit instructions derive from it.
llvm-svn: 142207
2011-10-17 18:06:56 +00:00
e3f27b79dc
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
...
llvm-svn: 142205
2011-10-17 18:01:00 +00:00
44419bfd54
Add f128 to datalayout string.
...
llvm-svn: 141978
2011-10-14 19:14:50 +00:00
62b34a65f9
Revert r141932, r141936 and r141937.
...
llvm-svn: 141959
2011-10-14 17:16:39 +00:00
d9ea7c8c31
Definition of function getMipsRegisterNumbering.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141938
2011-10-14 03:04:24 +00:00
1742a2c093
Add definition of class MipsELFWriterInfo.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141937
2011-10-14 02:55:47 +00:00
0fc7d7af5a
Add missing relocation types.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141936
2011-10-14 02:47:50 +00:00
769fc971b4
Fixup enumerations.
...
Patch by Jack Carter at Mips.
llvm-svn: 141934
2011-10-14 02:38:56 +00:00
4e2bfe0770
Add more Mips relocation types.
...
Patch by Jack Carter at Mips.
llvm-svn: 141932
2011-10-14 02:17:30 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
...
llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
...
Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
...
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
...
instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
8d4f74a6b1
Fix comment.
...
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
1c18465859
Fix function isUnalignedLoadStore.
...
llvm-svn: 141722
2011-10-11 22:04:01 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
453ac88b56
Change the names of 64-bit logical instructions so that they match the names of
...
the real instructions.
llvm-svn: 141718
2011-10-11 21:48:01 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
09b23eb7bc
Modify lowering of GlobalAddress so that correct code is emitted when target is
...
Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
fa55bc27cb
Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.
...
llvm-svn: 141615
2011-10-11 00:44:20 +00:00
e6ced5b3d5
Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.
...
llvm-svn: 141613
2011-10-11 00:37:28 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
...
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
6be7d6c976
Simplify definition of FP move instructions.
...
llvm-svn: 141476
2011-10-08 03:50:18 +00:00
2365f90676
Define classes and multiclasses for FP binary instructions.
...
llvm-svn: 141475
2011-10-08 03:38:41 +00:00
c7548dec7d
Define multiclasses for FP-to-FP instructions.
...
llvm-svn: 141474
2011-10-08 03:29:22 +00:00
13ae13bdc2
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
...
conversion instructions.
llvm-svn: 141473
2011-10-08 03:19:38 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
...
instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
fb3d935649
Build system infrastructure for multiple tblgens.
...
llvm-svn: 141266
2011-10-06 01:51:51 +00:00
c6b742f98a
Fix assertion string.
...
llvm-svn: 141197
2011-10-05 18:17:49 +00:00
426a804825
Make sure candidate for delay slot filler is not a return instruction.
...
llvm-svn: 141196
2011-10-05 18:16:09 +00:00
14e4149f4e
Add RA to the set of registers that are defined if instruction is a call.
...
llvm-svn: 141194
2011-10-05 18:11:44 +00:00
9ebdf46b5a
MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly.
...
llvm-svn: 141174
2011-10-05 10:11:02 +00:00
02e760add3
Insert space.
...
llvm-svn: 141158
2011-10-05 02:22:49 +00:00
8e532eb92f
Do not examine variadic or implicit operands if instruction is a return (jr).
...
llvm-svn: 141157
2011-10-05 02:21:58 +00:00
0d7dfc0b1f
Clean up function Filler::delayHasHazard.
...
llvm-svn: 141156
2011-10-05 02:18:58 +00:00
7b204688e7
Remove function Filler::insertCallUses.
...
Record the registers used and defined by a call in Filler::insertDefsUses.
llvm-svn: 141154
2011-10-05 02:04:17 +00:00
d9c8aab894
Clean up Filler::findDelayInstr.
...
llvm-svn: 141152
2011-10-05 01:57:46 +00:00
e7b0697412
Remove function Filler::isDelayFiller. Check if I is the same instruction that
...
filled the last delay slot visited.
llvm-svn: 141151
2011-10-05 01:30:09 +00:00
5d4e4ea3d5
Clean up Filler::runOnMachineBasicBlock. Change interface of
...
Filler::findDelayInstr.
llvm-svn: 141150
2011-10-05 01:23:39 +00:00
9e6034444a
Define a statistic for the number of slots that were filled with useful
...
instructions (instructions that are not NOP).
llvm-svn: 141149
2011-10-05 01:19:13 +00:00
8b3666af1b
Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before
...
I->getDesc().hasDelaySlot() does.
llvm-svn: 141148
2011-10-05 01:15:31 +00:00
7d398636a2
Add comments and move assignment statement. If sawStore is true, sawLoad does
...
not have to be set.
llvm-svn: 141147
2011-10-05 01:09:37 +00:00
b345b5c424
Correct description string of enable-mips-delay-filler.
...
llvm-svn: 141146
2011-10-05 01:06:57 +00:00
c3a6357ee3
Add support for 64-bit logical NOR.
...
llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
...
llvm-svn: 141028
2011-10-03 21:16:50 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
3caf8cb310
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
...
registers.
llvm-svn: 141019
2011-10-03 20:38:08 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
...
llvm-svn: 141017
2011-10-03 20:01:11 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
...
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
ee09394644
Register the MC object streamer.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
587fe6cd52
Add MCELFObjectTargetWriter and MCAsmBackend classes.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140885
2011-09-30 21:04:02 +00:00
3bad73a900
Update CMake build.
...
llvm-svn: 140879
2011-09-30 20:44:33 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
9727af7657
isCommutable should be 0 for DSUBu.
...
llvm-svn: 140862
2011-09-30 17:26:36 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
6728958279
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
...
It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
5a1b4a80c3
Define classes for unary and binary FP instructions and use them to define
...
multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
...
llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
...
llvm-svn: 140704
2011-09-28 17:56:55 +00:00
c117967b19
Mips64 predicate definitions. Patch by Liu.
...
llvm-svn: 140703
2011-09-28 17:50:27 +00:00
ae40dc735d
Remove MipsFPRound. Mips1 is no longer supported.
...
llvm-svn: 140661
2011-09-27 23:55:37 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
...
of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
...
Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
...
llvm-svn: 140607
2011-09-27 16:58:43 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
...
llvm-svn: 140598
2011-09-27 04:57:54 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
7d7ee0c3ac
Add .td file.
...
llvm-svn: 140446
2011-09-24 01:40:18 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
d6af2c62b4
Implement N32/64 calling convention. Patch by Liu.
...
llvm-svn: 140401
2011-09-23 19:08:15 +00:00
ceb55e72de
Make FGR64RegisterClass available if target is Mips64.
...
llvm-svn: 140397
2011-09-23 18:28:39 +00:00
77709a6793
Add definitions of 64-bit register files. Add code for returning Mips64's sets of
...
callee-saved registers and reserved registers.
llvm-svn: 140395
2011-09-23 18:11:56 +00:00
42fe6bd5f2
Add definitions of 64-bit int registers.
...
llvm-svn: 140366
2011-09-23 02:33:15 +00:00
61bbcce84a
Do not rely on the enum values of argument registers A0-A3 being consecutive.
...
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
56acf840f1
Print parentheses in next line.
...
llvm-svn: 140325
2011-09-22 18:29:29 +00:00
c021a4b8b4
Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment.
...
llvm-svn: 140324
2011-09-22 18:24:21 +00:00
79a45a839c
Define a new sub-register index sub_32 for accessing the 32-bit sub-register of
...
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.
llvm-svn: 140319
2011-09-22 17:57:32 +00:00
35b7fe8c25
Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or
...
VK_Mips_GPOFF_LO.
llvm-svn: 140316
2011-09-22 17:44:37 +00:00
da33066424
Add F31 to the set of callee-saved registers.
...
llvm-svn: 140315
2011-09-22 17:35:03 +00:00
cf9c4f80ba
Fix typo.
...
llvm-svn: 140313
2011-09-22 17:26:58 +00:00
Akira Hatanaka