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Author SHA1 Message Date
Evan Cheng 73fd08d5bd Make test less fragile. 
llvm-svn: 155732
 2012-04-27 20:48:18 +00:00
Evan Cheng f52003de56 - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2 
instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541

llvm-svn: 155685
 2012-04-27 01:27:19 +00:00