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221 Commits

Author SHA1 Message Date
Caroline Tice fe28f1bff9 Fix various small bugs found in the instruction emulation functions. 
llvm-svn: 127712
 2011-03-16 00:06:12 +00:00
Caroline Tice 94f87e37c8 Add code to emulate RFE Arm instruction. 
Add new instruction context for RFE instruction.

Add several new helper functions to help emulate RFE instruction
(including CurrentModeIsPrivileged, BadMode, and CPSRWriteByInstr).

llvm-svn: 126965
 2011-03-03 22:37:46 +00:00
Caroline Tice c8d0d3ae0b Add code to emulate UXTH Arm instruction. 
llvm-svn: 126954
 2011-03-03 18:48:58 +00:00
Caroline Tice 9c35f321c6 Add code to emulate UXTB Arm instruction. 
llvm-svn: 126953
 2011-03-03 18:27:17 +00:00
Caroline Tice 8678f2a192 Add code to emulate SXTH Arm instruction. 
llvm-svn: 126951
 2011-03-03 18:04:49 +00:00
Caroline Tice 67735bf069 Add code to emulate SXTB Arm instruction. 
llvm-svn: 126949
 2011-03-03 17:42:58 +00:00
Caroline Tice edc103e253 Fix bug where bitwise-AND was being used and it should have been bitwise-OR. 
llvm-svn: 126904
 2011-03-03 00:07:02 +00:00
Caroline Tice 30f40c6850 Add code to emulate ADD (immediate, Thumb) Arm instruction. 
Add addition context to EmulateInstruction contexts.

llvm-svn: 126903
 2011-03-02 23:57:02 +00:00
Caroline Tice 1a234ff46f Add code to emulate MUL Arm instruction. 
Add new context type & info structure for  mul instruction.

llvm-svn: 126891
 2011-03-02 22:43:54 +00:00
Caroline Tice a0d3b67572 Add code to emulate LDRSH (register) Arm instruction. 
llvm-svn: 126881
 2011-03-02 21:13:44 +00:00
Caroline Tice 1cd4459b21 Add code to emulate LDRSH (literal) Arm instruction. 
llvm-svn: 126866
 2011-03-02 19:45:34 +00:00
Caroline Tice d3e57ee4fc Add code to emulate LDRSH (immediate) Arm instruction. 
llvm-svn: 126807
 2011-03-02 00:39:42 +00:00
Caroline Tice 4776fbbd72 Add code to emulate LDRSB (register) Arm instruction. 
llvm-svn: 126802
 2011-03-01 23:55:59 +00:00
Caroline Tice 4947ffc80d Add code to emulate LDRSB (literal) Arm instruction. 
llvm-svn: 126789
 2011-03-01 22:25:17 +00:00
Caroline Tice 28c3fcccb2 Add code to emulate LDRSB (immediate) Arm instruction. 
llvm-svn: 126783
 2011-03-01 21:53:03 +00:00
Caroline Tice 4f0e5f8852 Add code to emulate LDRH (register) Arm instruction. 
llvm-svn: 126758
 2011-03-01 18:00:42 +00:00
Caroline Tice 6261d240e1 Add code to emulate LDRH (literal) Arm instruction. 
llvm-svn: 126709
 2011-02-28 23:15:24 +00:00
Caroline Tice adef8fb003 Add code to emulate LDRH (immediate, Thumb) arm instruction. 
llvm-svn: 126692
 2011-02-28 22:39:58 +00:00
Johnny Chen 699ac0e967 Add emulation for Encoding A1 of A8.6.97 MOV (register). 
llvm-svn: 126456
 2011-02-25 00:23:25 +00:00
Johnny Chen a517bae73c Fix typos in the opcode entries for branch instructions. 
llvm-svn: 126442
 2011-02-24 21:54:22 +00:00
Johnny Chen 3c970dc50d Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the attempt to 
switch to Jazelle state fails, thus treating BXJ as a BX operation.

llvm-svn: 126423
 2011-02-24 21:01:20 +00:00
Johnny Chen bf4afa8796 Add emulation methods for Bitwise Bit Clear (immediate and register) operations. 
llvm-svn: 126355
 2011-02-24 01:15:17 +00:00
Johnny Chen 132548df62 Add emulation methods for "SUB (immediate, Thumb)" and "SUB (immediate, ARM)" operations. 
llvm-svn: 126343
 2011-02-23 23:47:56 +00:00
Johnny Chen d88d96cac9 Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience function 
and rename the original ThumbImmScaled() function to ThumbImm7Scaled().

llvm-svn: 126335
 2011-02-23 21:24:25 +00:00
Johnny Chen 5278cd11ba Modify EmulateSUBSPImm() to handle the cases with generic Rd value instead of 
Rd == 13.  Add opcode entries for the generic "sub (sp minus immediate)" operations.

llvm-svn: 126293
 2011-02-23 01:55:07 +00:00
Johnny Chen 187b0e37c1 Add emulation methods for "SBC (immediate)" and "SBC (register)" operations. 
llvm-svn: 126283
 2011-02-23 01:01:21 +00:00
Greg Clayton 64195a2c8b Abtracted all mach-o and ELF out of ArchSpec. This patch is a modified form 
of Stephen Wilson's idea (thanks for the input Stephen!). What I ended up
doing was:
- Got rid of ArchSpec::CPU (which was a generic CPU enumeration that mimics
  the contents of llvm::Triple::ArchType). We now rely upon the llvm::Triple 
  to give us the machine type from llvm::Triple::ArchType.
- There is a new ArchSpec::Core definition which further qualifies the CPU
  core we are dealing with into a single enumeration. If you need support for
  a new Core and want to debug it in LLDB, it must be added to this list. In
  the future we can allow for dynamic core registration, but for now it is
  hard coded.
- The ArchSpec can now be initialized with a llvm::Triple or with a C string
  that represents the triple (it can just be an arch still like "i386").
- The ArchSpec can still initialize itself with a architecture type -- mach-o
  with cpu type and subtype, or ELF with e_machine + e_flags -- and this will
  then get translated into the internal llvm::Triple::ArchSpec + ArchSpec::Core.
  The mach-o cpu type and subtype can be accessed using the getter functions:
  
  uint32_t
  ArchSpec::GetMachOCPUType () const;

  uint32_t
  ArchSpec::GetMachOCPUSubType () const;
  
  But these functions are just converting out internal llvm::Triple::ArchSpec 
  + ArchSpec::Core back into mach-o. Same goes for ELF.

All code has been updated to deal with the changes.

This should abstract us until later when the llvm::TargetSpec stuff gets
finalized and we can then adopt it.

llvm-svn: 126278
 2011-02-23 00:35:02 +00:00
Johnny Chen 673badf292 Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs. 
llvm-svn: 126271
 2011-02-23 00:15:56 +00:00
Johnny Chen 7deb7422bc Add emulation methods for "RSC (immediate)" and "RSC (register)" operations. 
llvm-svn: 126267
 2011-02-23 00:07:09 +00:00
Johnny Chen 447c001048 Add emulation methods for "RSB (immediate)" and "RSB (register)". 
Plus add missing break stmts for "case" blocks.

llvm-svn: 126265
 2011-02-22 23:42:58 +00:00
Johnny Chen 5f88bcc16a Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() to ARMUtils.h. 
Use them within EmulateInstructionARM.cpp to save repetitive typing.

llvm-svn: 126247
 2011-02-22 21:17:52 +00:00
Johnny Chen 83a4ddd0cb Add "cmp<c>.w <Rn>, #<const>" emulation to EmulateCMPImm() method, 
and implement EmulateCMNImm() and EMulateCMNReg() methods.

llvm-svn: 126236
 2011-02-22 19:48:22 +00:00
Johnny Chen aebcfc86df Fix the 'variants' field of "CMN (immediate)" Encoding T1 entry, it should be ARMV6T2_ABOVE, not ARMvAll. 
llvm-svn: 126234
 2011-02-22 19:01:11 +00:00
Johnny Chen 01ceff367a Add ARM encoding entries for "CMN (immediate)" and "CMN (register)" operations. 
llvm-svn: 126179
 2011-02-22 02:00:12 +00:00
Johnny Chen 5ea119468a Add ARM encoding entries for "CMP (immediate)" and "CMP (register)" operations. 
Add ARM/Thumb encoding entries for "CMN (immediate)" and "CMN (register)" operations,
with the EmulateCMNImm()/Reg() methods not implemented yet for now.

llvm-svn: 126178
 2011-02-22 01:56:31 +00:00
Johnny Chen c2fa8fafde Add emulation methods for "MVN (immediate)" and "MVN (register)". 
llvm-svn: 126172
 2011-02-22 01:01:03 +00:00
Johnny Chen e69108a78f Add emulation methods for "EOR (Immediate)", "EOR (register)", 
"TEQ (immediate)", and "TEQ (register)" operations.

llvm-svn: 126160
 2011-02-21 23:42:44 +00:00
Johnny Chen 28c5882cb5 Add emulation methods for "TST (immediate)" and "TST (register)". 
Plus modified EmulateANDImm/Reg to delegate to TSTImm/Reg for Thumb2
32-bit instructions when Rd == '1111' and setflags is true.

llvm-svn: 126144
 2011-02-21 21:24:49 +00:00
Johnny Chen ce0dec7597 Make the helper method ReadCoreReg(uint32_t reg, bool *success) more generic 
which now handles R0-R12, SP, LR, as well as PC.  And refactored a lot of
calls to ReadRegisterUnsigned() to now funnel through ReadCoreReg(), instead.

llvm-svn: 126010
 2011-02-19 01:36:13 +00:00
Caroline Tice 55532be31f Add code to emulate LDRB (register) Arm instruction. 
llvm-svn: 125994
 2011-02-18 23:52:21 +00:00
Johnny Chen ce4e629fdf Add emulation methods for "ORR (immediate)" and "ORR (register)". 
Add Encoding T3 of "MOV (register)" to EmulateMOVRdRm() method and fixed
some bugs in EmulateMOVRdImm() and EmulateMOVRdRm() methods.

llvm-svn: 125992
 2011-02-18 23:41:11 +00:00
Caroline Tice 27d1032b60 Add code to emulate LDRB (literal) Arm instruction. 
llvm-svn: 125975
 2011-02-18 22:24:22 +00:00
Johnny Chen d1fd6963f5 Add emulation methods for "ADC (immediate)" and "ADC (register)". 
Plus add a helper method ReadCoreReg(uint32_t regnum, bool *success) to simplify
coding a bit.

llvm-svn: 125961
 2011-02-18 21:13:05 +00:00
Caroline Tice 489517c4a4 Add code to emulate LDRB (immediate, Thumb) instruction. 
llvm-svn: 125959
 2011-02-18 21:06:04 +00:00
Johnny Chen faba5dd4ae Add emulation methods for "AND (immediate)" and "AND (register)". 
Plus add macro definitions for APSR_C and APSR_V to simplify code.

llvm-svn: 125947
 2011-02-18 19:32:20 +00:00
Caroline Tice a1bf8db478 Add code to emulate LDR (register) Arm instruction. 
llvm-svn: 125945
 2011-02-18 18:52:37 +00:00
Johnny Chen f401d69c85 Fix typo. 
llvm-svn: 125812
 2011-02-18 01:26:39 +00:00
Johnny Chen fc9d00beb7 Add emulation of Encoding A1 "A8.6.6 ADD (register)" and "A8.6.5 ADD (immediate, ARM)". 
llvm-svn: 125809
 2011-02-18 01:22:22 +00:00
Caroline Tice 29c9b64096 Add code to emulate LDR (immediate,ARM) instruction. 
llvm-svn: 125808
 2011-02-18 00:55:53 +00:00
Johnny Chen ae147cafa9 Finished renamings to make the emulation method names consistent case-wise. 
llvm-svn: 125801
 2011-02-18 00:07:39 +00:00
Johnny Chen a18ae1ffde Some renamings to make the emulation method names consistent case-wise. 
llvm-svn: 125800
 2011-02-18 00:02:28 +00:00
Johnny Chen 2a7e05a3d7 Fix a bug in EmulateTB() (TBB, TBH) where the branch length should be "twice" 
the value of the byte/halfword returned from the table.

llvm-svn: 125793
 2011-02-17 23:27:44 +00:00
Johnny Chen 34dd9ba9c7 Refactoring. Abstracted the set flags operation into its own helper method 
WriteFlags() and renamed WriteCoreRegisterWithFlags() to WriteCoreRegOptionalFlags().
Modified the call sites to use the helper methods.

llvm-svn: 125788
 2011-02-17 22:37:12 +00:00
Johnny Chen fc5c19dec5 A8.6.6 ADD (register) 
Renamed EmulateAddRdnRm() to EmulateAddReg(), and added Encoding T1 to it.
Where Encoding T2 can potentially modify the PC, causing a brnach.

llvm-svn: 125782
 2011-02-17 22:03:29 +00:00
Johnny Chen 2789706059 Add EmulateTB() method to emulate "Table Branch Byte" and "Table Branch Halfword" 
operations for Thumb2.

llvm-svn: 125767
 2011-02-17 19:34:27 +00:00
Caroline Tice 032d2dd576 Add stubs for pseudocode functions "MemA[]" amd "MemU[]", corresponding to aligned 
and unaligned memory accesses.  The new stub functions are MemARead, MemAWrite,
MemURead, and MemUWrite.  At the moment these stubs just call ReadMemoryUnsigned or
WriteMemoryUnsigned, but we can fill them out further later if we decide we need
more accurate emulation of the memory system.

Replaced all the direct calls to ReadMemoryUnsigned and WriteMemoryUnsigned in
EmulateInstructionARM.cpp with calls to the appropriate new stub function.

llvm-svn: 125766
 2011-02-17 19:20:40 +00:00
Johnny Chen 0f60574fd7 Move Align(val, alignment) utility function to ARMUtils.h. 
llvm-svn: 125753
 2011-02-17 17:31:08 +00:00
Johnny Chen 0c64b5bbb6 Refactoring. Wrap the following pseudocode from the ARM Architecture Reference Manul: 
// if d == 15 then         // Can only occur for encoding A1
//     ALUWritePC(result); // setflags is always FALSE here
// else
//     R[d] = result;
//     if setflags then
//         APSR.N = result<31>;
//         APSR.Z = IsZeroBit(result);
//         APSR.C = carry;
//         // APSR.V unchanged

into a helper method WriteCoreRegisterWithFlags, and modified the existing methods
to take advantage of it.

Plus add two emulation methods (declaration only for now) for ORR (immediate) and ORR (register).

llvm-svn: 125701
 2011-02-17 01:35:27 +00:00
Johnny Chen 4890c85e0a Add emulation methods for ROR (immediate), ROR (register), and RRX. 
Turns out that they can be funneled through the helper methods
EmulateShiftImm()/ EmulateShiftReg() as well.

Modify EmulateShiftImm() to handle SRType_ROR and SRType_RRX.
And fix a typo in the impl of utility Shift_C() in ARMUtils.h.

llvm-svn: 125689
 2011-02-16 22:14:44 +00:00
Caroline Tice eaf2e4fdf1 Add code to emulate STRB (Thumb) instruction. 
llvm-svn: 125686
 2011-02-16 20:22:22 +00:00
Johnny Chen 14571f4b67 Add encoding entries for LSL (immediate and register) and LSR (immediate and register) to 
ARM and Thumb opcode tables.

llvm-svn: 125683
 2011-02-16 19:27:43 +00:00
Johnny Chen 22deaa5a1a Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), and LSR (register). 
Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR
delegate to the helper methods which take an extra ARM_ShifterType parameter.

The opcodes tables have not been updated yet to reflect these new entries.

llvm-svn: 125633
 2011-02-16 01:27:54 +00:00
Caroline Tice 5b5396ba77 Add documentation tags for LDM/STM instruction families. 
Add code to emulate STR (register) Arm instruction.

llvm-svn: 125623
 2011-02-16 00:33:43 +00:00
Johnny Chen 531dbfa5d8 A8.6.14 ASR (register) 
Add EmulateASRReg() Encodings T1, T2, and A1 to the opcodes tables.

llvm-svn: 125614
 2011-02-15 23:22:46 +00:00
Caroline Tice f199eea579 Add eContextRegisterLoad instruction emulation context. 
Add code to emulate STR (Immediate, Thumb) instruction.

llvm-svn: 125610
 2011-02-15 22:53:54 +00:00
Greg Clayton 514487e806 Made lldb_private::ArchSpec contain much more than just an architecture. It 
now, in addition to cpu type/subtype and architecture flavor, contains:
- byte order (big endian, little endian)
- address size in bytes
- llvm::Triple for true target triple support and for more powerful plug-in
  selection.

llvm-svn: 125602
 2011-02-15 21:59:32 +00:00
Johnny Chen f976896b83 Remove the "Register &reg" parameter from the BXWritePC(), LoadWritePC(), and ALUWritePC() 
methods of EmulateInstructionARM class.  The context data structure should provide sufficient
information already.

llvm-svn: 125596
 2011-02-15 21:08:58 +00:00
Johnny Chen 6f93f63955 Fix wrong mask and encoding for T2 of ASR (immediate). 
llvm-svn: 125593
 2011-02-15 20:14:02 +00:00
Johnny Chen a4afff97ad A8.6.14 ASR (immediate) 
Add EmulateASRImm() Encodings T1, T2, and A1 to the opcodes tables.

llvm-svn: 125592
 2011-02-15 20:10:55 +00:00
Caroline Tice 6e12e117d4 Add code to emulate STMIB Arm instruction. 
llvm-svn: 125580
 2011-02-15 18:42:15 +00:00
Caroline Tice 5e38f35fe3 Add code to emulate STMDB Arm instruction. 
Add some bit-mask fixes to code for getting register bits for various LDM and STM instructions.

llvm-svn: 125578
 2011-02-15 18:10:01 +00:00
Johnny Chen ef55e4c174 Remove the unnecessary assignment of m_inst_cpsr inside EvaluateInstruction(), 
because it's already been done within ReadInstruction().

llvm-svn: 125569
 2011-02-15 17:31:33 +00:00
Caroline Tice efb309619a Add code to emulate the STMDA Arm instruction. 
llvm-svn: 125542
 2011-02-15 00:19:42 +00:00
Johnny Chen 557520b996 Add missing logic (if BadReg(d) then UNPREDICTABLE;) for Encoding T2 of EmulateMovRdImm(). 
llvm-svn: 125533
 2011-02-14 23:33:58 +00:00
Johnny Chen 5623dc3559 Fix build warning (unused variable). 
llvm-svn: 125531
 2011-02-14 23:21:24 +00:00
Caroline Tice eccad4d005 - Rearrange instruction emulation contexts to use a union for the 
various types and numbers of arguments rather than trying to keep a
  constant number of arguments for all the types.

- Also create a Register type within the instructions, to hold
  register type and number.

- Modify EmulateInstructionArm.cpp to use the new register and context
  types in all the instruction emulation functions.

- Add code to emulate the STM Arm instruction.

llvm-svn: 125528
 2011-02-14 23:03:21 +00:00
Johnny Chen c3ba12d8e8 Add entries for EmulateMovRdImm() -- "MOV (immediate)" -- Encodings T1 & T2 into g_thumb_opcodes 
table.  Modify EmulateInstructionARM::EvaluateInstruction() so that if the cpsr has changed
during evaluate instruction, we flush out the change into m_inst_cpsr in preparation for the next
instruction.

llvm-svn: 125524
 2011-02-14 22:04:25 +00:00
Johnny Chen 86776147ff Add impl for EmulateMvnRdImm() -- "MVN (immediate)". Plus zero out the arg0 field of 
the context of eContextImmediate type, since the immediate value is known from the
argument value to WriteRegisterUnsigned() callback already.

llvm-svn: 125518
 2011-02-14 20:39:01 +00:00
Johnny Chen b3b8e0ffc2 Add entries for Encodings T1 and A1 of "MVN (immediate)" to g_arm_opcodes and g_thumb_opcodes 
tables.  The corresponding EmulateMvnRdImm() method impl is empty for now.

llvm-svn: 125425
 2011-02-12 01:27:26 +00:00
Johnny Chen 1173fbdc4b Add helper methods InITBlock() and LastInITBlock() to EmulateInstructionARM class 
instead of calling out to m_it_session.InITBlock()/LastInITBlock(), which simplifies
the coding a bit.

llvm-svn: 125421
 2011-02-12 00:50:05 +00:00
Johnny Chen a222c04588 Add EmulateBXRm() ("Branch and Exchange") to both g_arm_opcodes and g_thumb_opcodes table. 
llvm-svn: 125418
 2011-02-12 00:10:51 +00:00
Caroline Tice 7b37670d56 - Add three more instruction contexts to EmulateInstruction: 
eContextAdjustBaseRegister, eContextRegisterStore and
eContextWriteMemoryRandomBits.

- Implement a version of WriteBits32UnknownToMemory for writing to memory.

- Modify EmulateLDM, EmulateLDMDA, EmulateLDMDB and EmulateLDMIB to use the
eContextAdjustBaseRegister context when appropriate.

- Add code to emulate the STM/STMIA/STMEA Arm instruction.

llvm-svn: 125414
 2011-02-11 22:49:54 +00:00
Johnny Chen a61541663c Add EmulateCmpRnRm() for Encodings T1 & T2 to the g_thumb_opcodes table to emulate 
CMP (register) operations.

llvm-svn: 125413
 2011-02-11 21:53:58 +00:00
Johnny Chen c6ca7bb67a Rearraned some emulate instruction entries under the appropriate category. 
llvm-svn: 125405
 2011-02-11 21:23:32 +00:00
Johnny Chen f1075ce0e6 Handle the case of interworking branch for EmulateLDMDA. 
llvm-svn: 125392
 2011-02-11 19:37:03 +00:00
Johnny Chen 298251cd9b Add Thumb2 LDR (literal) instruction into the g_thumb_opcodes table. 
Change the method name from *LDRRdPCRelative to *LDRRtPCRelative to be compliant
with the ARM Arch Manual which uses Rt for the destination register.

llvm-svn: 125390
 2011-02-11 19:12:30 +00:00
Johnny Chen bce7ad6b48 Fix build. 
llvm-svn: 125379
 2011-02-11 18:11:22 +00:00
Caroline Tice 485b4d8352 Add new instruction context, eContextWriteRegisterRandomBits. 
Add new utility function, WriteBits32Unknown

Modify the LDM* instruction emulation functions to call WriteBits32Unknown.
Add missing overview comments to the LDM* instruction emulation functions.

Add code to emulate LDMDA Arm instruction.

llvm-svn: 125377
 2011-02-11 17:59:55 +00:00
Johnny Chen c7af6fe3bd Add an entry for CMP (immediate) (Encoding T1) to the g_thumb_opcodes table. 
llvm-svn: 125333
 2011-02-11 02:02:56 +00:00
Johnny Chen 37c48b02a4 Add a helper method AddWithCarry() to the EmulateInstructionARM class. 
llvm-svn: 125329
 2011-02-11 01:29:53 +00:00
Johnny Chen c843a78efc Namings are important. Renamed Bits32(const uint32_t val, uint32_t bit) to Bit32(val, bit) and 
SetBits32(uint32_t &bits, uint32_t bit, uint32_t val) to SetBit32(bits, bit, val).

llvm-svn: 125312
 2011-02-10 21:39:01 +00:00
Johnny Chen 101f6efb8a Some refactorings to use the convenience function: Bits32(const uint32_t value, const uint32_t bit). 
llvm-svn: 125303
 2011-02-10 19:54:05 +00:00
Johnny Chen 992b48c4be Add some comment markers. 
llvm-svn: 125302
 2011-02-10 19:40:42 +00:00
Johnny Chen 0cfda5bbb5 Add a generic EmulateMovRdRm() method and modify/add entries to the g_thumb_opcodes 
table.  Also add some more defines and convenience functions.

llvm-svn: 125300
 2011-02-10 19:29:03 +00:00
Johnny Chen 77224a5422 Rearrange the order of g_thumb_opcodes entries. 
llvm-svn: 125295
 2011-02-10 18:13:23 +00:00
Johnny Chen cc13e4c62e Add EmulateLDRRtRnImm() for EncodingT1 of LDR (immediate, Thumb) to the g_thumb_opcodes table, 
and a helper method UnalignedSupport().

llvm-svn: 125258
 2011-02-10 01:52:38 +00:00
Johnny Chen 1cabebe7bc Add a new member variable m_new_inst_cpsr to catch the to-be-updated state 
of the CPSR during the course of executing an opcode, and modified SelectInstrSet()
to update this variable instead of the original m_inst_cpsr, which should be
the cached copy of the CPSR at the beginning of executing the opcode.

llvm-svn: 125244
 2011-02-09 23:59:17 +00:00
Johnny Chen edf55ae52a Add EmulateAddRdnRm() for EncodingT2 of ADD(register) to the g_thumb_opcodes table, 
and a helper method ALUWritePC(Context&, uint32_t).

llvm-svn: 125241
 2011-02-09 23:43:29 +00:00
Johnny Chen 0ce4a83c44 Modified existing Emulate* methods to call LoadWritePC(context, data) where appropriate to 
effect an interworking branch if the ArchVersion() is ARMv5T and above.

llvm-svn: 125227
 2011-02-09 22:02:17 +00:00
Johnny Chen 8bba644bf4 Modified EmulatePop impl to use the helper method LoadWritePC(context, data) since if PC 
is in the list of registers to be load and we're in ARMv5T and above, this is an interworking branch.

llvm-svn: 125212
 2011-02-09 19:30:49 +00:00
Johnny Chen cc707657f9 If the CPSR is changed due to switching between ARM and Thumb ISETSTATE, 
we want to record it and issue a WriteRegister callback so the clients
can track the mode changes accordingly.

llvm-svn: 125209
 2011-02-09 19:11:32 +00:00
Greg Clayton 000aeb89ae Patch from Kirk Beitz to make things compile on MinGW minus the putenv part. 
llvm-svn: 125199
 2011-02-09 17:41:27 +00:00
Johnny Chen 7eaacc517b Add some helper methods to the EmulateInstructionARM class as a first step in the 
refactorings of EmulateInstructionARM.cpp file, which will be modified later to
take advantage of these helper methods.

llvm-svn: 125148
 2011-02-09 01:00:31 +00:00
Caroline Tice 123b89b67f Add code to emulate the LDMIB Arm instruction. 
Modify code for LDM and LDMDB instructions to only
create one context and to reuse it, rather than 
creating multiple contexts.

llvm-svn: 125139
 2011-02-08 23:56:10 +00:00
Johnny Chen 108a363318 Fix typos. 
llvm-svn: 125138
 2011-02-08 23:49:37 +00:00
Johnny Chen 03feace9d0 Add EmulateCB() entry to the g_thumb_opcodes table to represent "Compare and Branch 
on NonZero and Compare and Branch on Zero" operations.

llvm-svn: 125134
 2011-02-08 23:21:57 +00:00
Caroline Tice cdb58e1236 Add code to emulate LDMDB Arm instruction. 
llvm-svn: 125133
 2011-02-08 23:16:02 +00:00
Caroline Tice 7aa01cfd64 Add code to emulate the LDM ARM instruction. 
llvm-svn: 125118
 2011-02-08 22:24:38 +00:00
Johnny Chen 181376f29f Add missing implementation for "BL, BLX (immediate)" Encoding T1 and an entry for "bl <label>" 
into g_thumb_opcodes table.

llvm-svn: 125112
 2011-02-08 20:36:34 +00:00
Johnny Chen 86e48b6940 Add missing implementation for "BL, BLX (immediate)" Encoding A1. 
llvm-svn: 125103
 2011-02-08 18:58:31 +00:00
Johnny Chen a3990398a3 Add implementation for EmulateInstructionARM::EmulateB() and fixed two typos in g_thumb_opcodes 
as pointed out By Caroline.  Refactored a little bit by adding two new helper methods to the
EmulateInstructionARM class:

o BranchWritePC()
o BXWritePC()

llvm-svn: 125059
 2011-02-08 00:06:35 +00:00
Johnny Chen 05a975d777 Add EmulateInstructionARM::EmulateB entries to the g_arm_opcodes and g_thumb_opcodes 
tables.  EmulateB() has empty impl. and needs to be filled in later.

llvm-svn: 125048
 2011-02-07 20:11:47 +00:00
Johnny Chen 56902044a7 Handle the thumb branch instructions which have their cond bits embedded in the instruction stream. 
llvm-svn: 124925
 2011-02-05 01:39:52 +00:00
Johnny Chen 6e2acff0be Add EmulateInstructionARM::EmulateIT() to the g_thumb_opcodes table, 
to represent the the 'If Then' instruction which makes up to four following
instructions (the IT block)conditional.

Hook up ITSession utility class as a member variable of EmulateInstructionARM.

llvm-svn: 124915
 2011-02-05 00:46:10 +00:00
Johnny Chen ea745e86c8 Add a utility class ITSession to maintain the ITState for the Thumb ISA. 
llvm-svn: 124906
 2011-02-04 23:02:47 +00:00
Johnny Chen b52193787d Add EmulateInstructionARM::EmulateSVC() to the g_arm_opcodes and g_thumb_opcodes tables, 
to represent the supervisor call instruction (previosuly software interrupt).

llvm-svn: 124840
 2011-02-04 00:40:18 +00:00
Johnny Chen d07a57f222 Add EmulateBLXImmediate() and EmulateBLXRm() to the g_arm_opcodes and g_thumb_opcodes tables, 
which represent "bl <label>", "blx <label>", and "blx <Rm>" instructions.

llvm-svn: 124710
 2011-02-02 01:13:56 +00:00
Johnny Chen 2684ccccda Remove the 'lldb_private::' namespace resolution operator. 
llvm-svn: 124671
 2011-02-01 18:51:48 +00:00
Johnny Chen 3d9011d6dd Add EmulateVPOP() to the g_arm_opcodes and g_thumb_opcodes tables, which represents 
an operation to load multiple extension registers from the stack.

llvm-svn: 124670
 2011-02-01 18:35:28 +00:00
Greg Clayton c46f94d490 Cleaned up the EmulateInstructionARM to have the evaluate instruction 
callbacks use member functions.

llvm-svn: 124636
 2011-02-01 00:49:32 +00:00
Greg Clayton c1dfd93e1e Made the EmulateInstruction class into a plug-in interface and moved the 
source files around into the places they need to go.

llvm-svn: 124631
 2011-02-01 00:04:43 +00:00