Evan Cheng
|
6cfbe61361
|
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
llvm-svn: 76925
|
2009-07-24 00:53:56 +00:00 |
|
David Goodwin
|
cdd405d804
|
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
llvm-svn: 76919
|
2009-07-24 00:16:18 +00:00 |
|
David Goodwin
|
6deba28c6f
|
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
llvm-svn: 76883
|
2009-07-23 17:06:46 +00:00 |
|
Evan Cheng
|
151b23d043
|
Fix a regression from 76124. Thumb1 instructions default to S bit being true.
llvm-svn: 76374
|
2009-07-19 19:16:46 +00:00 |
|
Anton Korobeynikov
|
c5df7e2dc1
|
Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
llvm-svn: 76124
|
2009-07-16 23:26:06 +00:00 |
|
Evan Cheng
|
3b88dd6900
|
Move isPredicated from .cpp to .h
llvm-svn: 75217
|
2009-07-10 01:38:27 +00:00 |
|
David Goodwin
|
03ab0bbb24
|
Generalize opcode selection in ARMBaseRegisterInfo.
llvm-svn: 75036
|
2009-07-08 20:28:28 +00:00 |
|
David Goodwin
|
af7451b674
|
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
llvm-svn: 75010
|
2009-07-08 16:09:28 +00:00 |