473e34782d
[Hexagon] Simplify boolean expression
...
Patch by Richard
http://reviews.llvm.org/D8523
llvm-svn: 232955
2015-03-23 16:01:03 +00:00
4d0f35a901
Remove the target independent TargetMachine::getSubtarget and
...
TargetMachine::getSubtargetImpl routines.
This keeps the target independent code free of bare subtarget
calls while the remainder of the backends are migrated, or not
if they don't wish to support per-function subtargets as would
be needed for function multiversioning or LTO of disparate
cpu subarchitecture types, e.g.
clang -msse4.2 -c foo.c -emit-llvm -o foo.bc
clang -c bar.c -emit-llvm -o bar.bc
llvm-link foo.bc bar.bc -o baz.bc
llc baz.bc
and get appropriate code for what the command lines requested.
llvm-svn: 232885
2015-03-21 04:22:23 +00:00
23a7d1e6f4
Make the Hexagon ISelDAGToDAG pass set the subtarget dynamically
...
on each runOnMachineFunction invocation.
llvm-svn: 232874
2015-03-21 03:12:59 +00:00
421133470f
[Hexagon] Add support for vector instructions
...
llvm-svn: 232728
2015-03-19 16:33:08 +00:00
c6f19333cf
[Hexagon] ENDLOOP is a non-reversible conditional branch
...
llvm-svn: 232725
2015-03-19 15:18:57 +00:00
105270f68c
Add a default implementation of createObjectStreamer.
...
This removes duplicated code from backends that don't need to do anything
fancy.
llvm-svn: 232658
2015-03-18 19:08:20 +00:00
36ccfa5779
[Hexagon] Use pseudo-instructions for true/false predicate values
...
llvm-svn: 232657
2015-03-18 19:07:53 +00:00
7a9cd80f54
Revert "[Hexagon] Use pseudo-instructions for true/false predicate values"
...
This reverts r232650.
Missed a piece of code in the previous commit.
llvm-svn: 232656
2015-03-18 18:50:06 +00:00
5d7e8fcd52
[Hexagon] Use pseudo-instructions for true/false predicate values
...
llvm-svn: 232650
2015-03-18 17:20:51 +00:00
47ab1f2007
[Hexagon] Intrinsics for circular and bit-reversed loads and stores
...
llvm-svn: 232645
2015-03-18 16:23:44 +00:00
78cc36fed7
[Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranch
...
llvm-svn: 232643
2015-03-18 15:56:43 +00:00
8c1cab9a27
Generate bit manipulation instructions on Hexagon
...
llvm-svn: 232577
2015-03-18 00:43:46 +00:00
d89581c5e7
Remove unneeded selection functions from HexagonISelDAGToDAG
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- SelectSelect, and
- SelectTruncate
llvm-svn: 232569
2015-03-17 23:54:48 +00:00
ae14e7bf99
Selection DAG preprocessing on Hexagon
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Simplify: (or (select c x 0) z) -> (select c (or x z) z)
(or (select c 0 y) z) -> (select c z (or y z))
llvm-svn: 232553
2015-03-17 21:47:16 +00:00
49f643c472
Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
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Summary:
But still handle them the same way since I don't know how they differ on
this target.
No functional change intended.
Reviewers: kparzysz, adasgupt
Reviewed By: kparzysz, adasgupt
Subscribers: colinl, llvm-commits
Differential Revision: http://reviews.llvm.org/D8204
Like for the PowerPC target, I've had to add 'i' to the constraint mappings in
order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically
been treated as a memory constraint.
llvm-svn: 232480
2015-03-17 14:37:39 +00:00
f696df1148
Pass in a "const Triple &T" instead of a raw StringRef.
...
llvm-svn: 232429
2015-03-16 22:29:29 +00:00
9bcf2fcb89
Remove unused argument. NFC.
...
llvm-svn: 232428
2015-03-16 22:06:15 +00:00
e8a570562d
Revert r232374: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
...
2007-12-17-InvokeAsm.ll fails on the buildbot but not on my own system. Will investigate.
llvm-svn: 232376
2015-03-16 14:21:22 +00:00
b2d0c02451
[hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
...
Summary:
But still handle them the same way since I don't know how they differ on
this target.
No functional change intended.
Reviewers: kparzysz, adasgupt
Reviewed By: kparzysz, adasgupt
Subscribers: colinl, llvm-commits
Differential Revision: http://reviews.llvm.org/D8204
llvm-svn: 232374
2015-03-16 13:54:19 +00:00
bf5b80f5f9
Make each target map all inline assembly memory constraints to InlineAsm::Constraint_m. NFC.
...
Summary:
This is instead of doing this in target independent code and is the last
non-functional change before targets begin to distinguish between
different memory constraints when selecting code for the ISD::INLINEASM
node.
Next, each target will individually move away from the idea that all
memory constraints behave like 'm'.
Subscribers: jholewinski, llvm-commits
Differential Revision: http://reviews.llvm.org/D8173
llvm-svn: 232373
2015-03-16 13:13:41 +00:00
60f1db0525
Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints.
...
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.
This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break
anything.
The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate
Constraint_* values.
PR22883 was caused the matching operands copying the whole of the operand flags
for the matched operand. This included the constraint id which needed to be
replaced with the operand number. This has been fixed with a conversion
function. Following on from this, matching operands also used the operand
number as the constraint id. This has been fixed by looking up the matched
operand and taking it from there.
llvm-svn: 232165
2015-03-13 12:45:09 +00:00
e78e52ba9b
Revert "r232027 - Add infrastructure for support of multiple memory constraints"
...
This (r232027) has caused PR22883; so it seems those bits might be used by
something else after all. Reverting until we can figure out what else to do.
Original commit message:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.
This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.
The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.
llvm-svn: 232093
2015-03-12 20:09:39 +00:00
a29622a8c5
Remove unused complex patterns for addressing modes on Hexagon.
...
llvm-svn: 232057
2015-03-12 16:44:50 +00:00
41c072e63b
Add infrastructure for support of multiple memory constraints.
...
Summary:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.
This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.
The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.
Reviewers: hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, jholewinski, llvm-commits
Differential Revision: http://reviews.llvm.org/D8171
llvm-svn: 232027
2015-03-12 11:00:48 +00:00
234a1ec404
Remove some unnecessary forward declarations and put a couple more
...
where they're supposed to reside.
llvm-svn: 232014
2015-03-12 06:07:16 +00:00
325297c101
Fix build break introduced in r231992
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llvm-svn: 231996
2015-03-12 00:49:13 +00:00
6d5a4b5dcd
Eliminate constant-extender profitability checks from Hexagon isel
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llvm-svn: 231992
2015-03-12 00:19:59 +00:00
93e1ea167e
Move the DataLayout to the generic TargetMachine, making it mandatory.
...
Summary:
I don't know why every singled backend had to redeclare its own DataLayout.
There was a virtual getDataLayout() on the common base TargetMachine, the
default implementation returned nullptr. It was not clear from this that
we could assume at call site that a DataLayout will be available with
each Target.
Now getDataLayout() is no longer virtual and return a pointer to the
DataLayout member of the common base TargetMachine. I plan to turn it into
a reference in a future patch.
The only backend that didn't have a DataLayout previsouly was the CPPBackend.
It now initializes the default DataLayout. This commit is NFC for all the
other backends.
Test Plan: clang+llvm ninja check-all
Reviewers: echristo
Subscribers: jfb, jholewinski, llvm-commits
Differential Revision: http://reviews.llvm.org/D8243
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231987
2015-03-12 00:07:24 +00:00
5f141b03fa
Remove useMachineScheduler and replace it with subtarget options
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that control, individually, all of the disparate things it was
controlling.
At the same time move a FIXME in the Hexagon port to a new
subtarget function that will enable a user of the machine
scheduler to avoid using the source scheduler for pre-RA-scheduling.
The FIXME would have this removed, but involves either testcase
changes or adding -pre-RA-sched=source to a few testcases.
llvm-svn: 231980
2015-03-11 22:56:10 +00:00
7af9528747
Have getCalleeSavedRegs take a non-null MachineFunction all the
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time. The target independent code was passing in one all the
time and targets weren't checking validity before using. Update
a few calls to pass in a MachineFunction where necessary.
llvm-svn: 231970
2015-03-11 21:41:28 +00:00
c4d3140524
Remove subtarget dependence from HexagonRegisterInfo.
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llvm-svn: 231887
2015-03-10 23:45:55 +00:00
0169e42c3b
Remove the use of the subtarget in MCCodeEmitter creation and
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update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.
llvm-svn: 231861
2015-03-10 22:03:14 +00:00
bdc6c83d24
[Hexagon] Adding frame index + add load/store patterns.
...
llvm-svn: 231850
2015-03-10 21:24:13 +00:00
3901c066e0
[Hexagon] Simplifying deallocret definitions.
...
llvm-svn: 231847
2015-03-10 21:12:32 +00:00
4e90d2136f
[Hexagon] Separating InstHexagon from OpcodeHexagon.
...
llvm-svn: 231844
2015-03-10 20:56:22 +00:00
60a99e66a0
[Hexagon] Adding nodes for PIC support.
...
llvm-svn: 231829
2015-03-10 20:04:44 +00:00
092d9c18a8
[Hexagon] Adding DuplexInst instruction format and duplex class defs.
...
llvm-svn: 231828
2015-03-10 19:53:14 +00:00
3b6747df13
[Hexagon] Adding nodes for vector insert/extract lowering.
...
llvm-svn: 231825
2015-03-10 19:40:03 +00:00
ee776452f9
[Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.
...
llvm-svn: 231824
2015-03-10 19:29:53 +00:00
9d1f2dfec7
Hexagon: Remove unused InstrMapping.
...
llvm-svn: 231809
2015-03-10 18:19:16 +00:00
4683395808
Hexagon: Remove pass that does nothing at all
...
llvm-svn: 231791
2015-03-10 15:06:38 +00:00
f00fd1f087
Removing dead code to silence warning C4060: switch statement contains no 'case' or 'default' labels; NFC.
...
llvm-svn: 231785
2015-03-10 13:56:28 +00:00
fa79110cc7
[Hexagon] Removing unused patterns.
...
llvm-svn: 231723
2015-03-09 23:08:46 +00:00
7b1799c7f8
[Hexagon] Use single tailcall pseudoinst and fix checking for label jumping versus tail calling.
...
llvm-svn: 231713
2015-03-09 22:05:21 +00:00
2efa2d01d7
[Hexagon] Reapply r231699. Remove assumption that second operand is an immediate when checking if A2_tfrsi is combinable.
...
llvm-svn: 231710
2015-03-09 21:48:13 +00:00
ed853397c6
[Hexagon] Reverting r231699
...
llvm-svn: 231703
2015-03-09 21:19:02 +00:00
8c4dfaa13b
[Hexagon] Updating constant set to simpler versions.
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llvm-svn: 231699
2015-03-09 20:33:12 +00:00
7bd1f7cb58
Remove the remaining uses of abs64 and nuke it.
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std::abs works just fine and we're already using it in many places. NFC intended.
llvm-svn: 231696
2015-03-09 20:20:16 +00:00
542510925b
[Hexagon] Removing old halfword codegen instructions and updating const32/64 splitting.
...
llvm-svn: 231695
2015-03-09 20:11:02 +00:00
96bfaa9766
[Hexagon] Eliminating immediate condition set.
...
llvm-svn: 231693
2015-03-09 19:57:18 +00:00
d46aeffc54
[Hexagon] Removing TFR_condset_ir/TFR_condset_ri modeling.
...
llvm-svn: 231689
2015-03-09 19:31:25 +00:00
63adf969a5
[Hexagon] Changing AddrFI back to ADDRri to address test issue.
...
llvm-svn: 231687
2015-03-09 18:57:33 +00:00
bd8d0f3108
[Hexagon] Adding PackHL nodes and some missing modeling instructions and patterns
...
llvm-svn: 231678
2015-03-09 18:34:05 +00:00
f1362f6196
ArrayRefize memory operand folding. NFC.
...
llvm-svn: 230846
2015-02-28 12:04:00 +00:00
11e4df73c8
getRegForInlineAsmConstraint wants to use TargetRegisterInfo for
...
a lookup, pass that in rather than use a naked call to getSubtargetImpl.
This involved passing down and around either a TargetMachine or
TargetRegisterInfo. Update all callers/definitions around the targets
and SelectionDAG.
llvm-svn: 230699
2015-02-26 22:38:43 +00:00
23a3a7c871
Remove an argument-less call to getSubtargetImpl from TargetLoweringBase.
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This required plumbing a TargetRegisterInfo through computeRegisterProperties
and into findRepresentativeClass which uses it for register class
iteration. This required passing a subtarget into a few target specific
initializations of TargetLowering.
llvm-svn: 230583
2015-02-26 00:00:24 +00:00
3d61760bd6
Fix a warning on HexagonMCCodeEmitter::MCII. [-Wunused-private-field]
...
llvm-svn: 230170
2015-02-22 09:58:29 +00:00
3b6b7ca2bc
CodeGen: convert CCState interface to using ArrayRefs
...
Everyone except R600 was manually passing the length of a static array
at each callsite, calculated in a variety of interesting ways. Far
easier to let ArrayRef handle that.
There should be no functional change, but out of tree targets may have
to tweak their calls as with these examples.
llvm-svn: 230118
2015-02-21 02:11:17 +00:00
1174fea31c
[Hexagon] Moving remaining methods off of HexagonMCInst in to HexagonMCInstrInfo and eliminating HexagonMCInst class.
...
llvm-svn: 229914
2015-02-19 21:10:50 +00:00
745c4710db
[Hexagon] Moving more functions off of HexagonMCInst and in to HexagonMCInstrInfo.
...
llvm-svn: 229903
2015-02-19 19:49:27 +00:00
af304e5192
[Hexagon] Creating HexagonMCInstrInfo namespace as landing zone for static functions detached from HexagonMCInst.
...
llvm-svn: 229885
2015-02-19 19:00:00 +00:00
f08a3ccf50
[Hexagon] Removing static variable holding MCInstrInfo.
...
llvm-svn: 229872
2015-02-19 17:38:39 +00:00
f9a1897c72
Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition.
...
llvm-svn: 229340
2015-02-15 22:54:22 +00:00
30d69c2e36
[PM] Remove the old 'PassManager.h' header file at the top level of
...
LLVM's include tree and the use of using declarations to hide the
'legacy' namespace for the old pass manager.
This undoes the primary modules-hostile change I made to keep
out-of-tree targets building. I sent an email inquiring about whether
this would be reasonable to do at this phase and people seemed fine with
it, so making it a reality. This should allow us to start bootstrapping
with modules to a certain extent along with making it easier to mix and
match headers in general.
The updates to any code for users of LLVM are very mechanical. Switch
from including "llvm/PassManager.h" to "llvm/IR/LegacyPassManager.h".
Qualify the types which now produce compile errors with "legacy::". The
most common ones are "PassManager", "PassManagerBase", and
"FunctionPassManager".
llvm-svn: 229094
2015-02-13 10:01:29 +00:00
5f6a907288
MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line with countTrailingZeros
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Update all callers.
llvm-svn: 228930
2015-02-12 15:35:40 +00:00
404d5b242d
[Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class.
...
llvm-svn: 228708
2015-02-10 16:59:36 +00:00
36a036909c
Fix the clang -Werror build (-Wunused-variable)
...
llvm-svn: 228635
2015-02-10 00:16:36 +00:00
328b1633d7
[Hexagon] Adding missing load instructions and removing an unused multiclass parameter.
...
llvm-svn: 228630
2015-02-09 23:45:24 +00:00
4282e7cffd
[Hexagon] Factoring classes out of some load patterns and deleting some unused ones.
...
llvm-svn: 228627
2015-02-09 23:05:44 +00:00
4fd203d3e1
[Hexagon] Removing more V4 predicates since V4 is the required minimum.
...
llvm-svn: 228614
2015-02-09 21:56:37 +00:00
641c24b9bf
[Hexagon] Removing v2-4 flags. V4 is the minimum supported version.
...
llvm-svn: 228605
2015-02-09 21:07:35 +00:00
955c4ff9c3
[Hexagon] Factoring classes out of store patterns.
...
llvm-svn: 228602
2015-02-09 20:33:46 +00:00
ab5a8d6070
[Hexagon] Formatting v5 TD file. Removing commented defs.
...
llvm-svn: 228598
2015-02-09 20:03:42 +00:00
38e6689276
[Hexagon] Cleaning up definition formatting.
...
llvm-svn: 228593
2015-02-09 19:24:44 +00:00
6e3e62fd13
[Hexagon] Renaming v4 compare-and-jump instructions.
...
llvm-svn: 228349
2015-02-05 22:03:32 +00:00
6b3aac8ad9
[Hexagon] Deleting unused patterns.
...
llvm-svn: 228348
2015-02-05 21:43:56 +00:00
de68b66b4d
[Hexagon] Simplifying and formatting several patterns. Changing a pattern multiply to be expanded.
...
llvm-svn: 228347
2015-02-05 21:13:25 +00:00
99c5ce1ce4
[Hexagon] Factoring a class out of some store patterns, deleting unused definitions and reformatting some patterns.
...
llvm-svn: 228345
2015-02-05 20:38:58 +00:00
d40bb5353d
[Hexagon] Factoring out a class for immediate transfers and cleaning up formatting.
...
llvm-svn: 228343
2015-02-05 20:08:52 +00:00
b882f2b5cf
[Hexagon] Renaming Y2_barrier. Fixing issues where doubleword variants of instructions can't be newvalue producers.
...
llvm-svn: 228330
2015-02-05 18:56:28 +00:00
27d50073b3
[Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting.
...
llvm-svn: 228326
2015-02-05 18:38:08 +00:00
f297dbed48
[Hexagon] Renaming A2_addi and formatting.
...
llvm-svn: 228318
2015-02-05 17:49:13 +00:00
a66cf6f2df
[Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by default and remove explicitly setting it.
...
llvm-svn: 228316
2015-02-05 17:32:17 +00:00
ceebe8659b
[Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs.
...
llvm-svn: 228238
2015-02-05 00:10:16 +00:00
9cb9078ccf
[Hexagon] Updating load extend to i64 patterns.
...
llvm-svn: 228237
2015-02-04 23:55:16 +00:00
712d5c393b
[Hexagon] Cleaning up i1 load and extension patterns.
...
llvm-svn: 228232
2015-02-04 23:27:48 +00:00
90a91bbf43
[Hexagon] Simplifying more load and store patterns and using new addressing patterns.
...
llvm-svn: 228231
2015-02-04 23:23:16 +00:00
ad13d4e8a6
[Hexagon] Simplifying some load and store patterns.
...
llvm-svn: 228227
2015-02-04 23:10:21 +00:00
68292c96da
[Hexagon] Converting absolute-address load patterns to use AddrGP.
...
llvm-svn: 228225
2015-02-04 22:54:51 +00:00
8bf5de10c3
[Hexagon] Converting atomic store/load to use AddrGP addressing.
...
llvm-svn: 228223
2015-02-04 22:40:36 +00:00
5149135369
[Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.
...
llvm-svn: 228220
2015-02-04 22:36:28 +00:00
987b0943c8
[Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them.
...
llvm-svn: 228184
2015-02-04 20:38:01 +00:00
86abe35ceb
[Hexagon] Replacing some load patterns with cleaner versions.
...
llvm-svn: 228169
2015-02-04 19:05:32 +00:00
f856dcb75e
[Hexagon] Adding missing isCodeGenOnly = 0
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llvm-svn: 228160
2015-02-04 18:11:32 +00:00
c0434466e4
[Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet.
...
llvm-svn: 228158
2015-02-04 17:52:06 +00:00
7d971056ed
[Hexagon] Adding encoding information for absolute-set stores.
...
llvm-svn: 228154
2015-02-04 17:24:04 +00:00
0eb9727d42
[Hexagon] Adding encoding bits for indirect long load instructions.
...
llvm-svn: 228152
2015-02-04 16:56:46 +00:00
585316cb41
[Hexagon] Revert change to isCodeGenOnly = 1 in r228080
...
llvm-svn: 228082
2015-02-04 00:09:23 +00:00
510ba0c661
[Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts.
...
llvm-svn: 228080
2015-02-04 00:07:26 +00:00
e4101e2c9e
[Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.
...
llvm-svn: 228050
2015-02-03 22:09:51 +00:00
cd9cb023d7
[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.
...
llvm-svn: 228026
2015-02-03 20:40:52 +00:00
cf7248bcaf
[Hexagon] Updating XTYPE/PRED intrinsics.
...
llvm-svn: 228019
2015-02-03 19:43:59 +00:00
e5daf3abfe
[Hexagon] Updating XTYPE/PERM intrinsics.
...
llvm-svn: 228015
2015-02-03 19:36:59 +00:00
99cc7c1070
[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests.
...
llvm-svn: 228010
2015-02-03 19:15:11 +00:00
a6632452be
[Hexagon] Converting complex number intrinsics and adding tests.
...
llvm-svn: 227995
2015-02-03 18:16:28 +00:00
cdba4e1bcc
[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.
...
llvm-svn: 227993
2015-02-03 18:01:45 +00:00
36fe028a2a
Only access TLOF via the TargetMachine, not TargetLowering.
...
llvm-svn: 227949
2015-02-03 07:22:52 +00:00
8f276db622
Define a runOnMachineFunction for the Hexagon AsmPrinter and
...
use it to initialize the subtarget.
llvm-svn: 227948
2015-02-03 06:40:22 +00:00
d5c235dab8
Use the cached subtarget on the MachineFunction.
...
llvm-svn: 227885
2015-02-02 22:40:56 +00:00
6905059e80
Remove dead header.
...
llvm-svn: 227884
2015-02-02 22:40:54 +00:00
57931fca07
Remove dead code in the HexagonMCInst classes. This also fixes
...
a layering violation in the port and removes calls to getSubtargetImpl.
llvm-svn: 227883
2015-02-02 22:40:53 +00:00
d21486dfe0
80-col fixup.
...
llvm-svn: 227882
2015-02-02 22:40:51 +00:00
2b7707c07e
Remove dead code in the HexagonMCInst classes. This also fixes
...
a layering violation in the port and removes calls to getSubtargetImpl.
llvm-svn: 227880
2015-02-02 22:28:48 +00:00
97a2a39695
80-col fixup.
...
llvm-svn: 227879
2015-02-02 22:28:46 +00:00
6098f150a1
Remove unused class variables and update all callers/uses from
...
the HexagonSplitTFRCondSet pass. Use the subtarget off the machine
function at the same time.
llvm-svn: 227878
2015-02-02 22:28:44 +00:00
01f875e859
Migrate the HexagonSplitConst32AndConst64 pass from TargetMachine
...
based getSubtarget to the one cached on the MachineFunction.
Remove unused class variables and update all callers/uses.
llvm-svn: 227874
2015-02-02 22:11:43 +00:00
0fef34e3fc
Remove #if'd code and update comment.
...
llvm-svn: 227873
2015-02-02 22:11:42 +00:00
f8b8e4a3fb
Move HexagonMachineScheduler to use the subtarget off of the
...
MachineFunction and update all uses accordingly including
VLIWResourceModel.
llvm-svn: 227872
2015-02-02 22:11:40 +00:00
d737b76b63
Cache and use the subtarget that owns the target lowering.
...
llvm-svn: 227871
2015-02-02 22:11:36 +00:00
202f22bbda
Migrate HexagonISelDAGToDAG to setting a subtarget pointer during
...
runOnMachineFunction. Update all uses of the Subtarget accordingly.
llvm-svn: 227840
2015-02-02 19:22:03 +00:00
90295c9c63
Use the getSubtarget call off of the MachineFunction rather than
...
the TargetMachine.
llvm-svn: 227839
2015-02-02 19:22:01 +00:00
2c44f43ebe
Remove unused class variables and update calls to get the subtarget
...
off of the machine function.
llvm-svn: 227837
2015-02-02 19:05:28 +00:00
d55c7c6670
Sink queries into asserts since the variable is unused otherwise.
...
llvm-svn: 227836
2015-02-02 18:58:24 +00:00
241a9e8db2
Update CMake build for removed files.
...
llvm-svn: 227834
2015-02-02 18:52:49 +00:00
6ff7ed6446
Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction
...
and remove unnecessary class variables.
llvm-svn: 227832
2015-02-02 18:46:31 +00:00
12a5c0db57
Use the function template getSubtarget to remove an explicit cast.
...
llvm-svn: 227831
2015-02-02 18:46:29 +00:00
5c3376aa62
Grab TargetInstrInfo off of the MachineFunction and remove
...
unnecessary class variables.
llvm-svn: 227830
2015-02-02 18:46:27 +00:00
da67cc97a7
Remove unused files.
...
llvm-svn: 227829
2015-02-02 18:46:23 +00:00
cefca69d72
[Hexagon] Adding vector shift instructions and tests.
...
llvm-svn: 227619
2015-01-30 21:58:46 +00:00
cc4329b836
[Hexagon] Adding vector predicate instructions.
...
llvm-svn: 227613
2015-01-30 21:24:06 +00:00
26a537c743
[Hexagon] Adding vector permutation instructions and tests.
...
llvm-svn: 227612
2015-01-30 21:14:00 +00:00
16f5e56703
[Hexagon] Adding vector multiplies. Cleaning up tests.
...
llvm-svn: 227609
2015-01-30 20:56:54 +00:00
b84ec02296
[Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests.
...
llvm-svn: 227607
2015-01-30 20:08:37 +00:00
21fbc94777
[Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files.
...
llvm-svn: 227598
2015-01-30 19:13:26 +00:00
709c0a16bb
[Hexagon] Adding a number of vector load variants and organizing tests.
...
llvm-svn: 227588
2015-01-30 18:09:44 +00:00
3c740a3614
[Hexagon] Organizing tests and adding a few missing jump instruction encodings.
...
llvm-svn: 227498
2015-01-29 21:47:15 +00:00
bc63f42e0d
[Hexagon] Adding missing instruction encodings and tests.
...
llvm-svn: 227495
2015-01-29 21:30:22 +00:00
bd4770f915
[Hexagon] Adding alu vector instructions
...
llvm-svn: 227493
2015-01-29 21:09:30 +00:00
ba31e27f0a
Compute the ELF SectionKind from the flags.
...
Any code creating an MCSectionELF knows ELF and already provides the flags.
SectionKind is an abstraction used by common code that uses a plain
MCSection.
Use the flags to compute the SectionKind. This removes a lot of
guessing and boilerplate from the MCSectionELF construction.
llvm-svn: 227476
2015-01-29 17:33:21 +00:00
1610730faf
[Hexagon] Deleting old variants of intrinsics and adding missing tests.
...
llvm-svn: 227474
2015-01-29 17:26:56 +00:00
860210bc49
[Hexagon] Adding CR intrinsic tests.
...
llvm-svn: 227463
2015-01-29 16:55:37 +00:00
e75aa4983c
[Hexagon] Deleting unused classes.
...
llvm-svn: 227460
2015-01-29 16:35:38 +00:00
a749b3ee6a
[Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1.
...
llvm-svn: 227457
2015-01-29 16:08:43 +00:00
4379d10273
[Hexagon] Updating several V5 intrinsics and adding FP tests.
...
llvm-svn: 227379
2015-01-28 22:08:16 +00:00
1de7e0d923
[Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes.
...
llvm-svn: 227353
2015-01-28 19:39:09 +00:00
94c33218e3
[Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions.
...
llvm-svn: 227347
2015-01-28 19:16:17 +00:00
19ed07c75a
[Hexagon] Deleting a lot of old variants of intrinsics and updating references.
...
llvm-svn: 227338
2015-01-28 18:29:11 +00:00
39b846ce0f
[Hexagon] Converting XTYPE/BIT intrinsic patterns and adding tests.
...
llvm-svn: 227335
2015-01-28 18:06:23 +00:00
fe03c9a678
[Hexagon] Replacing XTYPE/SHIFT intrinsic patternss. Adding tests and missing instructions with tests.
...
llvm-svn: 227330
2015-01-28 17:37:59 +00:00
fdbc5adbb6
[Hexagon] Replacing intrinsics for halfword adds and max/min word/dword.
...
llvm-svn: 227322
2015-01-28 17:06:40 +00:00
b81dfa6378
[LPM] Stop using the string based preservation API. It is an
...
abomination.
For starters, this API is incredibly slow. In order to lookup the name
of a pass it must take a memory fence to acquire a pointer to the
managed static pass registry, and then potentially acquire locks while
it consults this registry for information about what passes exist by
that name. This stops the world of LLVMs in your process no matter
how little they cared about the result.
To make this more joyful, you'll note that we are preserving many passes
which *do not exist* any more, or are not even analyses which one might
wish to have be preserved. This means we do all the work only to say
"nope" with no error to the user.
String-based APIs are a *bad idea*. String-based APIs that cannot
produce any meaningful error are an even worse idea. =/
I have a patch that simply removes this API completely, but I'm hesitant
to commit it as I don't really want to perniciously break out-of-tree
users of the old pass manager. I'd rather they just have to migrate to
the new one at some point. If others disagree and would like me to kill
it with fire, just say the word. =]
llvm-svn: 227294
2015-01-28 04:57:56 +00:00
8b7706517c
Move DataLayout back to the TargetMachine from TargetSubtargetInfo
...
derived classes.
Since global data alignment, layout, and mangling is often based on the
DataLayout, move it to the TargetMachine. This ensures that global
data is going to be layed out and mangled consistently if the subtarget
changes on a per function basis. Prior to this all targets(*) have
had subtarget dependent code moved out and onto the TargetMachine.
*One target hasn't been migrated as part of this change: R600. The
R600 port has, as a subtarget feature, the size of pointers and
this affects global data layout. I've currently hacked in a FIXME
to enable progress, but the port needs to be updated to either pass
the 64-bitness to the TargetMachine, or fix the DataLayout to
avoid subtarget dependent features.
llvm-svn: 227113
2015-01-26 19:03:15 +00:00
94269db8ba
[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.
...
llvm-svn: 226681
2015-01-21 18:13:15 +00:00
988c68f2a7
[Hexagon] Adding intrinsics for doubleword ALU operations.
...
llvm-svn: 226606
2015-01-20 20:45:05 +00:00
0ee02fc9fe
[Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion.
...
llvm-svn: 226500
2015-01-19 20:31:18 +00:00
fcd4569af6
[Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends.
...
llvm-svn: 226483
2015-01-19 18:56:19 +00:00
9327bdad2f
[Hexagon] Converting remaining ALU32/ALU intrinsics.
...
llvm-svn: 226480
2015-01-19 18:33:58 +00:00
663419b008
[Hexagon] Converting ALU32/ALU intrinsics to new patterns.
...
llvm-svn: 226478
2015-01-19 18:22:19 +00:00
310bad8b7e
[Hexagon] Converting halfword to double accumulating multiply intrinsics.
...
llvm-svn: 226472
2015-01-19 17:36:32 +00:00
9459832ebd
std::unique_ptrify the MCStreamer argument to createAsmPrinter
...
llvm-svn: 226414
2015-01-18 20:29:04 +00:00
823415b881
[Hexagon] Converting halfword to doubleword multiply intrinsics.
...
llvm-svn: 226326
2015-01-16 21:41:57 +00:00
cd9b276966
[Hexagon] Converting accumulating halfword multiply intrinsics to patterns.
...
llvm-svn: 226324
2015-01-16 21:36:34 +00:00
3b047e0ee5
[Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitions. Converting halfword multiply intrinsics.
...
llvm-svn: 226318
2015-01-16 20:38:54 +00:00
54adb6a5d5
[Hexagon] Fix 226309, replacement atomic store patterns didn't actually exist, added new versions.
...
llvm-svn: 226315
2015-01-16 20:16:14 +00:00
bb6718b30e
[Hexagon] Removing old duplicate atomic load/store patterns.
...
llvm-svn: 226309
2015-01-16 19:53:35 +00:00
7d1f632380
[Hexagon] Converting old patterns to new versions using classes.
...
llvm-svn: 226304
2015-01-16 19:29:59 +00:00
2e3a26de0c
[Hexagon] Updating call/jump instruction patterns.
...
llvm-svn: 226288
2015-01-16 17:05:27 +00:00
cd9c4e3e07
[Hexagon] Adding new-value store and bit reverse instructions.
...
llvm-svn: 226224
2015-01-15 23:10:29 +00:00
c59328e627
[Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends.
...
llvm-svn: 226210
2015-01-15 21:35:49 +00:00
f87697f05e
[Hexagon] Updating indexed load-extend patterns and changing test to new expected output.
...
llvm-svn: 226206
2015-01-15 21:07:52 +00:00
538b85810c
[Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.
...
llvm-svn: 226194
2015-01-15 19:28:32 +00:00
504157f1ae
[Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references.
...
llvm-svn: 226184
2015-01-15 18:16:00 +00:00
2d1c14563e
[Hexagon] Deleting old float comparison instruction and updating references to new ones.
...
llvm-svn: 226179
2015-01-15 17:28:14 +00:00
7959cac725
[Hexagon] Replacing old fadd/fsub instructions and updating references.
...
llvm-svn: 226176
2015-01-15 16:30:07 +00:00
8ffce23cda
[Hexagon] Replacing old versions of stores and loads.
...
llvm-svn: 226065
2015-01-15 00:15:30 +00:00
c7522f31f1
[Hexagon] Replacing old version of convert and load f64.
...
llvm-svn: 226057
2015-01-14 23:07:36 +00:00
11a34b385d
[Hexagon] Removing old, unused !tstbit instructions.
...
llvm-svn: 226036
2015-01-14 20:26:15 +00:00
c91fabc233
[Hexagon] Removing old versions of cmph and updating references.
...
llvm-svn: 226013
2015-01-14 18:26:14 +00:00
ffacc6eac6
[Hexagon] Removing old versions of cmpb and updating references.
...
llvm-svn: 226006
2015-01-14 18:05:44 +00:00
fa947906bf
[Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references.
...
llvm-svn: 226003
2015-01-14 16:49:12 +00:00
d9903888d9
[cleanup] Re-sort all the #include lines in LLVM using
...
utils/sort_includes.py.
I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.
llvm-svn: 225974
2015-01-14 11:23:27 +00:00
2b6917b020
[SelectionDAG] Allow targets to specify legality of extloads' result
...
type (in addition to the memory type).
The *LoadExt* legalization handling used to only have one type, the
memory type. This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.
However, this isn't always the case. For instance, on X86, with AVX,
this is legal:
v4i32 load, zext from v4i8
but this isn't:
v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.
Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.
Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.
Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior. The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)
No functional change intended.
Differential Revision: http://reviews.llvm.org/D6532
llvm-svn: 225421
2015-01-08 00:51:32 +00:00
92b49c3e39
[Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings.
...
llvm-svn: 225377
2015-01-07 20:43:38 +00:00
627df427eb
[Hexagon] Adding floating point classification and creation.
...
llvm-svn: 225374
2015-01-07 20:28:57 +00:00
290ece7d4c
[Hexagon] Adding encodings for v5 floating point instructions.
...
llvm-svn: 225372
2015-01-07 20:24:09 +00:00
777abcb1d7
[Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.
...
llvm-svn: 225371
2015-01-07 20:07:28 +00:00
507dd32703
[Hexagon] Adding compound jump encodings.
...
llvm-svn: 225291
2015-01-06 20:03:31 +00:00
68b2e050f0
[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
...
llvm-svn: 225283
2015-01-06 19:03:20 +00:00
d9c605ddae
[Hexagon] Adding encoding information for absolute address loads.
...
llvm-svn: 225279
2015-01-06 18:38:26 +00:00
243a5481d9
[Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior.
...
llvm-svn: 225270
2015-01-06 16:52:38 +00:00
1445553474
[Hexagon] Adding dealloc_return encoding and absolute address stores.
...
llvm-svn: 225267
2015-01-06 16:15:15 +00:00
dacf057bdc
[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
...
llvm-svn: 225210
2015-01-05 21:36:38 +00:00
28bb02a8c7
[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
...
llvm-svn: 225201
2015-01-05 20:56:41 +00:00
abdf2b37d8
[Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
...
llvm-svn: 225199
2015-01-05 20:35:54 +00:00
3acfddd6b5
[Hexagon] Adding V4 logic-logic instructions and tests.
...
llvm-svn: 225198
2015-01-05 20:14:58 +00:00
ff10c8c95c
[Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
...
llvm-svn: 225197
2015-01-05 20:04:40 +00:00
5e079577e1
[Hexagon] Adding round reg/imm and bitsplit instructions.
...
llvm-svn: 225188
2015-01-05 18:08:21 +00:00
d3c02f177a
Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.
...
llvm-svn: 225160
2015-01-05 10:15:49 +00:00
5691eb5ee7
Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon
...
llvm-svn: 225047
2014-12-31 17:14:35 +00:00
79e8ebada2
[Hexagon] Removing assertion to appease buildbot until I can reproduce the problem
...
llvm-svn: 225045
2014-12-31 16:20:00 +00:00
94272611ac
[Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relocations aren't implemented yet but we don't need to abort for this in release builds.
...
llvm-svn: 225043
2014-12-31 15:57:38 +00:00
bc405294f0
[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.
...
llvm-svn: 225024
2014-12-31 00:08:34 +00:00
8971e055ae
[Hexagon] Adding double-logic on predicate instructions.
...
llvm-svn: 225018
2014-12-30 23:22:39 +00:00
65f3e12ed1
[Hexagon] Adding newvalue compare and jumps.
...
llvm-svn: 225015
2014-12-30 23:04:21 +00:00
0cba5f1b43
[Hexagon] Adding postincrement register newvalue stores.
...
llvm-svn: 225010
2014-12-30 22:34:08 +00:00
9014890819
[Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores.
...
llvm-svn: 225009
2014-12-30 22:28:31 +00:00
820d5cb608
[Hexagon] Adding indexed store new-value variants.
...
llvm-svn: 225007
2014-12-30 22:00:26 +00:00
2bad4a7177
[Hexagon] Adding indexed store of immediates.
...
llvm-svn: 225006
2014-12-30 21:01:38 +00:00
94a498bf0e
[Hexagon] Adding indexed stores.
...
llvm-svn: 225005
2014-12-30 20:42:23 +00:00
9161d47476
[Hexagon] Adding reg-reg indexed load forms.
...
llvm-svn: 224997
2014-12-30 18:58:47 +00:00
82fb8cba16
[Hexagon] Dropping old combine instructions without encodings.
...
llvm-svn: 224992
2014-12-30 17:53:54 +00:00
377ac65340
[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.
...
llvm-svn: 224991
2014-12-30 17:39:24 +00:00
d7a56fd9ff
[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.
...
llvm-svn: 224989
2014-12-30 15:44:17 +00:00
651b72095b
[Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores.
...
llvm-svn: 224957
2014-12-29 21:33:45 +00:00
488b6f7bbc
[Hexagon] Fixing 224952 where an addressing mode update was missed.
...
llvm-svn: 224955
2014-12-29 21:18:02 +00:00
bda31b42a0
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.
...
llvm-svn: 224952
2014-12-29 20:44:51 +00:00
9a3cd3f58c
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits.
...
llvm-svn: 224951
2014-12-29 20:00:43 +00:00
3d34afb32d
[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs.
...
llvm-svn: 224949
2014-12-29 19:42:14 +00:00
8233fb002d
[Hexagon] Adding auto-incrementing loads with and without byte reversal.
...
llvm-svn: 224871
2014-12-26 21:09:25 +00:00
0a721cd4e1
[Hexagon] Adding locked loads.
...
llvm-svn: 224870
2014-12-26 20:42:27 +00:00
ff370ed90e
[Hexagon] Adding deallocframe and circular addressing loads.
...
llvm-svn: 224869
2014-12-26 20:30:58 +00:00
c83cbbf6a1
[Hexagon] Adding remaining post-increment instruction variants. Removing unused classes.
...
llvm-svn: 224868
2014-12-26 19:31:46 +00:00
fe9612e09d
[Hexagon] Adding post-increment unsigned byte loads.
...
llvm-svn: 224867
2014-12-26 19:12:11 +00:00
96976a10a3
[Hexagon] Adding post-increment signed byte loads with tests.
...
llvm-svn: 224866
2014-12-26 18:57:13 +00:00
e193e1c48b
[Hexagon] Removing old classes.
...
llvm-svn: 224795
2014-12-24 00:43:00 +00:00
947cd70413
[Hexagon] Adding doubleword load.
...
llvm-svn: 224787
2014-12-23 20:44:59 +00:00
026e88d317
[Hexagon] Reapplying 224775 load words.
...
llvm-svn: 224786
2014-12-23 20:02:16 +00:00
20be15718b
Reverting 224775 until mayLoad flag is addressed.
...
llvm-svn: 224783
2014-12-23 19:22:59 +00:00
122aeaafea
[Hexagon] Adding word loads.
...
llvm-svn: 224775
2014-12-23 18:06:56 +00:00
8e39cad934
[Hexagon] Adding signed halfword loads.
...
llvm-svn: 224774
2014-12-23 17:25:57 +00:00
a9386d28a5
[Hexagon] Adding unsigned halfword load.
...
llvm-svn: 224772
2014-12-23 16:42:57 +00:00
4b1eac4dda
[Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.
...
llvm-svn: 224735
2014-12-22 21:40:43 +00:00
af1e5de141
[Hexagon] Adding classes and load unsigned byte instruction, updating usages.
...
llvm-svn: 224730
2014-12-22 21:20:03 +00:00
0f850bde0e
[Hexagon] Removing old variants of instructions and updating references.
...
llvm-svn: 224612
2014-12-19 20:29:29 +00:00
38ce8cd2e2
[Hexagon] Adding bit extraction and table indexing instructions.
...
llvm-svn: 224610
2014-12-19 20:01:08 +00:00
3c7f664d5a
[Hexagon] Adding bit insertion instructions.
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llvm-svn: 224609
2014-12-19 19:54:38 +00:00
d63ef93b4b
[Hexagon] Adding more xtype shift instructions.
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llvm-svn: 224608
2014-12-19 19:51:35 +00:00
cc09d1ccc5
[Hexagon] Adding xtype shift instructions.
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llvm-svn: 224604
2014-12-19 19:34:50 +00:00
f3db884efb
[Hexagon] Adding transfers to and from control registers.
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llvm-svn: 224599
2014-12-19 19:06:32 +00:00
402f772b82
[Hexagon] Adding doubleregs for control registers. Renaming control register class.
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llvm-svn: 224598
2014-12-19 18:56:10 +00:00
5ccbb1298b
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
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llvm-svn: 224556
2014-12-19 00:06:53 +00:00
174476ed96
Reverting 224550, was not ready for commit.
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llvm-svn: 224552
2014-12-18 23:36:15 +00:00
9000481cda
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
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llvm-svn: 224550
2014-12-18 23:27:51 +00:00
2055538edb
[Hexagon] Reconfiguring register alternate names.
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llvm-svn: 224455
2014-12-17 20:35:11 +00:00
aa1bade7b4
[Hexagon] Updating doubleword shift usages to new versions.
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llvm-svn: 224391
2014-12-16 23:36:15 +00:00
7fc90fc7e9
[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.
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llvm-svn: 224381
2014-12-16 22:17:09 +00:00
f5acc8c625
[Hexagon] Adding tstbit/bitclr/bitset instructions.
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llvm-svn: 224374
2014-12-16 21:28:58 +00:00
615757f2f1
[Hexagon] Adding bit count and twiddling instructions.
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llvm-svn: 224367
2014-12-16 20:57:56 +00:00
6fce46baf6
[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions.
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llvm-svn: 224365
2014-12-16 20:40:23 +00:00
1944a8cd04
[Hexagon] Adding absolute value, and negate with saturation
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llvm-svn: 224346
2014-12-16 17:44:49 +00:00
Colin LeMahieu