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4 Commits

Author SHA1 Message Date
Matt Arsenault 0de924b76d AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE 
Make the REG_SEQUENCE be a VGPR, and do the register class
copy first.

llvm-svn: 251855
 2015-11-02 23:15:42 +00:00
Matt Arsenault 10aa807856 PeepholeOptimizer: Remove redundant copies 
If a virtual register is copied and another copy was already
seen, replace with the previous copy. This only handles the
simplest cases for now.

This pattern shows up from various operand restrictions
AMDGPU has which require inserting copies depending
on the register class of the operands.

llvm-svn: 248611
 2015-09-25 20:22:12 +00:00
Matt Arsenault 28bd7d4afe AMDGPU: Add some more tests for literal operands 
llvm-svn: 248600
 2015-09-25 18:21:47 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00