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58 Commits

Author SHA1 Message Date
Ahmed Bougacha 0306b5ef07 [AArch64][GlobalISel] Select p0 G_FRAME_INDEX. 
And mark it as legal.

llvm-svn: 278802
 2016-08-16 14:02:42 +00:00
Ahmed Bougacha 6db3cfe2da [AArch64][GlobalISel] Select G_XOR. 
llvm-svn: 277173
 2016-07-29 16:56:25 +00:00
Ahmed Bougacha 7adfac56b3 [AArch64][GlobalISel] Select G_LOAD/G_STORE. 
Mostly straightforward as we ignore addressing modes and just
use the base + unsigned immediate offset (always 0) variants.

This currently fails to select extloads because we have yet to
agree on a representation.

llvm-svn: 277171
 2016-07-29 16:56:16 +00:00
Ahmed Bougacha 8550509b64 [AArch64][GlobalISel] Select G_BR. 
This is the first unsized instruction we support; move down the
'sized' check to binops.

llvm-svn: 277007
 2016-07-28 17:15:15 +00:00
Ahmed Bougacha d7748d6491 [AArch64][GlobalISel] Select GPR G_SUB. 
llvm-svn: 277003
 2016-07-28 16:58:35 +00:00
Ahmed Bougacha 61a7928dde [AArch64][GlobalISel] Select GPR G_AND. 
llvm-svn: 277002
 2016-07-28 16:58:31 +00:00
Ahmed Bougacha 46c05fc861 [GlobalISel] Remove types on selected insts instead of using LLT(). 
LLT() has a particular meaning: it's one invalid type. But we really
want selected instructions to have no type whatsoever.

Also verify that types don't linger after ISel, and enable the verifier
on the AArch64 select test.

llvm-svn: 277001
 2016-07-28 16:58:27 +00:00
Ahmed Bougacha 6756a2c953 [GlobalISel] Introduce an instruction selector. 
And implement it for AArch64, supporting x/w ADD/OR.

Differential Revision: https://reviews.llvm.org/D22373

llvm-svn: 276875
 2016-07-27 14:31:55 +00:00