96aecb5d76
Add missing PPC64 extload/truncstores
...
llvm-svn: 29140
2006-07-14 04:42:02 +00:00
a7976d329e
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
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into i16/i32 load/stores.
llvm-svn: 29089
2006-07-10 20:56:58 +00:00
4a66d69433
When possible, custom lower 32-bit SINT_TO_FP to this:
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_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
ec9d0bc3ec
Fix a couple of bugs that broke the alpha tester build
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llvm-svn: 26722
2006-03-13 05:23:59 +00:00
4fbb612685
Handle cracked instructions in dispatch group formation.
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llvm-svn: 26721
2006-03-13 05:20:04 +00:00
51348c5f27
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
d03132a409
blr is a branch too
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llvm-svn: 26710
2006-03-11 21:49:49 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
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llvm-svn: 26608
2006-03-08 04:25:59 +00:00
907e13c742
add another missing store.
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llvm-svn: 26595
2006-03-07 16:26:48 +00:00
8c73d80b08
add a couple more load/store instrs, add a newline to the end of file.
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llvm-svn: 26594
2006-03-07 16:19:46 +00:00
3e3219cc0a
This kinda sorta implements "things that have to lead a dispatch group".
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llvm-svn: 26591
2006-03-07 08:30:27 +00:00
675567f77c
add some new instructions to the classifier. With this, we correctly insert
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a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).
llvm-svn: 26590
2006-03-07 07:14:55 +00:00
05ad128dca
add some comments that describe what we model
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llvm-svn: 26588
2006-03-07 06:44:19 +00:00
2cab13573c
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
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flushes
llvm-svn: 26587
2006-03-07 06:32:48 +00:00
Chris Lattner