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63 Commits

Author SHA1 Message Date
Kannan Narayanan acb089e12a [AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing. 
Based on comments in https://reviews.llvm.org/D31161.

llvm-svn: 300023
 2017-04-12 03:25:12 +00:00
Dmitry Preobrazhensky e5147247b8 [AMDGPU][MC] Fix for Bug 28211 + LIT tests 
- corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description)
  - address operand is not used
  - several opcodes have data operand
  - all opcodes have offset modifier
- DS_AND_SRC2_B32: corrected typo in mnemo
- DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32
- added CI/VI opcodes:
  - DS_CONDXCHG32_RTN_B64
  - DS_GWS_SEMA_RELEASE_ALL
- added VI opcodes:
  - DS_CONSUME
  - DS_APPEND
  - DS_ORDERED_COUNT

Differential Revision: https://reviews.llvm.org/D31707

llvm-svn: 299767
 2017-04-07 13:07:13 +00:00
Matt Arsenault 781249833b AMDGPU: Add ds_nop to assembler 
llvm-svn: 296513
 2017-02-28 20:15:46 +00:00
Matt Arsenault dedc544ac7 AMDGPU: Add definitions for ds_{read|write}_b{96|128} 
It's not clear to me if this is always better than
doing ds_write2_b64 This adds the constraint of
a 128-bit register input instead of a pair of
64-bit.

llvm-svn: 296512
 2017-02-28 20:15:43 +00:00
Artem Tamazov 43b61561b0 [AMDGPU][mc] Fix AddressSanitizer leftover issue in gfx7_asm_all test 
Issue occurs when assembling "ds_ordered_count v0, v0 gds".

llvm-svn: 294004
 2017-02-03 12:47:30 +00:00
Tom Stellard 115a61560e AMDGPU: Add VI i16 support 
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

llvm-svn: 286464
 2016-11-10 16:02:37 +00:00
Tom Stellard 2d2d33f1dc Revert "AMDGPU: Add VI i16 support" 
This reverts commit r285939 and r285948.  These broke some conformance tests.

llvm-svn: 285995
 2016-11-04 13:06:34 +00:00
Tom Stellard 2b3379cdff AMDGPU: Add VI i16 support 
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

llvm-svn: 285939
 2016-11-03 17:13:50 +00:00
Matt Arsenault f3dd863031 AMDGPU: Whitespace fixes 
llvm-svn: 285659
 2016-11-01 00:55:14 +00:00
Artem Tamazov 751985a757 [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed. 
Fixes Bug 28215. Lit tests updated.

Differential Revision: https://reviews.llvm.org/D25837

llvm-svn: 284825
 2016-10-21 14:49:22 +00:00
Matt Arsenault 10c17ca6c6 AMDGPU: Partially fix reported code size for some instructions 
These ones need to have the size on the pseudo instruction set for
getInstSizeInBytes to work correctly. These also have a statically
known size.

llvm-svn: 283437
 2016-10-06 10:13:23 +00:00
Artem Tamazov 2e217b87cb [AMDGPU][mc] Add support for ds_add_[rtn_]f32. 
Lit tests added.
Resolves https://github.com/RadeonOpenCompute/hcc/issues/122.

Differential Revision: https://reviews.llvm.org/D24765

llvm-svn: 282086
 2016-09-21 16:35:44 +00:00
Valery Pykhtin 902db3101b [AMDGPU] refactor DS instruction definitions. NFC. 
Differential revision: https://reviews.llvm.org/D22522

llvm-svn: 277344
 2016-08-01 14:21:30 +00:00