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Author SHA1 Message Date
Matt Arsenault b3dd381a73 AMDGPU: Introduce a flag to disable mul24 intrinsic formation 
llvm-svn: 369856
 2019-08-24 22:14:41 +00:00
Matt Arsenault 49169a963e AMDGPU: Add 24-bit mul intrinsics 
Insert these during codegenprepare.

This works around a DAG issue where generic combines eliminate the and
asserting the high bits are zero, which then exposes an unknown read
source to the mul combine. It doesn't worth the hassle of trying to
insert an AssertZext or something to try to deal with it.

llvm-svn: 366094
 2019-07-15 17:50:31 +00:00