0da76a676a
Add unique id to debug location for debug label use (work in progress.)
...
llvm-svn: 25096
2006-01-04 15:04:11 +00:00
6f9ff633a6
Change how MachineDebugInfo is fetched.
...
llvm-svn: 25089
2006-01-04 13:42:59 +00:00
30db2ec59f
allow custom lowering to return null for legal results
...
llvm-svn: 25007
2005-12-25 01:07:37 +00:00
7259426d88
Support Custom lowering of a few more operations.
...
Alpha needs to custom lower *DIV and *REM
llvm-svn: 25006
2005-12-24 23:42:32 +00:00
c7037abc5b
unbreak the build :-/
...
llvm-svn: 24992
2005-12-23 16:12:20 +00:00
31d15fa093
Allow custom lowering of LOAD, EXTLOAD, ZEXTLOAD, STORE, and TRUNCSTORE. Not
...
currently used.
llvm-svn: 24988
2005-12-23 07:29:34 +00:00
884eb3adc3
Fix a pasto
...
llvm-svn: 24973
2005-12-23 00:52:30 +00:00
9eae8d5d03
fix a thinko in the bit_convert handling code
...
llvm-svn: 24972
2005-12-23 00:50:25 +00:00
36e663d6e1
add very simple support for the BIT_CONVERT node
...
llvm-svn: 24970
2005-12-23 00:16:34 +00:00
177d7af5d5
remove dead code
...
llvm-svn: 24965
2005-12-22 21:16:08 +00:00
1408c05a8b
The 81st column doesn't like code in it.
...
llvm-svn: 24943
2005-12-22 05:23:45 +00:00
9e296bee9a
Disengage DEBUG_LOC from non-PPC targets.
...
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
c1583dbd63
* Added support for X86 RET with an additional operand to specify number of
...
bytes to pop off stack.
* Added support for X86 SETCC.
llvm-svn: 24917
2005-12-21 20:21:51 +00:00
0fab459362
make sure to relegalize all cases
...
llvm-svn: 24911
2005-12-21 19:40:42 +00:00
ac12f68424
fix a bug I introduced that broke recursive expansion of nodes (e.g. scalarizing vectors)
...
llvm-svn: 24905
2005-12-21 18:02:52 +00:00
2af3ee4bdd
Fix a nasty latent bug in the legalizer that was triggered by my patch
...
last night, breaking crafty and twolf. Make sure that the newly found
legal nodes are themselves not re-legalized until the next iteration.
Also, since this functionality exists now, we can reduce number of legalizer
iterations by depending on this behavior instead of having to misuse 'do
another iteration' to get the same effect.
llvm-svn: 24875
2005-12-20 00:53:54 +00:00
6fc31046aa
X86 conditional branch support.
...
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
c06da626b4
Make sure to relegalize new nodes
...
llvm-svn: 24843
2005-12-18 23:54:29 +00:00
ebcfa0c210
More corrections for flagged copyto/from reg
...
llvm-svn: 24828
2005-12-18 15:36:21 +00:00
e3c67e97c7
legalize copytoreg and copyfromreg nodes that have flag operands correctly.
...
llvm-svn: 24826
2005-12-18 15:27:43 +00:00
bf0bd99e03
allow custom expansion of BR_CC
...
llvm-svn: 24804
2005-12-17 23:46:46 +00:00
225a4d0d6d
X86 lowers SELECT to a cmp / test followed by a conditional move.
...
llvm-svn: 24754
2005-12-17 01:21:05 +00:00
7c462768ed
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
956aef45c9
Lowering constant pool entries on ppc exposed a bug in the recently added
...
ConstantVec legalizing code, which would return constantpool nodes that
were not of the target's pointer type.
llvm-svn: 24691
2005-12-13 03:03:23 +00:00
b42ce7ca63
Fix CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
...
llvm-svn: 24677
2005-12-12 22:27:43 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
268d457b69
Teach legalize how to promote sext_inreg to fix a problem Andrew pointed
...
out to me.
llvm-svn: 24644
2005-12-09 17:32:47 +00:00
ae89d862f5
Fix a crash where ConstantVec nodes were being generated with the wrong
...
type when the target did not support them. Also teach Legalize how to
expand ConstantVecs.
This allows us to generate
_test:
lwz r2, 12(r3)
lwz r4, 8(r3)
lwz r5, 4(r3)
lwz r6, 0(r3)
addi r2, r2, 4
addi r4, r4, 3
addi r5, r5, 2
addi r6, r6, 1
stw r2, 12(r3)
stw r4, 8(r3)
stw r5, 4(r3)
stw r6, 0(r3)
blr
For:
void %test(%v4i *%P) {
%T = load %v4i* %P
%S = add %v4i %T, <int 1, int 2, int 3, int 4>
store %v4i %S, %v4i * %P
ret void
}
On PowerPC.
llvm-svn: 24633
2005-12-07 19:48:11 +00:00
41b1cdc771
Teach the SelectionDAG ISel how to turn ConstantPacked values into
...
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
llvm-svn: 24616
2005-12-06 06:18:55 +00:00
f9b27d7011
bah, must generate all results
...
llvm-svn: 24574
2005-12-02 06:08:08 +00:00
73420b3795
cycle counter fix
...
llvm-svn: 24573
2005-12-02 04:56:24 +00:00
05b0b4575b
Promote line and column number information for our friendly 64-bit targets.
...
llvm-svn: 24568
2005-12-01 18:21:35 +00:00
6ee8566cae
At long last, you can say that f32 isn't supported for setcc
...
llvm-svn: 24537
2005-11-30 17:12:26 +00:00
8d17c70171
add support for custom lowering SINT_TO_FP
...
llvm-svn: 24531
2005-11-30 06:43:03 +00:00
435b402e1f
Add support for a new STRING and LOCATION node for line number support, patch
...
contributed by Daniel Berlin, with a few cleanups here and there by me.
llvm-svn: 24515
2005-11-29 06:21:05 +00:00
89b049af90
Add the majority of the vector machien value types we expect to support,
...
and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
d37c13154a
Check in code to scalarize arbitrarily wide packed types for some simple
...
vector operations (load, add, sub, mul).
This allows us to codegen:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
on ppc as:
_foo:
lfs f0, 12(r3)
lfs f1, 8(r3)
lfs f2, 4(r3)
lfs f3, 0(r3)
fadds f0, f0, f0
fadds f1, f1, f1
fadds f2, f2, f2
fadds f3, f3, f3
stfs f0, 12(r3)
stfs f1, 8(r3)
stfs f2, 4(r3)
stfs f3, 0(r3)
blr
llvm-svn: 24484
2005-11-22 18:16:00 +00:00
07890bbec4
Rather than attempting to legalize 1 x float, make sure the SD ISel never
...
generates it. Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.
The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.
llvm-svn: 24482
2005-11-22 01:29:36 +00:00
44c28c22b7
Legalize MERGE_VALUES, expand READCYCLECOUNTER correctly, so it doesn't
...
break control dependence.
llvm-svn: 24437
2005-11-20 22:56:56 +00:00
627cbd49b1
The first patch of X86 support for read cycle counter
...
llvm-svn: 24429
2005-11-20 21:32:07 +00:00
301015a703
Silence a bogus warning
...
llvm-svn: 24420
2005-11-19 05:51:46 +00:00
b2e089c31b
Teach LLVM how to scalarize packed types. Currently, this only works on
...
packed types with an element count of 1, although more generic support is
coming. This allows LLVM to turn the following code:
void %foo(<1 x float> * %a) {
entry:
%tmp1 = load <1 x float> * %a;
%tmp2 = add <1 x float> %tmp1, %tmp1
store <1 x float> %tmp2, <1 x float> *%a
ret void
}
Into:
_foo:
lfs f0, 0(r3)
fadds f0, f0, f0
stfs f0, 0(r3)
blr
llvm-svn: 24416
2005-11-19 00:36:38 +00:00
45ca1c0194
Allow targets to custom legalize leaf nodes like GlobalAddress.
...
llvm-svn: 24387
2005-11-17 06:41:44 +00:00
4ff65ec745
Teach legalize about targetglobaladdress
...
llvm-svn: 24385
2005-11-17 05:52:24 +00:00
01aa56397d
continued readcyclecounter support
...
llvm-svn: 24300
2005-11-11 16:47:30 +00:00
bf4f233214
Switch the allnodes list from a vector of pointers to an ilist of nodes.This eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding
...
nodes to the graph.
llvm-svn: 24263
2005-11-09 23:47:37 +00:00
af3aefa10e
Handle the trivial (but common) two-op case more efficiently
...
llvm-svn: 24259
2005-11-09 18:48:57 +00:00
c4d6050db6
Allocate the right amount of memory for this vector up front.
...
llvm-svn: 24252
2005-11-08 23:32:44 +00:00
d8f2a1a0f3
Allow custom lowered FP_TO_SINT ops in the check for whether a larger
...
FP_TO_SINT is preferred to a larger FP_TO_UINT. This seems to be begging
for a TLI.isOperationCustom() helper function.
llvm-svn: 23992
2005-10-25 23:47:25 +00:00
5172ce641e
Teach Legalize how to do something with EXTRACT_ELEMENT when the type of
...
the pair of elements is a legal type.
llvm-svn: 23804
2005-10-19 00:06:56 +00:00
bd5f41a6a6
Legalize BUILD_PAIR appropriately for upcoming 64 bit PowerPC work.
...
llvm-svn: 23776
2005-10-18 00:27:41 +00:00
b986f471be
Use getExtLoad here instead of getNode, as extloads produce two values. This
...
fixes a legalize failure on SPASS for itanium.
llvm-svn: 23747
2005-10-15 20:24:07 +00:00
d59e5a7abb
Relax the checking on zextload generation a bit, since as sabre pointed out
...
you could be AND'ing with the result of a shift that shifts out all the
bits you care about, in addition to a constant.
Also, move over an add/sub_parts fold from legalize to the dag combiner,
where it works for things other than constants. Woot!
llvm-svn: 23720
2005-10-14 01:12:21 +00:00
258521d7ea
When ExpandOp'ing a [SZ]EXTLOAD, make sure to remember that the chain
...
is also legal. Add support for ExpandOp'ing raw EXTLOADs too.
llvm-svn: 23716
2005-10-13 21:44:47 +00:00
d23f4b7411
Implement PromoteOp for *EXTLOAD, allowing MallocBench/gs to Legalize
...
llvm-svn: 23715
2005-10-13 20:07:41 +00:00
c3a89c5259
Add support to Legalize for expanding i64 sextload/zextload into hi and lo
...
parts. This should fix the crafty and signed long long unit test failure
on x86 last night.
llvm-svn: 23711
2005-10-13 17:15:37 +00:00
02b23c6065
Move some Legalize functionality over to the DAGCombiner where it belongs.
...
Kill some dead code.
llvm-svn: 23706
2005-10-13 03:11:28 +00:00
7bf8d06f02
silence a bogus GCC warning
...
llvm-svn: 23646
2005-10-06 17:39:10 +00:00
4bbbb9eed7
Make the legalizer completely non-recursive
...
llvm-svn: 23642
2005-10-06 01:20:27 +00:00
f8221c5e2c
Remove some bad code from Legalize
...
llvm-svn: 23640
2005-10-05 21:44:10 +00:00
5da6908d65
Fix some faulty logic in the libcall inserter.
...
Since calls return more than one value, don't bail if one of their uses
happens to be a node that's not an MVT::Other when following the chain
from CALLSEQ_START to CALLSEQ_END.
Once we've found a CALLSEQ_START, we can just return; there's no need to
tail-recurse further up the graph.
Most importantly, just because something only has one use doesn't mean we
should use it's one use to follow from start to end. This faulty logic
caused us to follow a chain of one-use FP operations back to a much earlier
call, putting a cycle in the graph from a later start to an earlier end.
This is a better fix that reverting to the workaround committed earlier
today.
llvm-svn: 23620
2005-10-04 02:10:55 +00:00
54fb5002e5
Add back a workaround that fixes some breakages from chris's last change.
...
Neither of us have yet figured out why this code is necessary, but stuff
breaks if its not there. Still tracking this down...
llvm-svn: 23617
2005-10-04 00:37:37 +00:00
9cfccfb517
Fix a problem where the legalizer would run out of stack space on extremely
...
large basic blocks because it was purely recursive. This switches it to an
iterative/recursive hybrid.
llvm-svn: 23596
2005-10-02 17:49:46 +00:00
5b2be1f890
Fix two bugs in my patch earlier today that broke int->fp conversion on X86.
...
llvm-svn: 23522
2005-09-29 06:44:39 +00:00
6f3b577ee6
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
llvm-svn: 23504
2005-09-28 22:28:18 +00:00
2d454bf5be
Allow targets to say they don't support truncstore i1 (which includes a mask
...
when storing to an 8-bit memory location), as most don't.
llvm-svn: 23303
2005-09-10 00:20:18 +00:00
1a570f1fe4
Clean up some code from the last checkin
...
llvm-svn: 23229
2005-09-02 20:32:45 +00:00
630226697f
Fix a bug in legalize where it would emit two calls to libcalls that return
...
i64 values on targets that need that expanded to 32-bit registers. This fixes
PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll and speeds up 189.lucas from
taking 122.72s to 81.96s on my desktop.
llvm-svn: 23228
2005-09-02 20:26:58 +00:00
d9af1aab51
Make sure to legalize assert[zs]ext's operand correctly
...
llvm-svn: 23208
2005-09-02 01:15:01 +00:00
7753f175e6
legalize ANY_EXTEND appropriately
...
llvm-svn: 23204
2005-09-02 00:18:10 +00:00
8a1a5f2818
Allow targets to custom expand shifts that are too large for their registers
...
llvm-svn: 23173
2005-08-31 19:01:53 +00:00
61d21b1f3c
Fix FreeBench/fourinarow with the dag isel, by not adding a bogus result
...
to SHIFT_PARTS nodes
llvm-svn: 23151
2005-08-30 17:21:17 +00:00
9a4ad487f0
Fix a miscompile of PtrDist/bc. Sign extending bools is not the right thing,
...
at least tends to expose problems elsewhere.
llvm-svn: 23149
2005-08-30 16:56:19 +00:00
43144a2fe0
Add support for AssertSext and AssertZext, folding other extensions with
...
them. This allows for elminination of redundant extends in the entry
blocks of functions on PowerPC.
Add support for i32 x i32 -> i64 multiplies, by recognizing when the inputs
to ISD::MUL in ExpandOp are actually just extended i32 values and not real
i64 values. this allows us to codegen
int mulhs(int a, int b) { return ((long long)a * b) >> 32; }
as:
_mulhs:
mulhw r3, r4, r3
blr
instead of:
_mulhs:
mulhwu r2, r4, r3
srawi r5, r3, 31
mullw r5, r4, r5
add r2, r2, r5
srawi r4, r4, 31
mullw r3, r4, r3
add r3, r2, r3
blr
with a similar improvement on x86.
llvm-svn: 23147
2005-08-30 02:44:00 +00:00
835cbb364d
Some of us cared about the the promote path
...
llvm-svn: 23130
2005-08-29 20:46:51 +00:00
dcde1b2b6a
Fix an infinite loop on x86
...
llvm-svn: 23129
2005-08-29 17:30:00 +00:00
56ca46ee04
Nate noticed that Andrew never did this. This fixes PR600
...
llvm-svn: 23110
2005-08-26 22:50:40 +00:00
c30405e0ee
Change ConstantPoolSDNode to actually hold the Constant itself instead of
...
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
llvm-svn: 23081
2005-08-26 17:15:30 +00:00
c6d481db7a
the 5th operand is the 4th number
...
llvm-svn: 23074
2005-08-26 00:43:46 +00:00
5f573416cd
Add support for targets that want to custom expand select_cc in some cases.
...
llvm-svn: 23071
2005-08-26 00:23:59 +00:00
dff50cadaa
Allow LowerOperation to return a null SDOperand in case it wants to lower
...
some things given to it, but not all.
llvm-svn: 23070
2005-08-26 00:14:16 +00:00
f12eb4d676
Start using isOperationLegal and isTypeLegal to simplify the code
...
llvm-svn: 23012
2005-08-24 16:35:28 +00:00
987121a61a
Teach Legalize how to turn setcc into select_cc
...
llvm-svn: 22977
2005-08-23 04:29:48 +00:00
539c3fa863
When legalizing brcond ->brcc or select -> selectcc, make sure to truncate
...
the old condition to a one bit value. The incoming value must have been
promoted, and the top bits are undefined. This causes us to generate:
_test:
rlwinm r2, r3, 0, 31, 31
li r3, 17
cmpwi cr0, r2, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
li r3, 1
.LBB_test_2: ;
blr
instead of:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
li r2, 1
.LBB_test_2: ;
or r3, r2, r2
blr
for:
int %test(bool %c) {
%retval = select bool %c, int 17, int 1
ret int %retval
}
llvm-svn: 22947
2005-08-21 18:03:09 +00:00
b74c666186
Culling out use of unions for converting FP to bits and vice versa.
...
llvm-svn: 22838
2005-08-17 19:34:49 +00:00
686d6a1cb2
Switched to using BitsToDouble for int_to_float to avoid aliasing problem.
...
llvm-svn: 22831
2005-08-17 17:42:52 +00:00
898ba557d0
Change hex float constants for the sake of VC++.
...
llvm-svn: 22828
2005-08-17 09:44:59 +00:00
f2516a9180
Added generic code expansion for [signed|unsigned] i32 to [f32|f64] casts in the
...
legalizer. PowerPC now uses this expansion instead of ISel version.
Example:
// signed integer to double conversion
double f1(signed x) {
return (double)x;
}
// unsigned integer to double conversion
double f2(unsigned x) {
return (double)x;
}
// signed integer to float conversion
float f3(signed x) {
return (float)x;
}
// unsigned integer to float conversion
float f4(unsigned x) {
return (float)x;
}
Byte Code:
internal fastcc double %_Z2f1i(int %x) {
entry:
%tmp.1 = cast int %x to double ; <double> [#uses=1]
ret double %tmp.1
}
internal fastcc double %_Z2f2j(uint %x) {
entry:
%tmp.1 = cast uint %x to double ; <double> [#uses=1]
ret double %tmp.1
}
internal fastcc float %_Z2f3i(int %x) {
entry:
%tmp.1 = cast int %x to float ; <float> [#uses=1]
ret float %tmp.1
}
internal fastcc float %_Z2f4j(uint %x) {
entry:
%tmp.1 = cast uint %x to float ; <float> [#uses=1]
ret float %tmp.1
}
internal fastcc double %_Z2g1i(int %x) {
entry:
%buffer = alloca [2 x uint] ; <[2 x uint]*> [#uses=3]
%tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0 ; <uint*> [#uses=1]
store uint 1127219200, uint* %tmp.0
%tmp.2 = cast int %x to uint ; <uint> [#uses=1]
%tmp.3 = xor uint %tmp.2, 2147483648 ; <uint> [#uses=1]
%tmp.5 = getelementptr [2 x uint]* %buffer, int 0, int 1 ; <uint*> [#uses=1]
store uint %tmp.3, uint* %tmp.5
%tmp.9 = cast [2 x uint]* %buffer to double* ; <double*> [#uses=1]
%tmp.10 = load double* %tmp.9 ; <double> [#uses=1]
%tmp.13 = load double* cast (long* %signed_bias to double*) ; <double> [#uses=1]
%tmp.14 = sub double %tmp.10, %tmp.13 ; <double> [#uses=1]
ret double %tmp.14
}
internal fastcc double %_Z2g2j(uint %x) {
entry:
%buffer = alloca [2 x uint] ; <[2 x uint]*> [#uses=3]
%tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0 ; <uint*> [#uses=1]
store uint 1127219200, uint* %tmp.0
%tmp.1 = getelementptr [2 x uint]* %buffer, int 0, int 1 ; <uint*> [#uses=1]
store uint %x, uint* %tmp.1
%tmp.4 = cast [2 x uint]* %buffer to double* ; <double*> [#uses=1]
%tmp.5 = load double* %tmp.4 ; <double> [#uses=1]
%tmp.8 = load double* cast (long* %unsigned_bias to double*) ; <double> [#uses=1]
%tmp.9 = sub double %tmp.5, %tmp.8 ; <double> [#uses=1]
ret double %tmp.9
}
internal fastcc float %_Z2g3i(int %x) {
entry:
%buffer = alloca [2 x uint] ; <[2 x uint]*> [#uses=3]
%tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0 ; <uint*> [#uses=1]
store uint 1127219200, uint* %tmp.0
%tmp.2 = cast int %x to uint ; <uint> [#uses=1]
%tmp.3 = xor uint %tmp.2, 2147483648 ; <uint> [#uses=1]
%tmp.5 = getelementptr [2 x uint]* %buffer, int 0, int 1 ; <uint*> [#uses=1]
store uint %tmp.3, uint* %tmp.5
%tmp.9 = cast [2 x uint]* %buffer to double* ; <double*> [#uses=1]
%tmp.10 = load double* %tmp.9 ; <double> [#uses=1]
%tmp.13 = load double* cast (long* %signed_bias to double*) ; <double> [#uses=1]
%tmp.14 = sub double %tmp.10, %tmp.13 ; <double> [#uses=1]
%tmp.16 = cast double %tmp.14 to float ; <float> [#uses=1]
ret float %tmp.16
}
internal fastcc float %_Z2g4j(uint %x) {
entry:
%buffer = alloca [2 x uint] ; <[2 x uint]*> [#uses=3]
%tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0 ; <uint*> [#uses=1]
store uint 1127219200, uint* %tmp.0
%tmp.1 = getelementptr [2 x uint]* %buffer, int 0, int 1 ; <uint*> [#uses=1]
store uint %x, uint* %tmp.1
%tmp.4 = cast [2 x uint]* %buffer to double* ; <double*> [#uses=1]
%tmp.5 = load double* %tmp.4 ; <double> [#uses=1]
%tmp.8 = load double* cast (long* %unsigned_bias to double*) ; <double> [#uses=1]
%tmp.9 = sub double %tmp.5, %tmp.8 ; <double> [#uses=1]
%tmp.11 = cast double %tmp.9 to float ; <float> [#uses=1]
ret float %tmp.11
}
PowerPC Code:
.machine ppc970
.const
.align 2
.CPIl1__Z2f1i_0: ; float 0x4330000080000000
.long 1501560836 ; float 4.5036e+15
.text
.align 2
.globl l1__Z2f1i
l1__Z2f1i:
.LBBl1__Z2f1i_0: ; entry
xoris r2, r3, 32768
stw r2, -4(r1)
lis r2, 17200
stw r2, -8(r1)
lfd f0, -8(r1)
lis r2, ha16(.CPIl1__Z2f1i_0)
lfs f1, lo16(.CPIl1__Z2f1i_0)(r2)
fsub f1, f0, f1
blr
.const
.align 2
.CPIl2__Z2f2j_0: ; float 0x4330000000000000
.long 1501560832 ; float 4.5036e+15
.text
.align 2
.globl l2__Z2f2j
l2__Z2f2j:
.LBBl2__Z2f2j_0: ; entry
stw r3, -4(r1)
lis r2, 17200
stw r2, -8(r1)
lfd f0, -8(r1)
lis r2, ha16(.CPIl2__Z2f2j_0)
lfs f1, lo16(.CPIl2__Z2f2j_0)(r2)
fsub f1, f0, f1
blr
.const
.align 2
.CPIl3__Z2f3i_0: ; float 0x4330000080000000
.long 1501560836 ; float 4.5036e+15
.text
.align 2
.globl l3__Z2f3i
l3__Z2f3i:
.LBBl3__Z2f3i_0: ; entry
xoris r2, r3, 32768
stw r2, -4(r1)
lis r2, 17200
stw r2, -8(r1)
lfd f0, -8(r1)
lis r2, ha16(.CPIl3__Z2f3i_0)
lfs f1, lo16(.CPIl3__Z2f3i_0)(r2)
fsub f0, f0, f1
frsp f1, f0
blr
.const
.align 2
.CPIl4__Z2f4j_0: ; float 0x4330000000000000
.long 1501560832 ; float 4.5036e+15
.text
.align 2
.globl l4__Z2f4j
l4__Z2f4j:
.LBBl4__Z2f4j_0: ; entry
stw r3, -4(r1)
lis r2, 17200
stw r2, -8(r1)
lfd f0, -8(r1)
lis r2, ha16(.CPIl4__Z2f4j_0)
lfs f1, lo16(.CPIl4__Z2f4j_0)(r2)
fsub f0, f0, f1
frsp f1, f0
blr
llvm-svn: 22814
2005-08-17 00:39:29 +00:00
33182325f5
Eliminate the RegSDNode class, which 3 nodes (CopyFromReg/CopyToReg/ImplicitDef)
...
used to tack a register number onto the node.
Instead of doing this, make a new node, RegisterSDNode, which is a leaf
containing a register number. These three operations just become normal
DAG nodes now, instead of requiring special handling.
Note that with this change, it is no longer correct to make illegal
CopyFromReg/CopyToReg nodes. The legalizer will not touch them, and this
is bad, so don't do it. :)
llvm-svn: 22806
2005-08-16 21:55:35 +00:00
371e49515d
Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty
...
fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
llvm-svn: 22805
2005-08-16 19:49:35 +00:00
1973278b38
Add some methods for dag->dag isel.
...
Split RemoveNodeFromCSEMaps out of DeleteNodesIfDead to do it.
llvm-svn: 22801
2005-08-16 18:17:10 +00:00
d5e739dcc2
Fix last night's PPC32 regressions by
...
1. Not selecting the false value of a select_cc in the false arm, which
isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
Expander.
llvm-svn: 22789
2005-08-14 18:38:32 +00:00
36853ee1fd
Teach the legalizer how to legalize FP_TO_UINT.
...
Teach the legalizer to promote FP_TO_UINT to FP_TO_SINT if the wider
FP_TO_UINT is also illegal. This allows us on PPC to codegen
unsigned short foo(float a) { return a; }
as:
_foo:
.LBB_foo_0: ; entry
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
instead of:
_foo:
.LBB_foo_0: ; entry
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
lis r3, ha16(.CPI_foo_0)
lfs f0, lo16(.CPI_foo_0)(r3)
fcmpu cr0, f1, f0
blt .LBB_foo_2 ; entry
.LBB_foo_1: ; entry
fsubs f0, f1, f0
fctiwz f0, f0
stfd f0, -16(r1)
lwz r2, -12(r1)
xoris r2, r2, 32768
.LBB_foo_2: ; entry
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 22785
2005-08-14 01:20:53 +00:00
180b08897f
Some SELECT_CC cleanups:
...
1. move assertions for node creation to getNode()
2. legalize the values returned in ExpandOp immediately
3. Move select_cc optimizations from SELECT's getNode() to SELECT_CC's,
allowing them to be cleaned up significantly.
This paves the way to pick up additional optimizations on SELECT_CC, such
as sum-of-absolute-differences.
llvm-svn: 22757
2005-08-11 01:12:20 +00:00
e5b86d7442
Add new node, SELECT_CC. This node is for targets that don't natively
...
implement SELECT.
llvm-svn: 22755
2005-08-10 20:51:12 +00:00
d47675ed24
Eliminate the SetCCSDNode in favor of a CondCodeSDNode class. This pulls the
...
CC out of the SetCC operation, making SETCC a standard ternary operation and
CC's a standard DAG leaf. This will make it possible for other node to use
CC's as operands in the future...
llvm-svn: 22728
2005-08-09 20:20:18 +00:00
96ad31321a
Change FindEarliestCallSeqEnd (used by libcall insertion) to use a set to
...
avoid revisiting nodes more than once. This eliminates a source of
potentially exponential behavior. For a small function in 191.fma3d
(hexah_stress_divergence_), this speeds up isel from taking > 20mins to
taking 0.07s.
llvm-svn: 22680
2005-08-05 18:10:27 +00:00
cabdc34563
Fix a latent bug in the libcall inserter that was exposed by Nate's patch
...
yesterday. This fixes whetstone and a bunch of programs in the External tests.
llvm-svn: 22678
2005-08-05 16:23:57 +00:00
77558da546
Fix a fixme in LegalizeDAG
...
llvm-svn: 22661
2005-08-04 21:43:28 +00:00
8191442548
Fix PR611, codegen'ing SREM of FP operands to fmod or fmodf instead of
...
the sequence used for integer ops
llvm-svn: 22629
2005-08-03 20:31:37 +00:00
Jim Laskey