8cbbcb1f2f
Encode VFP load / store instructions.
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llvm-svn: 59084
2008-11-11 21:48:44 +00:00
38c9a14a88
Encode VFP conversion instructions.
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llvm-svn: 59074
2008-11-11 19:40:26 +00:00
ac2af2fdb2
Encode VFP arithmetic instructions.
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llvm-svn: 59016
2008-11-11 02:11:05 +00:00
98dc53e926
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
49d665218c
Encode extend instructions; more clean up.
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llvm-svn: 58818
2008-11-06 22:15:19 +00:00
aa03cd3336
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
47b546d75f
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
36ae40342f
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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llvm-svn: 58793
2008-11-06 03:35:07 +00:00
2686c8fb34
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
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llvm-svn: 58789
2008-11-06 01:21:28 +00:00
81889d010c
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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llvm-svn: 58764
2008-11-05 18:35:52 +00:00
4d0549e3be
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
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llvm-svn: 58626
2008-11-03 18:38:31 +00:00
33332bce17
Const-ify several TargetInstrInfo methods.
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llvm-svn: 57622
2008-10-16 01:49:15 +00:00
b53acd8caa
need ARM.h for ARMCC definition
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llvm-svn: 57261
2008-10-07 21:01:51 +00:00
c084e84028
Encode the conditional execution predicate when JITing.
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llvm-svn: 57258
2008-10-07 19:05:35 +00:00
12134701ec
Revert 56176. All those instruction formats are still needed.
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llvm-svn: 56180
2008-09-13 01:35:33 +00:00
c5c74f36fd
Eliminate unnecessary instruction formats.
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llvm-svn: 56176
2008-09-12 23:15:39 +00:00
33fa89c6fb
Rewrite address mode 1 code emission routines.
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llvm-svn: 56171
2008-09-12 22:01:15 +00:00
27fb3dcbc7
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
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was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
4f6bf04616
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
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llvm-svn: 54802
2008-08-14 22:49:33 +00:00
30cc028e4a
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
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Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.
llvm-svn: 53058
2008-07-02 23:41:07 +00:00
eabd647cd5
Change target-specific classes to use more precise static types.
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This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
llvm-svn: 51091
2008-05-14 01:58:56 +00:00
ae84bbdbed
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
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llvm-svn: 49809
2008-04-16 20:10:13 +00:00
ed6e34fe41
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
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llvm-svn: 48995
2008-03-31 20:40:39 +00:00
c60c67fc37
Add explicit keywords.
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llvm-svn: 48801
2008-03-25 22:06:05 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
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llvm-svn: 46930
2008-02-10 18:45:23 +00:00
3b3286d4bc
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
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llvm-svn: 46893
2008-02-08 21:20:40 +00:00
2a3be7bb6c
Move even more functionality from MRegisterInfo into TargetInstrInfo.
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Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
6bb0c52628
Move some more functionality from MRegisterInfo to TargetInstrInfo.
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llvm-svn: 45603
2008-01-04 23:57:37 +00:00
eee14601b1
Move some more instruction creation methods from RegisterInfo into InstrInfo.
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llvm-svn: 45484
2008-01-01 21:11:32 +00:00
25568e4cef
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
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a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
llvm-svn: 45475
2008-01-01 01:03:04 +00:00
7a73ae9a86
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
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Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
79dfbed6f6
Fix a misnamed parameter.
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llvm-svn: 43145
2007-10-18 19:29:45 +00:00
ab871baaf8
Instruction formats added used to generate multiply instructions of V5TE.
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llvm-svn: 41629
2007-08-30 23:34:14 +00:00
f7c6effc44
Initial JIT support for ARM by Raul Fernandes Herbster.
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llvm-svn: 40887
2007-08-07 01:37:15 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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llvm-svn: 38501
2007-07-10 18:08:01 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
36b1f5476e
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
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llvm-svn: 37606
2007-06-15 21:15:00 +00:00
2d91a4fd6a
Add missing const qualifiers.
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llvm-svn: 37342
2007-05-29 18:42:18 +00:00
1d764eca98
Hooks for predication support.
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llvm-svn: 37308
2007-05-23 07:22:05 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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llvm-svn: 37193
2007-05-18 00:18:17 +00:00
dcff2eb0e8
PredicateInstruction returns true if the operation was successful.
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llvm-svn: 37124
2007-05-16 21:53:07 +00:00
e2762c3d68
Removed isPredicable().
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llvm-svn: 37119
2007-05-16 20:50:23 +00:00
ad3aac71ce
Hooks for predication support.
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llvm-svn: 37093
2007-05-16 02:01:49 +00:00
760c68b8af
Factor GetInstSize() out of constpool island pass.
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llvm-svn: 33644
2007-01-29 23:45:17 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
aaeede0aa2
implement uncond branch insertion, mark branches with isBranch.
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llvm-svn: 31160
2006-10-24 16:47:57 +00:00
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
ffdc24b847
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
Evan Cheng