OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
268,867 Commits 32 Branches 0 Tags 2.2 GiB
Commit Graph

2 Commits

Author SHA1 Message Date
Alex Bradbury 6be16fbfb8 [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr 
llvm-svn: 295027
 2017-02-14 05:17:23 +00:00
Alex Bradbury 24d9b13b36 [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td 
For now, only add instruction definitions for basic ALU operations. Our 
initial target is a working MC layer rather than codegen, so appropriate 
SelectionDAG patterns will come later.

Differential Revision: https://reviews.llvm.org/D23561

llvm-svn: 285769
 2016-11-01 23:40:28 +00:00