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Author SHA1 Message Date
Haicheng Wu 6a6bc750d5 [AArch64] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize 
Mimic what x86 does when optimizing sdiv/udiv for minsize.

llvm-svn: 264606
 2016-03-28 18:17:07 +00:00