OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
128,514 Commits 31 Branches 0 Tags 2.2 GiB
Commit Graph

21446 Commits

Author SHA1 Message Date
Richard Barton f1ef87ddbb Correct decoder for T1 conditional B encoding 
llvm-svn: 158055
 2012-06-06 09:12:53 +00:00
Craig Topper bf2409e8aa Mark several instructions SSE2 instead of SSE3 as they should be. 
llvm-svn: 158049
 2012-06-06 06:45:27 +00:00
Andrew Trick 4544606c71 misched: API for minimum vs. expected latency. 
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021
 2012-06-05 21:11:27 +00:00
Yuan Lin 572a3a2cce Fix header file include order in NVPTX backend NV_CONTRIB 
llvm-svn: 158013
 2012-06-05 19:06:13 +00:00
Roman Divacky c856653fb3 PPC32 uses R2 as the TLS register. Fix the copy and paste. 
llvm-svn: 158004
 2012-06-05 17:14:17 +00:00
Andrew Trick 39a99140c7 X86 itinerary properties. 
llvm-svn: 157981
 2012-06-05 03:44:46 +00:00
Andrew Trick b2680c718f ARM itinerary properties. 
llvm-svn: 157980
 2012-06-05 03:44:43 +00:00
Andrew Trick 73d7736b17 misched: Added MultiIssueItineraries. 
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979
 2012-06-05 03:44:40 +00:00
Andrew Trick 515f131786 whitespace 
llvm-svn: 157976
 2012-06-05 03:44:29 +00:00
Joel Jones 7f2ac7a2c8 Revert commit r157966 
llvm-svn: 157972
 2012-06-05 00:47:21 +00:00
Joel Jones d08534f82e This change handles a another case for generating the bic instruction 
when a compile time constant is known.  This occurs when implicitly zero 
extending function arguments from 16 bits to 32 bits.

<rdar://problem/11481151>

llvm-svn: 157966
 2012-06-04 23:38:57 +00:00
Akira Hatanaka 6734685f21 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is 
inserted after the shift-left-logical node.

llvm-svn: 157937
 2012-06-04 17:46:29 +00:00
Roman Divacky e3f15c98d1 Implement local-exec TLS on PowerPC. 
llvm-svn: 157935
 2012-06-04 17:36:38 +00:00
Hans Wennborg 245917b536 MIPS TLS: use the model selected by TargetMachine::getTLSModel(). 
This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929
 2012-06-04 14:02:08 +00:00
Hans Wennborg 09610f3e09 Better comments for TLS-related X86 MachineOperand flags. 
llvm-svn: 157920
 2012-06-04 09:55:36 +00:00
Craig Topper c6ac4cefcc Add intrinsic forms for FMA instructions to opcode folding tables. 
llvm-svn: 157917
 2012-06-04 07:46:16 +00:00
Craig Topper 3cb143016d Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 forms of scalar FMA instructions. 
llvm-svn: 157914
 2012-06-04 07:08:21 +00:00
Hal Finkel 1de9bf01e4 Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no functionality change). 
llvm-svn: 157912
 2012-06-04 02:39:52 +00:00
Hal Finkel 595817eebe Enable generating PPC pre-increment (r+imm) instructions by default. 
It seems that this no longer causes test suite failures on PPC64 (after r157159),
and often gives a performance benefit, so it can be enabled by default.

llvm-svn: 157911
 2012-06-04 02:21:00 +00:00
Craig Topper 79dbb0c6e4 Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang. 
llvm-svn: 157903
 2012-06-03 18:58:46 +00:00
Craig Topper fd53b80219 Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. 
llvm-svn: 157898
 2012-06-03 07:26:46 +00:00
Manman Ren 5097e4f38a Revert r157831 
llvm-svn: 157896
 2012-06-03 03:14:24 +00:00
Craig Topper 29eafea292 Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior. 
llvm-svn: 157895
 2012-06-03 01:40:43 +00:00
Craig Topper badd755a0e Add neverHasSideEffects and mayLoad to FMA3 instructions. 
llvm-svn: 157894
 2012-06-03 00:30:49 +00:00
Benjamin Kramer bde9176663 Fix typos found by http://github.com/lyda/misspell-check 
llvm-svn: 157885
 2012-06-02 10:20:22 +00:00
Chris Lattner 58268c23ac remove an unused variable. 
llvm-svn: 157872
 2012-06-02 01:03:42 +00:00
Akira Hatanaka 23327b30ef Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower. 
llvm-svn: 157867
 2012-06-02 00:05:11 +00:00
Akira Hatanaka 019e592f75 Set operation actions for load/store nodes in the Mips backend. 
llvm-svn: 157866
 2012-06-02 00:04:42 +00:00
Akira Hatanaka f11571d90d Add definitions of 32/64-bit unaligned load/store instructions for Mips. 
llvm-svn: 157865
 2012-06-02 00:04:19 +00:00
Akira Hatanaka 8f1db778a4 Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which 
custom-lower unaligned load and store nodes.

llvm-svn: 157864
 2012-06-02 00:03:49 +00:00
Akira Hatanaka b9ebf8d644 Define Mips specific unaligned load/store nodes. 
llvm-svn: 157863
 2012-06-02 00:03:12 +00:00
Akira Hatanaka 4e76bf8282 Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862
 2012-06-02 00:02:45 +00:00
Akira Hatanaka 56bf023a6d In MipsMCInstLower::LowerSymbolOperand, get offset from symbol if 
the MachineOperand type has a valid offset. 

llvm-svn: 157861
 2012-06-02 00:02:11 +00:00
Jakob Stoklund Olesen 54038d796c Switch all register list clients to the new MC*Iterator interface. 
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854
 2012-06-01 23:28:30 +00:00
Chad Rosier f319324082 [arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0 
then DestReg is undefined.

llvm-svn: 157840
 2012-06-01 21:12:31 +00:00
Jakob Stoklund Olesen 92a0083944 Switch some getAliasSet clients to MCRegAliasIterator. 
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837
 2012-06-01 20:36:54 +00:00
Manman Ren 879ca9d47d X86: peephole optimization to remove cmp instruction 
This patch will optimize the following:
  sub r1, r3
  cmp r3, r1 or cmp r1, r3
  bge L1
TO
  sub r1, r3
  bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.

llvm-svn: 157831
 2012-06-01 19:49:33 +00:00
Manman Ren e873552091 ARM: properly handle alignment for struct byval. 
Factor out the expansion code into a function.
This change is to be enabled in clang.

rdar://9877866

llvm-svn: 157830
 2012-06-01 19:33:18 +00:00
Hans Wennborg 789acfb63d Implement the local-dynamic TLS model for x86 (PR3985) 
This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

llvm-svn: 157818
 2012-06-01 16:27:21 +00:00
Craig Topper 1d4d62d76c Enable automatic detection of FMA3 support to allow intrinsics to be used. 
llvm-svn: 157805
 2012-06-01 06:10:14 +00:00
Craig Topper 00649d5111 Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though. 
llvm-svn: 157804
 2012-06-01 06:07:48 +00:00
Craig Topper 2e127b5274 Add VFNSUB* instructions to folding table. 
llvm-svn: 157802
 2012-06-01 05:48:39 +00:00
Craig Topper 9eadcfdf2a Remove a trailing space and fix a comment. 
llvm-svn: 157801
 2012-06-01 05:34:01 +00:00
Craig Topper df09da8355 Tidy up. Remove trailing spaces and fix the worst of the 80 column violations. 
llvm-svn: 157799
 2012-06-01 05:24:29 +00:00
Manman Ren 9f9111651e ARM: support struct byval in llvm 
We handle struct byval by inserting a pseudo op, which will be expanded to a
loop at ExpandISelPseudos.
A separate patch for clang will be submitted to enable struct byval.

rdar://9877866

llvm-svn: 157793
 2012-06-01 02:44:42 +00:00
Chad Rosier 526772de29 Put the shiny new MCSubRegIterator to work. 
llvm-svn: 157783
 2012-06-01 00:02:08 +00:00
Jakob Stoklund Olesen 4f203ea34b Add support for return value promotion in X86 calling conventions. 
Patch by Yiannis Tsiouris!

llvm-svn: 157757
 2012-05-31 17:28:20 +00:00
Manman Ren 9bccb64e56 X86: replace SUB with CMP if possible 
This patch will optimize the following
        movq    %rdi, %rax
        subq    %rsi, %rax
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax
to
        cmpq    %rsi, %rdi
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023
llvm-svn: 157755
 2012-05-31 17:20:29 +00:00
Jakob Stoklund Olesen fa9d7db17b Add a PrintRegUnit helper similar to PrintReg. 
Reg-units are named after their root registers, and most units have a
single root, so they simply print as 'AL', 'XMM0', etc. The rare dual
root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ...

The printing piggybacks on the existing register name tables, so no
extra const data space is required.

llvm-svn: 157754
 2012-05-31 17:18:29 +00:00
Joel Jones 585bc82489 Fix typos 
llvm-svn: 157752
 2012-05-31 17:11:25 +00:00