Commit Graph

1158 Commits

Author SHA1 Message Date
Akira Hatanaka 6734685f21 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is
inserted after the shift-left-logical node.

llvm-svn: 157937
2012-06-04 17:46:29 +00:00
Hans Wennborg 245917b536 MIPS TLS: use the model selected by TargetMachine::getTLSModel().
This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929
2012-06-04 14:02:08 +00:00
Benjamin Kramer bde9176663 Fix typos found by http://github.com/lyda/misspell-check
llvm-svn: 157885
2012-06-02 10:20:22 +00:00
Chris Lattner 58268c23ac remove an unused variable.
llvm-svn: 157872
2012-06-02 01:03:42 +00:00
Akira Hatanaka 23327b30ef Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.
llvm-svn: 157867
2012-06-02 00:05:11 +00:00
Akira Hatanaka 019e592f75 Set operation actions for load/store nodes in the Mips backend.
llvm-svn: 157866
2012-06-02 00:04:42 +00:00
Akira Hatanaka f11571d90d Add definitions of 32/64-bit unaligned load/store instructions for Mips.
llvm-svn: 157865
2012-06-02 00:04:19 +00:00
Akira Hatanaka 8f1db778a4 Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which
custom-lower unaligned load and store nodes.

llvm-svn: 157864
2012-06-02 00:03:49 +00:00
Akira Hatanaka b9ebf8d644 Define Mips specific unaligned load/store nodes.
llvm-svn: 157863
2012-06-02 00:03:12 +00:00
Akira Hatanaka 4e76bf8282 Expand unaligned i16 loads/stores for the Mips backend.
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862
2012-06-02 00:02:45 +00:00
Akira Hatanaka 56bf023a6d In MipsMCInstLower::LowerSymbolOperand, get offset from symbol if
the MachineOperand type has a valid offset. 

llvm-svn: 157861
2012-06-02 00:02:11 +00:00
Jakob Stoklund Olesen 92a0083944 Switch some getAliasSet clients to MCRegAliasIterator.
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837
2012-06-01 20:36:54 +00:00
Akira Hatanaka bff8e31d3c Cleanup and factoring of mips16 tablegen classes. Make register classes
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730
2012-05-31 02:59:44 +00:00
Eric Christopher f481ab3877 Add support for the mips inline asm 'm' output modifier.
Patch by Jack Carter.

llvm-svn: 157709
2012-05-30 19:05:19 +00:00
Jakob Stoklund Olesen ad8103dc7b Fix some uses of getSubRegisters() to use getSubReg() instead.
It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

llvm-svn: 157703
2012-05-30 18:40:49 +00:00
Akira Hatanaka 5cec9007bb Fix predicate HasStandardEncoding in MipsInstrInfo.td per suggestion of
Benjamin Kramer.

llvm-svn: 157504
2012-05-25 22:15:15 +00:00
Akira Hatanaka 03968fac4f Delete MipsExpandPseudo.cpp.
llvm-svn: 157496
2012-05-25 20:54:48 +00:00
Akira Hatanaka d0ac2c93d3 Move the code in MipsExpandPseudo to MipsInstrInfo::expandPostRAPseudo.
Delete MipsExpandPseudo.

llvm-svn: 157495
2012-05-25 20:52:52 +00:00
Akira Hatanaka f4554485cb Remove the code that expands MIPS' .cpload directive.
llvm-svn: 157494
2012-05-25 20:46:52 +00:00
Akira Hatanaka 5de59266cd Remove the code that emits MIPS' .cprestore directive.
llvm-svn: 157493
2012-05-25 20:42:55 +00:00
Akira Hatanaka 4d9b017ef2 Remove pseudo instructions that are no longer used.
llvm-svn: 157492
2012-05-25 20:37:40 +00:00
Justin Holewinski aa58397b3c Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479
2012-05-25 16:35:28 +00:00
Akira Hatanaka a649cc75b3 Turn on mips16 pseudo op when compiling for mips16.
Expand test case for this.

Patch by Reed Kotler.

llvm-svn: 157410
2012-05-24 18:37:43 +00:00
Akira Hatanaka df98a7a34d Enable Mips16 compiler to compile a null program.
First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.

llvm-svn: 157408
2012-05-24 18:32:33 +00:00
Craig Topper 273b0d7be5 Use uint16_t to store registers in static tables. Matches other tables.
llvm-svn: 157375
2012-05-24 06:09:56 +00:00
Akira Hatanaka cdf4fd8267 This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
2012-05-22 03:10:09 +00:00
Eric Christopher bc5d24999c Add support for the 'd' mips inline asm output modifier.
Patch by Jack Carter.

llvm-svn: 157093
2012-05-19 00:51:56 +00:00
Eric Christopher 9ca26cfb5f Add support for the mips 'x' inline asm modifier.
Patch by Jack Carter.

llvm-svn: 157057
2012-05-18 17:39:35 +00:00
Akira Hatanaka 0faaebf27c This patch adds the register class for MIPS16 as well as the ability for
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.

Patch by Reed Kotler.

llvm-svn: 156958
2012-05-16 22:19:56 +00:00
Jim Grosbach c3b0427921 Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828
2012-05-15 17:35:52 +00:00
Akira Hatanaka cf434ee4c1 Temporarily disable anti-dependence breaking for Mips until bug 12829 is
resolved.

llvm-svn: 156801
2012-05-15 03:14:52 +00:00
Akira Hatanaka 4773e67e0b Add a command line option to skip the delay slot filler pass entirely for Mips.
The purpose of this option is to silence error messages issued by machine
verifier passes and enable them to run to the end. If this option is not
provided, -verify-machineinstrs complains when it discovers there is a
non-terminator instruction (an instruction that is in a delay slot) after the
first terminator in a basic block.

llvm-svn: 156790
2012-05-14 23:59:17 +00:00
Akira Hatanaka a6c3fd8317 Remove MipsEmitGPRestore.cpp.
llvm-svn: 156696
2012-05-12 03:24:03 +00:00
Akira Hatanaka 3ecc5273c1 Delete all functions that are no longer needed in MipsFunctionInfo, including
the ones that get or set the frame index for the $gp save slot. 

Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns
GP. This function should always return a virtual register.

llvm-svn: 156695
2012-05-12 03:22:13 +00:00
Akira Hatanaka 2e31e036b6 Stop reserving register $gp. Do not call isGPFI to check whether a frame object
is the $gp save slot.

llvm-svn: 156694
2012-05-12 03:21:18 +00:00
Akira Hatanaka 0fb87feb39 Do not add the pass which restores $gp after every function call.
llvm-svn: 156693
2012-05-12 03:19:51 +00:00
Akira Hatanaka f542ebd958 Make the following changes in MipsISelLowering.cpp:
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692
2012-05-12 03:19:04 +00:00
Akira Hatanaka c980f8453a Make the following changes in MipsFrameLowering.cpp:
- Stop emitting instructions needed to initialize the global pointer register.
- Stop emitting .cprestore directive.
- Do not take into account the $gp save slot when computing stack size.

llvm-svn: 156691
2012-05-12 03:18:00 +00:00
Akira Hatanaka 8f3573034b Make the following changes in MipsAsmPrinter.cpp:
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

llvm-svn: 156689
2012-05-12 00:48:43 +00:00
Akira Hatanaka d918f77ba3 Insert instructions to the entry basic block which initializes the global
pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.

llvm-svn: 156671
2012-05-12 00:17:17 +00:00
Akira Hatanaka 0661b81bca Do not replace operands of pseudo instructions with register $zero.
llvm-svn: 156663
2012-05-11 23:22:18 +00:00
Akira Hatanaka e37614438f Fix a misleading comment.
llvm-svn: 156603
2012-05-11 01:45:15 +00:00
Eric Christopher ed51b9ec0b Add support for the 'X' inline asm operand modifier.
Patch by Jack Carter.

llvm-svn: 156577
2012-05-10 21:48:22 +00:00
Akira Hatanaka ca41d13bbd Add another peephole pattern for conditional moves.
llvm-svn: 156460
2012-05-09 02:29:29 +00:00
Akira Hatanaka 05b9dad1e6 Make register FP allocatable if the compiled function does not have dynamic
allocas.

llvm-svn: 156458
2012-05-09 01:38:13 +00:00
Akira Hatanaka 0a8ab718cb Expand 64-bit shifts if target ABI is O32.
llvm-svn: 156457
2012-05-09 00:55:21 +00:00
Akira Hatanaka c515bfb9e7 Define mips16 instruction formats.
Patch by Reed Kotler.

llvm-svn: 156408
2012-05-08 19:08:58 +00:00
Eric Christopher 0d8c15d20f Add support for the 'x' constraint.
Patch by Jack Carter.

llvm-svn: 156295
2012-05-07 06:25:19 +00:00
Eric Christopher 9c492e6ebf Add support for the 'l' constraint.
Patch by Jack Carter.

llvm-svn: 156294
2012-05-07 06:25:15 +00:00
Eric Christopher e3c494de82 Add support for the 'c' constraint.
Patch by Jack Carter.

llvm-svn: 156293
2012-05-07 06:25:10 +00:00