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4 Commits

Author SHA1 Message Date
Matt Arsenault e0b8443460 AMDGPU: Check MRI for callee saved regs instead of TRI 
This should the same, but MRI does allow dynamically changing the CSR
set, although currently not used.

llvm-svn: 364425
 2019-06-26 13:39:29 +00:00
Galina Kistanova ed49f6d8e6 Reverted r361134 because of a failing test left unattended for a long time. 
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/17792/steps/test-check-all/logs/stdio
Failing Tests (1):
    LLVM :: CodeGen/AMDGPU/regbank-reassign.mir

llvm-svn: 361430
 2019-05-22 20:42:56 +00:00
Fangrui Song 68774edcd6 Use llvm::sort. NFC 
llvm-svn: 361134
 2019-05-20 10:18:35 +00:00
Stanislav Mekhanoshin 3b7925f035 [AMDGPU] gfx1010 GCNRegBankReassign pass 
Reassign registers to reduce register bank conflicts.

Differential Revision: https://reviews.llvm.org/D61344

llvm-svn: 359704
 2019-05-01 16:49:31 +00:00