fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
f0157cb0bc
Use movaps instead of movapd for spill / restore.
...
llvm-svn: 28005
2006-04-28 02:23:35 +00:00
ab0ee6340c
MakeMIInst() should handle jump table index operands.
...
llvm-svn: 27955
2006-04-24 05:37:35 +00:00
3823aa1d0f
- PEXTRW cannot take a memory location as its first source operand.
...
- PINSRWrmi encoding bug.
llvm-svn: 27818
2006-04-18 21:59:43 +00:00
43f4ef4ffb
SHUFP{S|D}, PSHUF* encoding bugs. Left out the mask immediate operand.
...
llvm-svn: 27817
2006-04-18 21:56:36 +00:00
09e36ef710
Encoding bug: CMPPSrmi, CMPPDrmi dropped operand 2 (condtion immediate).
...
llvm-svn: 27815
2006-04-18 21:31:08 +00:00
bf0d13c54f
Incorrect foldMemoryOperand entries
...
llvm-svn: 27763
2006-04-17 18:06:12 +00:00
685ddd8152
Can't fold loads into alias vector SSE ops used for scalar operation. The load
...
address has to be 16-byte aligned but the values aren't spilled to 128-bit
locations.
llvm-svn: 27732
2006-04-16 06:58:19 +00:00
0ba896c75b
Added SSE (and other) entries to foldMemoryOperand().
...
llvm-svn: 27716
2006-04-14 23:33:27 +00:00
e349d01acf
We were not adjusting the frame size to ensure proper alignment when alloca /
...
vla are present in the function. This causes a crash when a leaf function
allocates space on the stack used to store / load with 128-bit SSE
instructions.
llvm-svn: 27698
2006-04-14 07:26:43 +00:00
c9ed8e4c1a
Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available for SSE1.
...
llvm-svn: 27554
2006-04-10 07:21:31 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
8f3b6b8d8a
Minor fixes + naming changes.
...
llvm-svn: 27410
2006-04-04 19:12:30 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
3c43609f1f
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
bfc2e97383
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
...
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
aca7915b70
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
...
ADD32ri8.
llvm-svn: 26816
2006-03-17 02:25:01 +00:00
42d5ac557c
Fix an obvious bug exposed when we are doing
...
ADD X, 4
==>
MOV32ri $X+4, ...
llvm-svn: 26366
2006-02-25 01:37:02 +00:00
fa57a0add9
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
...
Added generic vector types: VR64 and VR128.
llvm-svn: 26295
2006-02-21 01:38:21 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
3f99628939
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
...
llvm-svn: 26240
2006-02-16 21:20:26 +00:00
ae82498e81
Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
...
transfer.
According to the Intel P4 Optimization Manual:
Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.
Not to mention movaps is shorter than movss.
llvm-svn: 26226
2006-02-16 01:50:02 +00:00
c408558638
When rewriting frame instructions, emit the appropriate small-immediate
...
instruction when possible.
llvm-svn: 25938
2006-02-03 18:20:04 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
246ee44c8f
implement isStoreToStackSlot
...
llvm-svn: 25911
2006-02-02 20:00:41 +00:00
f1ed826c2a
Added SSE entries to foldMemoryOperand().
...
llvm-svn: 25888
2006-02-01 23:02:25 +00:00
9c249c37f8
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
...
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
172fce7050
* Fast call support.
...
* FP cmp, setcc, etc.
llvm-svn: 25117
2006-01-06 00:43:03 +00:00
782b654e6f
Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.
...
llvm-svn: 25004
2005-12-24 09:48:35 +00:00
9ae486047e
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
f431ad4477
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
...
that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
2005-12-21 07:47:04 +00:00
9d7008b08d
Properly split f32 and f64 into separate register classes for scalar sse fp
...
fixing a bunch of nasty hackery
llvm-svn: 23735
2005-10-14 22:06:00 +00:00
bb1c9ecb17
simplify this code using the new regclass info passed in
...
llvm-svn: 23557
2005-09-30 17:12:38 +00:00
a654525c1c
Pass extra regclasses into spilling code
...
llvm-svn: 23537
2005-09-30 01:29:42 +00:00
de3c87a2ab
Implement the isLoadFromStackSlot interface
...
llvm-svn: 23387
2005-09-19 05:23:44 +00:00
8ad3700a3e
The simple isel being gone makes this dead!
...
llvm-svn: 22914
2005-08-19 18:32:03 +00:00
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
...
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
8a0933608a
First round of support for doing scalar FP using the SSE2 ISA extension and
...
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
llvm-svn: 22340
2005-07-06 18:59:04 +00:00
97e3b65652
Teach reginfo how to deal with ADJSTACKPTRri, allowing us to generate:
...
add %ESP, 20
jmp %EDX # TAIL CALL
instead of:
add %ESP, -8
add %ESP, 28
jmp %EDX # TAIL CALL
llvm-svn: 22047
2005-05-15 05:49:58 +00:00
5366c859a7
When emitting the function epilog, check to see if there already a stack
...
adjustment. If so, we merge the adjustment into the existing one. This
allows us to generate:
caller2:
sub %ESP, 12
mov DWORD PTR [%ESP], 0
mov %EAX, 1234567890
mov %EDX, 0
call func2
add %ESP, 8
ret 4
intead of:
caller2:
sub %ESP, 12
mov DWORD PTR [%ESP], 0
mov %EAX, 1234567890
mov %EDX, 0
call func2
sub %ESP, 4
add %ESP, 12
ret 4
for X86/fast-cc-merge-stack-adj.ll
llvm-svn: 22038
2005-05-14 23:53:43 +00:00
f0649db870
Add some new instructions
...
llvm-svn: 22036
2005-05-14 23:35:21 +00:00
c0e369ed66
switch to having the callee pop stack operands for fastcc. This is currently buggy
...
do not use
llvm-svn: 21984
2005-05-13 21:44:04 +00:00
1a12476531
allow RETI
...
llvm-svn: 21980
2005-05-13 20:46:35 +00:00
c21db6b15c
add signed versions of the extra precision multiplies
...
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
0edf9535b9
Add rotate instructions.
...
llvm-svn: 19690
2005-01-19 07:50:03 +00:00
d54845f530
Improve coverage of the X86 instruction set by adding 16-bit shift doubles.
...
llvm-svn: 19687
2005-01-19 07:31:24 +00:00
5b589ec0c4
Add conditional moves for the parity flag.
...
llvm-svn: 19437
2005-01-10 22:09:33 +00:00
b62b45b3fc
Add support for SETNPr to lower to memory form.
...
llvm-svn: 19248
2005-01-02 02:37:46 +00:00
33660426a5
Spill/restore X86 floating point stack registers with 64-bits of precision
...
instead of 80-bits of precision. This fixes PR467.
This change speeds up fldry on X86 with LLC from 7.32s on apoc to 4.68s.
llvm-svn: 18433
2004-12-02 18:17:31 +00:00
e9bfa5a2a4
Add some new instructions. Fix the asm string for sbb32rr
...
llvm-svn: 16759
2004-10-06 04:01:02 +00:00
7c16caa336
Changes For Bug 352
...
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
7c98308013
Reduce uses of getRegClass
...
llvm-svn: 15973
2004-08-21 20:13:52 +00:00
a0b38d3cb1
Code insertion methods now return void instead of an int.
...
llvm-svn: 15780
2004-08-15 22:15:11 +00:00
98de1d7795
These methods no longer take a TargetRegisterClass* operand.
...
llvm-svn: 15774
2004-08-15 21:56:44 +00:00
a4da0d6294
Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent
...
llvm-svn: 15739
2004-08-14 22:05:10 +00:00
8a4039ed9a
Reserve the correct amt of space.
...
llvm-svn: 14913
2004-07-17 20:24:05 +00:00
c2726e63ed
Delete the allocate*TargetMachine function, which is now dead .
...
The shared command line options are now in a header that makes sense.
llvm-svn: 14756
2004-07-11 04:17:10 +00:00
eb04d9bcb4
Add #include <iostream> since Value.h does not #include it any more.
...
llvm-svn: 14622
2004-07-04 12:19:56 +00:00
c22299d21b
Spell out `NoFramePointerElim' for readability.
...
llvm-svn: 14299
2004-06-21 21:17:44 +00:00
5cb198a9c6
Use the common `NoFPElim' setting instead of our own.
...
llvm-svn: 14298
2004-06-21 21:10:24 +00:00
6b7275996c
Rename Type::PrimitiveID to TypeId and ::getPrimitiveID() to ::getTypeID()
...
llvm-svn: 14201
2004-06-17 18:19:28 +00:00
a0cfedef3a
Add support for the setp instructions
...
llvm-svn: 14140
2004-06-11 04:30:06 +00:00
82baa9c394
Convert to the new TargetMachine interface.
...
llvm-svn: 13952
2004-06-02 05:55:25 +00:00
d186ed02e4
Add more ADC and SBB variants
...
llvm-svn: 12607
2004-04-02 07:11:10 +00:00
358c97e7ae
Implement spill code folding for all of the conditional move instructions
...
llvm-svn: 12554
2004-03-30 21:29:47 +00:00
4837f6c0d9
Another API change to MRegisterInfo::foldMemoryOperand. Instead of a
...
MachineBasicBlock::iterator take a MachineInstr*.
llvm-svn: 12392
2004-03-14 20:14:27 +00:00
48da2f8a6d
Change MRegisterInfo::foldMemoryOperand to return the folded
...
instruction to make the API more flexible.
llvm-svn: 12386
2004-03-14 07:19:51 +00:00
d6f62ba55b
Add memory operand version of conditional move.
...
llvm-svn: 12190
2004-03-07 03:19:11 +00:00
ea81b79a97
A big X86 instruction rename. The instructions are renamed to make
...
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register
IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
llvm-svn: 11995
2004-02-29 08:50:03 +00:00
fa63580517
SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
...
to denote this fact.
llvm-svn: 11972
2004-02-28 23:46:44 +00:00
4953ae085a
Floating point loads/stores act on memory operands. Rename them to
...
denote this fact.
llvm-svn: 11971
2004-02-28 23:42:35 +00:00
5b5dee4afb
Uncomment instructions that take both an immediate and a memory
...
operand but their sizes differ.
llvm-svn: 11969
2004-02-28 22:06:59 +00:00
2debead504
Do not generate instructions with mismatched memory/immediate sized
...
operands. The X86 backend doesn't handle them properly right now.
llvm-svn: 11944
2004-02-28 06:01:43 +00:00
9476b7cbe5
Add memory operand folding support for the SETcc family of
...
instructions.
llvm-svn: 11907
2004-02-27 16:13:37 +00:00
8d99063b38
Add memory operand folding support for SHLD and SHRD instructions.
...
llvm-svn: 11905
2004-02-27 15:03:18 +00:00
3537404299
Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.
...
llvm-svn: 11903
2004-02-27 09:28:43 +00:00
8358cc573d
Move MOTy::UseType enum into MachineOperand. This eliminates the
...
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).
llvm-svn: 11715
2004-02-22 19:23:26 +00:00
de51c65299
When folding memory operands in machine instructions be careful to
...
leave register operands with the same use/def flags as the original
instruction.
llvm-svn: 11709
2004-02-22 06:54:26 +00:00
30e73e3442
Add support for GlobalAddress's for alkis
...
llvm-svn: 11560
2004-02-17 18:23:55 +00:00
cf7b9392ea
Instructiosn with 1 memory operand have 4 operands in our
...
representation.. duh!
llvm-svn: 11554
2004-02-17 15:58:13 +00:00
f90da5f346
Align case statements.
...
llvm-svn: 11552
2004-02-17 15:50:41 +00:00
546513ccfd
Add TEST and XCHG memory operand support.
...
llvm-svn: 11550
2004-02-17 15:48:42 +00:00
f08064b714
Add OR and XOR memory operand support.
...
llvm-svn: 11549
2004-02-17 15:33:14 +00:00
e5585328d8
Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT,
...
MOVSX, and MOVZX.
llvm-svn: 11546
2004-02-17 09:14:23 +00:00
93398df103
Add memory operand folding for CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32}
...
and DECm{8,16,32} instructions.
llvm-svn: 11545
2004-02-17 08:49:20 +00:00
7f615d7e9a
Add support for folding memory operands for ADC, SBB and SUB instructions.
...
llvm-svn: 11541
2004-02-17 08:08:51 +00:00
7ef6d2fd0e
Add a (hidden) option to print instructions that fail to fuse. It's looking
...
like compares and test's would be the next huge win...
llvm-svn: 11539
2004-02-17 08:03:47 +00:00
6974f4758a
Add support for folding memory operands in MOVri{8,16,32} instructions.
...
llvm-svn: 11538
2004-02-17 07:47:20 +00:00
ca8f1c2716
Add an option to disable spill fusing in the X86 backend
...
llvm-svn: 11531
2004-02-17 06:30:34 +00:00
3abcdf3b90
Fix the mneumonics for the mov instructions to have the source and destination
...
order in the correct sense!! Arg!
llvm-svn: 11530
2004-02-17 06:28:19 +00:00
9990476875
GRRR. Move instructions have swapped the order of the r/m operands.
...
llvm-svn: 11528
2004-02-17 06:20:20 +00:00
01dded2e69
Change to match the newer, simpler, interface
...
llvm-svn: 11525
2004-02-17 05:54:57 +00:00
ba30c776a6
Add support for folding memory operands into AND and IMUL's
...
llvm-svn: 11523
2004-02-17 05:46:06 +00:00
8d6eebf0d7
Scrunchify code, by adding helpers. No functionality changes.
...
llvm-svn: 11522
2004-02-17 05:35:13 +00:00
cde4ade314
Add API to check and fold memory operands into instructions.
...
llvm-svn: 11519
2004-02-17 04:33:18 +00:00
43e82e1152
Fix the 'have a framepointer' case, so that the frame pointer always points
...
to the old saved EBP.
llvm-svn: 11455
2004-02-15 00:15:37 +00:00
f54cd1524d
There is no reason to align the stack pointer if there are no callees of this
...
function!
llvm-svn: 11450
2004-02-14 20:11:07 +00:00
7dceed5ff9
The prologue/epilogue related method calls have no reason to return a value,
...
make them return void.
This allows us to avoid some costly MBB.size() calls
llvm-svn: 11448
2004-02-14 19:49:54 +00:00
9f75a55329
finegrainify namespacification, fix 80col prob
...
llvm-svn: 11445
2004-02-14 06:00:36 +00:00
5a92240270
Use newly added next() and prior() utility functions.
...
llvm-svn: 11430
2004-02-14 01:18:34 +00:00
537805f315
Change interface so that we can add to the end of a basic block
...
without getting an assertion from ilist that we are dereferencing
ilist<T>::end().
llvm-svn: 11345
2004-02-12 08:11:04 +00:00
80da865f77
Change MachineBasicBlock's vector of MachineInstr pointers into an
...
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
llvm-svn: 11340
2004-02-12 02:27:10 +00:00
327426411e
Modify the two address instruction pass to remove the duplicate
...
operand of the instruction and thus simplify the register allocation.
llvm-svn: 11124
2004-02-04 22:17:40 +00:00
960707c335
Put all LLVM code into the llvm namespace, as per bug 109.
...
llvm-svn: 9903
2003-11-11 22:41:34 +00:00
9118a426d3
Change all machine basic block modifier functions in MRegisterInfo to
...
return the number of instructions added to/removed from the basic block
passed as their first argument.
Note: This is only needed because we use a std::vector instead of an
ilist to keep MachineBasicBlock instructions. Inserting an instruction
to a MachineBasicBlock invalidates all iterators to the basic
block. The return value can be used to update an index to the machine
basic block instruction vector and circumvent the iterator elimination
problem but this is really not needed if we move to a better
representation.
llvm-svn: 9704
2003-11-04 22:57:09 +00:00
482202a601
Added LLVM project notice to the top of every C++ source file.
...
Header files will be on the way.
llvm-svn: 9298
2003-10-20 19:43:21 +00:00
fdfe370406
Output a contorted sequence of instructions to make sure that we don't access
...
off the bottom of the stack. This fixes PR#41
llvm-svn: 9114
2003-10-14 19:09:05 +00:00
97c7a8ed1a
Disable the leaf function optimization, which is apparently not legal on
...
X86/linux. :( The problem is that a signal delivered while the function
is executing could clobber the functions stack. This is a partial fix
for PR41.
llvm-svn: 9113
2003-10-14 18:52:41 +00:00
7eb05a170a
Spell `necessary' correctly.
...
llvm-svn: 7944
2003-08-18 14:43:39 +00:00
6aa90493a3
Rename register classes to be upper case to make it obvious that they are X86
...
specific in the tree patterns
llvm-svn: 7578
2003-08-04 20:58:29 +00:00
a4741a94ff
Switch over to TableGen generated register file description
...
llvm-svn: 7511
2003-08-03 15:48:14 +00:00
bbc8db5266
Move "register flags" definition the type of registers to be fully fledged
...
value types
llvm-svn: 7377
2003-07-29 05:14:16 +00:00
30f40d94cc
Rename -no-* to -disable-*
...
llvm-svn: 5642
2003-02-26 20:00:41 +00:00
b2809dc6b5
Implement code to keep the stack pointer aligned to an 8 byte boundary.
...
This improves the performance of the power benchmark by a few percent.
This will be neccesary for SSE code, which requires 16 byte alignment of
the stack.
llvm-svn: 5320
2003-01-16 02:20:12 +00:00
9e75444c8b
Handle frame offset due to return address pushed on the stack
...
llvm-svn: 5319
2003-01-15 22:57:35 +00:00
06e07162fc
* Move frame and constant pool indexes to first argument of memory reference
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so we can put an offset in there as well...
* Fix long/ulong stuff
llvm-svn: 5231
2003-01-13 00:50:33 +00:00
26c23467c5
Rename FunctionFrameInfo to MachineFrameInfo
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llvm-svn: 5201
2002-12-28 21:08:28 +00:00
1d79b4ce86
*** Implement frame pointer elimination on X86!
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* Include contents of X86RegisterClasses.cpp into here
* Adjustments to register api to work with new frame manager
* Eliminate moveImm2Reg, getFramePointer, and getStackPointer
* Cleanup and simplify prolog/epilog code generation
* Prolog/epilog are MUCH more efficient now.
llvm-svn: 5186
2002-12-28 20:32:28 +00:00
dafa31658f
New simpler spill interface
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llvm-svn: 5148
2002-12-25 05:07:09 +00:00
d8201972bf
Fix compilation on gcc 2.96
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llvm-svn: 5116
2002-12-23 23:46:55 +00:00
6e7c821dc0
Fix warning
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llvm-svn: 5109
2002-12-20 04:13:28 +00:00
4cb8af96b3
Update to use new interface for register info
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llvm-svn: 5098
2002-12-17 04:19:17 +00:00
eaf58b03b2
Round number of bytes allocated on the stack up to a multiple of 4 so that the
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stack remains aligned
llvm-svn: 5095
2002-12-17 03:15:26 +00:00
5afbc4c387
Register allocator is responsible for spilling callee saved regs
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llvm-svn: 5092
2002-12-17 02:48:57 +00:00
c87fcde854
Fix prolog/epilog in the presence of alloca
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llvm-svn: 5087
2002-12-16 22:29:30 +00:00
6b5ca53493
Finish implementation of alias list impl
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llvm-svn: 5083
2002-12-16 19:31:48 +00:00
d44d25323d
Try #2 to get alias set stuff to work
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llvm-svn: 5077
2002-12-16 16:14:51 +00:00
4cf76c23e8
Add info about register file aliasing
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llvm-svn: 5074
2002-12-16 15:55:25 +00:00
3c1b59ca59
Correct the setting of Def flags on registers that are modified!
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llvm-svn: 5065
2002-12-15 22:38:47 +00:00
e2533336f5
Simplify interfaces used by regalloc to insert code
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llvm-svn: 5052
2002-12-15 20:06:35 +00:00
3374ec7c1b
Cleaned up the code: factored out switch/case into a separate function, put
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constants in an array for quick lookup. Stole the idea from elsewhere in
Jello.
llvm-svn: 5017
2002-12-13 12:00:06 +00:00
121ae7d3a7
Treat longs as ints => pretend they're all 32-bit values and squeeze them into
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32-bit registers.
llvm-svn: 5008
2002-12-13 10:43:09 +00:00
78401cbb3c
Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to
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PHI nodes.
llvm-svn: 5001
2002-12-13 09:54:12 +00:00
862f3ef8bc
Moves now select correct opcode based on the data size.
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llvm-svn: 4981
2002-12-13 04:24:53 +00:00
83e62f14dd
Implemented functions for emitting prologues and epilogues;
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removed EBP from the list of callee-saved registers (it isn't one).
llvm-svn: 4929
2002-12-04 23:57:03 +00:00
1af9bebcda
storeReg2RegOffset() and loadRegOffset2Reg() now take the iterator by value
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instead of by reference, since they return the modified iterator.
llvm-svn: 4914
2002-12-04 17:14:13 +00:00
0d28502c32
Moved buildReg2RegClassMap() into from X86RegisterInfo to MRegisterInfo, since
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it is target-independent.
llvm-svn: 4911
2002-12-04 16:47:04 +00:00
d9522256d3
Added support for callee- and caller-save registers.
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llvm-svn: 4897
2002-12-03 23:11:21 +00:00
aa15563510
Fix order of operands on a store from reg to [reg+offset].
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llvm-svn: 4857
2002-12-02 21:10:35 +00:00
5014e38273
Oops. Got the MOVrm and MOVmr mixed up. Fixed. We can now print out
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instructions correctly.
llvm-svn: 4830
2002-11-22 23:15:27 +00:00
bde217d7a9
Added methods to read/write values to stack in .h, fixed implementation in
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.cpp to return the iterator correctly.
llvm-svn: 4827
2002-11-22 22:43:47 +00:00
53d2de923a
Add definitions for function headers from MRegisterInfo.h:
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Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.
llvm-svn: 4784
2002-11-20 18:59:43 +00:00
d92fb0058b
Initial checkin of X86 backend.
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We can instruction select exactly one instruction 'ret void'. Wow.
llvm-svn: 4284
2002-10-25 22:55:53 +00:00
Chris Lattner