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540 Commits

Author SHA1 Message Date
Chad Rosier f0e8720054 [ms-inline asm] Add support for creating AsmRewrites in the target specific 
AsmParser logic.  To be used/tested in a subsequent commit.

llvm-svn: 166714
 2012-10-25 20:41:34 +00:00
Chad Rosier 4996355592 [ms-inline asm] Remove the MatchInstruction() function. Previously, this was 
the interface between the front-end and the MC layer when parsing inline
assembly.  Unfortunately, this is too deep into the parsing stack. Specifically,
we're unable to handle target-independent assembly (i.e., assembly directives,
labels, etc.).  Note the MatchAndEmitInstruction() isn't the correct
abstraction either.  I'll be exposing target-independent hooks shortly, so this
is really just a cleanup.

llvm-svn: 165858
 2012-10-13 00:26:04 +00:00
Chad Rosier 2f480a8a50 [ms-inline asm] Use the new API introduced in r165830 in lieu of the 
MapAndConstraints vector.  Also remove the unused Kind argument.

llvm-svn: 165833
 2012-10-12 22:53:36 +00:00
Craig Topper a004b0d303 In parseMSRMaskOperand, add an explicit check for the operand being an identifier instead of just having an assert. 
llvm-svn: 165480
 2012-10-09 04:55:28 +00:00
Chad Rosier 8f06e7dea4 [ms-inline asm] Add a few typedefs to simplify future changes. 
llvm-svn: 165324
 2012-10-05 18:41:14 +00:00
Chad Rosier f4e35dc672 [ms-inline asm] Add the convertToMapAndConstraints() function that is used to 
map constraints and MCInst operands to inline asm operands.  This replaces the
getMCInstOperandNum() function.

The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.

llvm-svn: 164979
 2012-10-01 23:45:51 +00:00
Sylvestre Ledru 91ce36c986 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 
llvm-svn: 164768
 2012-09-27 10:14:43 +00:00
Sylvestre Ledru 721cffd53a Fix a typo 'iff' => 'if' 
llvm-svn: 164767
 2012-09-27 09:59:43 +00:00
Jim Grosbach e974a6afaf ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'. 
rdar://9795790

llvm-svn: 164577
 2012-09-25 00:08:13 +00:00
Chad Rosier c4734c8950 Rather then have a wrapper function, have tblgen instantiate the implementation. 
Also remove an unused argument.

llvm-svn: 164567
 2012-09-24 22:57:55 +00:00
Chad Rosier 3cb355d11f Rather then have a wrapper function, have tblgen instantiate the implementation. 
llvm-svn: 164548
 2012-09-24 19:32:29 +00:00
Tim Northover 0c97e76492 Fix the handling of edge cases in ARM shifted operands. 
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

llvm-svn: 164455
 2012-09-22 11:18:12 +00:00
Chad Rosier 17ede627f0 [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser. 
llvm-svn: 164420
 2012-09-21 22:21:26 +00:00
Chad Rosier 143d0f7371 Add comment. 
llvm-svn: 164414
 2012-09-21 20:51:43 +00:00
Jim Grosbach 9659ed9813 Tidy up. Formatting. 
llvm-svn: 164343
 2012-09-21 00:26:53 +00:00
Chad Rosier 4109983fbc Rename the isMemory() function to isMem(). No functional change intended. 
llvm-svn: 163654
 2012-09-11 23:02:35 +00:00
Chad Rosier a05ea0f3e3 Fix function name per coding standard. 
llvm-svn: 163187
 2012-09-05 01:15:43 +00:00
Chad Rosier 9e2aff8b6d [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, add 
the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.

llvm-svn: 163124
 2012-09-03 20:31:23 +00:00
Chad Rosier 391d299737 [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in the 
MCTargetAsmParser class.

llvm-svn: 163122
 2012-09-03 18:47:45 +00:00
Chad Rosier a353dba17d Removed unused argument. 
llvm-svn: 163104
 2012-09-03 03:16:09 +00:00
Chad Rosier e38bb6a34e [ms-inline asm] Expose the Kind and Opcode variables from the 
MatchInstructionImpl() function.

These values are used by the ConvertToMCInst() function to index into the
ConversionTable.  The values are also needed to call the GetMCInstOperandNum()
function.

llvm-svn: 163101
 2012-09-03 02:06:46 +00:00
Chad Rosier 451ef13cde Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst() 
function nowadays.

llvm-svn: 163030
 2012-08-31 22:12:31 +00:00
Chad Rosier 9d1fc3672b Add a comment to explain what's really going on. 
llvm-svn: 163005
 2012-08-31 17:24:10 +00:00
Chad Rosier a8f3c4fe35 The ConvertToMCInst() function can't fail, so remove the now dead Match_ConversionFail enum. 
llvm-svn: 163002
 2012-08-31 16:41:07 +00:00
Chad Rosier 98cfa1044f With the fix in r162954/162955 every cvt function returns true. Thus, have 
the ConvertToMCInst() return void, rather then a bool.  Update all the cvt
functions as well.

llvm-svn: 162961
 2012-08-31 00:03:31 +00:00
Chad Rosier db482ef7a7 Fix for r162954. Return the Error. 
llvm-svn: 162955
 2012-08-30 23:22:05 +00:00
Chad Rosier 8513ffbb83 Move a check to the validateInstruction() function where it more properly belongs. 
llvm-svn: 162954
 2012-08-30 23:20:38 +00:00
Chad Rosier 5eec49fe09 Typo. 
llvm-svn: 162952
 2012-08-30 23:00:00 +00:00
Eric Christopher 6ac277ce91 Remove getARMRegisterNumbering and replace with calls into 
the register info for getEncodingValue. This builds on the
small patch of yesterday to set HWEncoding in the register
file.

One (deprecated) use was turned into a hard number to avoid
needing register info in the old JIT.

llvm-svn: 161628
 2012-08-09 22:10:21 +00:00
Jiangning Liu 6a43bf7d74 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. 
llvm-svn: 161162
 2012-08-02 08:29:50 +00:00
Jiangning Liu 288e1af8c8 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. 
llvm-svn: 161161
 2012-08-02 08:21:27 +00:00
Jiangning Liu 10dd40e42d Fix #13241, a bug around shift immediate operand for ARM instruction ADR. 
llvm-svn: 161159
 2012-08-02 08:13:13 +00:00
Richard Barton 984d0ba6b6 Some formatting to keep Clang happy 
llvm-svn: 159948
 2012-07-09 18:30:56 +00:00
Richard Barton 35aceb86fe Prevent ARM assembler from losing a right shift by #32 applied to a register 
llvm-svn: 159937
 2012-07-09 16:31:14 +00:00
Richard Barton d56603722e Spelling! 
llvm-svn: 159936
 2012-07-09 16:14:28 +00:00
Richard Barton a39625ecc6 Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable. 
llvm-svn: 159935
 2012-07-09 16:12:24 +00:00
Richard Barton 57b7d16e34 Teach assembler to handle capitalised operation values for DSB instructions 
llvm-svn: 159259
 2012-06-27 09:48:23 +00:00
Richard Barton 4b7558ef9a Prevent ARM Assembler crashing on unrecognised assembly format for DSB instruction 
llvm-svn: 159257
 2012-06-27 09:36:19 +00:00
Jim Grosbach 087affe2f3 ARM: Add a better diagnostic for some out of range immediates. 
As an example of how the custom DiagnosticType can be used to provide
better operand-mismatch diagnostics, add a custom diagnostic for
the imm0_15 operand class used for several system instructions.
Update the tests to expect the improved diagnostic.

rdar://8987109

llvm-svn: 159051
 2012-06-22 23:56:48 +00:00
Kevin Enderby 6c7279ec2e Fix the encoding of the armv7m (MClass) for MSR registers other than aspr, 
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.

llvm-svn: 158560
 2012-06-15 22:14:44 +00:00
Richard Barton b0ec375b96 Replace assertion failure for badly formatted CPS instrution with error message. 
llvm-svn: 158445
 2012-06-14 10:48:04 +00:00
Benjamin Kramer bde9176663 Fix typos found by http://github.com/lyda/misspell-check 
llvm-svn: 157885
 2012-06-02 10:20:22 +00:00
Craig Topper 42b96d1b74 Mark a static array as const. 
llvm-svn: 157368
 2012-05-24 04:11:15 +00:00
Kevin Enderby f1b225d0e0 Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing 
the 0b10 mask encoding bits.  Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use.  Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions.  Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025

llvm-svn: 157019
 2012-05-17 22:18:01 +00:00
Silviu Baranga 5a719f9b9a Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. 
llvm-svn: 156608
 2012-05-11 09:10:54 +00:00
Jim Grosbach c6f32b3295 ARM: Thumb add(sp plus register) asm constraints. 
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

llvm-svn: 155748
 2012-04-27 23:51:36 +00:00
Richard Barton 82f95ea2ad Fix ARM assembly parsing for upper case condition codes on IT instructions. 
llvm-svn: 155720
 2012-04-27 17:34:01 +00:00
Richard Barton f435b09eaf Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. 
llvm-svn: 155700
 2012-04-27 08:42:59 +00:00
Richard Barton ba5b0cc82e Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. 
llvm-svn: 155565
 2012-04-25 18:00:18 +00:00
Craig Topper 3ec7c2aa84 Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning. 
llvm-svn: 155538
 2012-04-25 06:56:34 +00:00