5333e2e5ce
Temporarily turn off anti-dependency checking
...
during Post RA scheduling in X86,
until the X86 target is changed to properly set up
post RA liveness.
llvm-svn: 154874
2012-04-16 22:52:28 +00:00
1fcf5bcae1
Prune some includes
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llvm-svn: 153502
2012-03-27 07:54:11 +00:00
5dfe6dab25
Remove extra semi-colons.
...
llvm-svn: 151169
2012-02-22 17:25:00 +00:00
1b81fddd65
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
...
llvm-svn: 150008
2012-02-07 22:50:41 +00:00
8523b16ff5
Instruction scheduling itinerary for Intel Atom.
...
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
4e7992eeba
PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.
...
llvm-svn: 149294
2012-01-30 23:10:32 +00:00
96cd35cf6d
Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.
...
Add a test that checks the stack alignment of a simple function for
Darwin, Linux and NetBSD for 32bit and 64bit mode.
llvm-svn: 147888
2012-01-10 22:43:53 +00:00
f287a4509e
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.
...
llvm-svn: 147770
2012-01-09 09:02:13 +00:00
744f6311d3
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
...
llvm-svn: 147762
2012-01-09 00:11:29 +00:00
dd286a5201
Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.
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llvm-svn: 147348
2011-12-29 19:25:56 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
...
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
1280eb1d06
Add XOP feature flag.
...
llvm-svn: 145682
2011-12-02 15:14:37 +00:00
228d9131aa
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
...
llvm-svn: 143319
2011-10-30 19:57:21 +00:00
49045ddb4c
Remove NaClMode
...
llvm-svn: 142338
2011-10-18 05:29:23 +00:00
e20793a4f1
Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147.
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llvm-svn: 142177
2011-10-17 05:33:10 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
6c8879e3ab
Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.
...
llvm-svn: 142089
2011-10-16 00:21:51 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
a14c5723eb
Put a bunch of calls to ToggleFeature behind proper if statements.
...
llvm-svn: 141527
2011-10-10 05:34:02 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
...
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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llvm-svn: 141007
2011-10-03 17:28:23 +00:00
6559656e73
Detect attempt to use segmented stacks on non ELF systems and error
...
(not assert) early.
llvm-svn: 139233
2011-09-07 16:10:57 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
...
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
...
llvm-svn: 138660
2011-08-26 21:21:21 +00:00
bc153d49b7
Next round of MC refactoring. This patch factor MC table instantiations, MC
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registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
2011-07-14 20:59:42 +00:00
c5e6d2f519
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
...
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
llvm-svn: 134884
2011-07-11 03:57:24 +00:00
fe2088bb1f
Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets.
...
llvm-svn: 134773
2011-07-08 23:43:01 +00:00
5286833f4a
Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets.
...
llvm-svn: 134768
2011-07-08 23:07:42 +00:00
60fc0fca5c
Restore old behavior. Always auto-detect features unless cpu or features are specified.
...
llvm-svn: 134757
2011-07-08 22:30:25 +00:00
e2f76c4ade
Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
...
llvm-svn: 134753
2011-07-08 22:16:47 +00:00
964cb5feb0
For non-x86 host, used generic as CPU name.
...
llvm-svn: 134741
2011-07-08 21:14:14 +00:00
4d1ca96bfc
Eliminate asm parser's dependency on TargetMachine:
...
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
llvm-svn: 134678
2011-07-08 01:53:10 +00:00
13bcc6c1c7
Add Mode64Bit feature and sink it down to MC layer.
...
llvm-svn: 134641
2011-07-07 21:06:52 +00:00
1a72add615
Compute feature bits at time of MCSubtargetInfo initialization.
...
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
c9c090d7a5
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
...
llvm-svn: 134281
2011-07-01 22:36:09 +00:00
0d639a28aa
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
...
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
54b68e3432
- Added MCSubtargetInfo to capture subtarget features and scheduling
...
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
llvm-svn: 134257
2011-07-01 20:45:01 +00:00
fe6e405e8c
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
...
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
llvm-svn: 134127
2011-06-30 01:53:36 +00:00
3a0c5e52ff
Remove TargetOptions.h dependency from X86Subtarget.
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llvm-svn: 133726
2011-06-23 17:54:54 +00:00
6f6b44d19d
Enable autodetect of popcnt
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llvm-svn: 131476
2011-05-17 18:33:37 +00:00
cd01ed5bd6
ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
...
triple component.
llvm-svn: 129838
2011-04-20 00:14:25 +00:00
100455a3c8
Target/X86: Eliminate uses of getDarwinVers().
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llvm-svn: 129813
2011-04-19 21:04:12 +00:00
e8a93fe8f0
Stack alignment is 16 bytes on FreeBSD/i386 too.
...
llvm-svn: 126226
2011-02-22 17:30:05 +00:00
bda7175a43
The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.
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llvm-svn: 126130
2011-02-21 17:37:17 +00:00
da2d2f4d1f
Experiment with changing the default 32-bit linux stack alignment to
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16 bytes for PR8969. Update all testcases accordingly.
llvm-svn: 123367
2011-01-13 06:47:10 +00:00
f8b4c0035b
Disable auto-detection of AVX support since AVX codegen support is not ready.
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llvm-svn: 121677
2010-12-13 04:23:53 +00:00
8b08f5232b
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
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llvm-svn: 121439
2010-12-10 00:26:57 +00:00
2bce78e8fc
Initialize HasPOPCNT.
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llvm-svn: 120923
2010-12-04 23:57:24 +00:00
447762da85
Merge System into Support.
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llvm-svn: 120298
2010-11-29 18:16:10 +00:00
db9820ecaa
Use rip-rel addressing on win64 by default. For this we just
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defaults to small pic code model.
llvm-svn: 111741
2010-08-21 17:21:11 +00:00
09dc24beac
Add x86 CLMUL (Carry-less multiplication) cpu feature
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llvm-svn: 109206
2010-07-23 01:17:51 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
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llvm-svn: 107625
2010-07-05 19:26:33 +00:00
faa7bdccbf
fix a nasty bug where we were not treating available_externally
...
symbols as declarations in the X86 backend. This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:
symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression
This fixes PR7353.
llvm-svn: 105954
2010-06-14 20:11:56 +00:00
dc53f1cb5c
FastISel doesn't yet handle callee-pop functions.
...
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
llvm-svn: 104866
2010-05-27 18:43:40 +00:00
050df1b8de
Enable i16 to i32 promotion by default.
...
llvm-svn: 102493
2010-04-28 08:30:49 +00:00
9c8cd8c061
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
...
llvm-svn: 101979
2010-04-21 01:47:12 +00:00
2ef63183a5
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
...
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
llvm-svn: 100231
2010-04-02 21:54:27 +00:00
738b0f9ec7
Nehalem unaligned memory access is fast.
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llvm-svn: 100089
2010-04-01 05:58:17 +00:00
bf724b9ee0
Turning off post-ra scheduling for x86. It isn't a consistent win.
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llvm-svn: 98810
2010-03-18 06:55:42 +00:00
402d6442c5
no really, all 64-bit cpu's have cmov support. This should
...
fix the rest of the buildbot failures on non-x86 hosts.
llvm-svn: 98522
2010-03-14 22:39:35 +00:00
091217be6f
Kill ModuleProvider and ghost linkage by inverting the relationship between
...
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.
Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.
Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735 .
llvm-svn: 94686
2010-01-27 20:34:15 +00:00
206351a1ff
Implement a feature (-vector-unaligned-mem) to allow targets to
...
ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
2010-01-11 16:29:42 +00:00
0041181684
Change errs() to dbgs().
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llvm-svn: 92648
2010-01-05 01:29:13 +00:00
71d7eaa87e
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
...
llvm-svn: 91910
2009-12-22 17:47:23 +00:00
4cf30b72bf
On recent Intel u-arch's, folding loads into some unary SSE instructions can
...
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
2009-12-18 07:40:29 +00:00
9528ccdd77
Don't enable the post-RA scheduler on x86 except at -O3. In its
...
current form, it is too expensive in compile time.
llvm-svn: 90781
2009-12-07 19:04:31 +00:00
7a6611793f
Target-independent support for TargetFlags on BlockAddress operands,
...
and support for blockaddresses in x86-32 PIC mode.
llvm-svn: 89506
2009-11-20 23:18:13 +00:00
241d01b590
Add llvm::sys::getHostCPUName, for detecting the LLVM name for the host CPU.
...
- This is an initial step towards -march=native support in Clang, and towards
eliminating host dependencies in the targets. See PR5389.
- Patch by Roman Divacky!
llvm-svn: 88768
2009-11-14 10:09:12 +00:00
b9fe5d5d02
Allow target to specify regclass for which antideps will only be broken along the critical path.
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llvm-svn: 88682
2009-11-13 19:52:48 +00:00
0d412c2528
Fixed to address code review. No functional changes.
...
llvm-svn: 86634
2009-11-10 00:48:55 +00:00
e4a2117161
Remove X86Subtarget::IsLinux. It's no longer being used.
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llvm-svn: 84200
2009-10-15 20:23:21 +00:00
1b38952c99
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
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llvm-svn: 80904
2009-09-03 07:04:02 +00:00
c3a0aba120
Make these functions static and local.
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llvm-svn: 80892
2009-09-03 05:47:34 +00:00
47455a79ae
X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
...
No functionality changes.
llvm-svn: 80880
2009-09-03 04:37:05 +00:00
cc8c581a5b
Add support for modeling whether or not the processor has support for
...
conditional moves as a subtarget feature. This is the easy part of
PR4841.
llvm-svn: 80763
2009-09-02 05:53:04 +00:00
f43ab91486
Short-term workaround for frame-related weirdness on win64.
...
Some other minor win64 fixes as well.
Patch by Michael Beck!
llvm-svn: 80370
2009-08-28 16:06:41 +00:00
1e9097e36a
change the -x86-asm-syntax=intel/att flag to be in X86TAI
...
instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
llvm-svn: 78746
2009-08-11 23:01:09 +00:00
4cc1feff4f
Remove some dead code.
...
llvm-svn: 78219
2009-08-05 18:12:37 +00:00
6eecd56efc
- s/DOUT/DEBUG(errs()/g
...
- Tidy up some headers.
llvm-svn: 77929
2009-08-03 00:11:34 +00:00
31b44e8f6c
Normalize Subtarget constructors to take a target triple string instead of
...
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
2009-08-02 22:11:08 +00:00
ac0ca9241a
Fix some minor MSVC compiler warnings.
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llvm-svn: 76356
2009-07-19 01:38:38 +00:00
02a765280f
GV with ghost linkage (module being lazily streamed in in JIT lazy compilation mode) do not require extra load from stub. This fixes ExecutionEngine/2005-12-02-TailCallBug.ll.
...
llvm-svn: 76121
2009-07-16 22:53:10 +00:00
7dce9919e1
fix indentation
...
llvm-svn: 75277
2009-07-10 21:01:59 +00:00
21c2940553
remove the now-dead TM argument to these methods.
...
llvm-svn: 75276
2009-07-10 21:00:45 +00:00
ba4d73310a
make PIC vs DynamicNoPIC be explicit in PICStyles.
...
llvm-svn: 75275
2009-07-10 20:58:47 +00:00
bd3e560f1a
some minor simplifications.
...
llvm-svn: 75274
2009-07-10 20:53:38 +00:00
e2f524f176
add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
...
llvm-svn: 75273
2009-07-10 20:47:30 +00:00
20073edf67
simplify fast isel by using ClassifyGlobalReference. This
...
elimiantes the last use of GVRequiresExtraLoad, so delete it.
llvm-svn: 75244
2009-07-10 07:48:51 +00:00
93f0f79178
eliminate GVRequiresRegister, replacing it with predicates we
...
need for other purposes.
llvm-svn: 75243
2009-07-10 07:38:24 +00:00
dc842c06c2
move some classification logic around. Now GVRequiresExtraLoad
...
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.
llvm-svn: 75237
2009-07-10 07:20:05 +00:00
b9af63a4d2
GVRequiresExtraLoad is now never used for calls, simplify it based on this.
...
llvm-svn: 75232
2009-07-10 05:52:02 +00:00
ace6ec26d9
actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
...
more complex and slow than just directly testing what we care about.
llvm-svn: 75231
2009-07-10 05:48:03 +00:00
7277a807f0
There is only one case where GVRequiresExtraLoad returns true for calls:
...
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.
llvm-svn: 75230
2009-07-10 05:45:15 +00:00
1cc7ae7c3b
the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
...
llvm-svn: 75229
2009-07-10 05:37:11 +00:00
fef11d6e77
simplify some code based on the fact that picstyles != none are only valid
...
in pic or dynamic-no-pic mode. Also, x86-64 never used picstylegot.
llvm-svn: 75101
2009-07-09 04:39:06 +00:00
821084a356
Reduce indentation in GVRequiresExtraLoad. Return true for windows
...
with DLLImport symbols even when in -static mode.
llvm-svn: 75093
2009-07-09 03:27:27 +00:00
8f6f72cc99
Add feature flags for AVX and FMA and fix some SSE4A feature flag
...
initialization problems.
llvm-svn: 74350
2009-06-26 22:46:54 +00:00
77d1943637
The attached patches implement most of the ARM AAPCS-VFP hard float
...
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
llvm-svn: 73095
2009-06-08 22:53:56 +00:00
96180b5387
Update CPU capabilities for AMD machines
...
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
llvm-svn: 72434
2009-05-26 21:04:35 +00:00
Preston Gurd