7867793aff
Add new TargetLowering code to provide the final register type that an
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illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
llvm-svn: 37781
2007-06-28 23:29:44 +00:00
df0c705d7d
If a livein is not used in the block. It's live through.
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llvm-svn: 37764
2007-06-27 18:47:28 +00:00
77f541ddfd
Partial fix for PR1502: If a EH register is needed in a successor of landing pad, add it as livein to all the blocks in the paths between the landing pad and the specified block.
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llvm-svn: 37763
2007-06-27 18:45:32 +00:00
3b62d7265d
Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT.
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llvm-svn: 37758
2007-06-27 16:08:04 +00:00
7139a48057
Use getVectorTypeBreakdown in FunctionLoweringInfo::CreateRegForValue
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to compute the number and type of registers needed for vector values
instead of computing it manually. This fixes PR1529.
llvm-svn: 37755
2007-06-27 14:34:07 +00:00
f4e86da3a6
Make the comment for ScalarizeVectorOp mention that it is only for use
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with single-element vectors.
llvm-svn: 37752
2007-06-27 14:06:22 +00:00
95759c0e78
ok, this is something of a dirty hack, but it seems to work. (fixes e.g.
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the SPASS miscompilation)
llvm-svn: 37750
2007-06-27 09:01:14 +00:00
89183dcc14
ok, this much doesn't seem to bork anything
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llvm-svn: 37749
2007-06-27 08:31:07 +00:00
a415dcaa2a
revert evan's fixes (and my doofusness) since they had a huge code
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quality hit. will look at this soon.
llvm-svn: 37748
2007-06-27 08:11:59 +00:00
540d329542
pull evan's fixes - should help the nightly tester (but there are still
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some issues)
llvm-svn: 37747
2007-06-27 07:07:13 +00:00
e66f822ecc
Replace std::set with SmallPtrSet.
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llvm-svn: 37746
2007-06-27 05:23:00 +00:00
6cf1371456
Fix an obvious bug. Old code only worked for the entry block.
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llvm-svn: 37743
2007-06-27 01:16:36 +00:00
4bf87f1f44
Correctly handle implcit def / use operands.
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llvm-svn: 37740
2007-06-26 21:05:13 +00:00
d8417d9199
Properly handle kills of a physical register which has sub-registers that are read by later instructions.
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llvm-svn: 37739
2007-06-26 21:03:35 +00:00
f4dc5b26e2
tidy this file up a bit
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llvm-svn: 37725
2007-06-26 00:21:58 +00:00
77416383e8
A bunch of fixes to the BigBlock allocator improve compile-time by ~20%
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and code quality by ~2% on my tests.
A big thank you to Roman Levenstein for this patch! See
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070618/050717.html
for more details.
llvm-svn: 37724
2007-06-25 23:46:54 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
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extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
81a752aa95
check in the BigBlock local register allocator
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llvm-svn: 37703
2007-06-22 08:27:12 +00:00
e3c4419953
std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
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llvm-svn: 37701
2007-06-22 01:35:51 +00:00
8e8d34b220
Tidy up ValueType names in comments.
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llvm-svn: 37688
2007-06-21 14:48:26 +00:00
04deef3a49
Rename TargetLowering::getNumElements and friends to
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TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
llvm-svn: 37687
2007-06-21 14:42:22 +00:00
aa5f5d960d
Xforms:
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(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
llvm-svn: 37685
2007-06-21 07:39:16 +00:00
a955c02c9b
Avoid if-converting simple block that ends with unconditional branch or fallthrough unless it branches / falls to the 'false' block. Not profitable, may end up increasing code size.
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llvm-svn: 37660
2007-06-19 21:45:13 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
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for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
37228f6ce5
document and hide two options.
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llvm-svn: 37651
2007-06-19 05:47:49 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
26be02febf
add isVarArg to CCState
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llvm-svn: 37640
2007-06-19 00:11:09 +00:00
0598b2d5eb
Fix some fragile code wrt CFG edge updating.
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llvm-svn: 37634
2007-06-18 22:44:57 +00:00
2afd702c20
Move CorrectExtraCFGEdges() from BranchFolding.cpp to a MachineBasicBlock method.
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llvm-svn: 37633
2007-06-18 22:43:58 +00:00
e31adc8ab9
make ComputeTopDownOrdering significantly faster and use less stack space
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by making it non-recursive
llvm-svn: 37629
2007-06-18 21:28:10 +00:00
8c7333266c
Make chain dependencies blue, in addition to being dashed.
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llvm-svn: 37626
2007-06-18 15:30:16 +00:00
51eb2c3bbe
Properly remove duplicate instructions as result of diamond if-conversion. Other bug fixes.
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llvm-svn: 37623
2007-06-18 08:37:25 +00:00
3a51c854d0
Really turn if-converter loose:
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1. Consider all possible ifcvt cases at once. No longer restricted to bottom
up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.
llvm-svn: 37613
2007-06-16 09:34:52 +00:00
e199f97fa8
Codegen support (stripped out) for the annotate attribute.
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llvm-svn: 37608
2007-06-15 22:26:58 +00:00
23402fcaef
Not every predicable block can be safely duplicated.
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llvm-svn: 37607
2007-06-15 21:18:05 +00:00
f852e339b6
Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
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for tied register constraints.
llvm-svn: 37601
2007-06-15 19:11:01 +00:00
234a90e83e
MachineInstr::isPredicable() is no longer needed.
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llvm-svn: 37599
2007-06-15 19:06:07 +00:00
92bf2c628c
Workaround for PR1508.
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llvm-svn: 37597
2007-06-15 19:04:19 +00:00
cd5f5e3ecd
Extra edges are deleted later if needed.
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llvm-svn: 37593
2007-06-15 17:34:48 +00:00
92fb5453c3
Allow small blocks to be duplicated to enable if-conversion.
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llvm-svn: 37590
2007-06-15 07:36:12 +00:00
add977670f
No really, clear predcessors states.
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llvm-svn: 37581
2007-06-14 23:34:09 +00:00
9fc56c079d
If BB is predicated, invalidate its predecessor(s) which would if-convert it. It needs to be re-analyzed.
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llvm-svn: 37580
2007-06-14 23:13:19 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
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llvm-svn: 37579
2007-06-14 22:58:02 +00:00
e08f0eefa6
Fix typo.
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llvm-svn: 37577
2007-06-14 21:26:08 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
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implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
1e6f08b2a2
Fix some stupid bugs that have effectively disabled if-conversion.
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llvm-svn: 37575
2007-06-14 20:28:52 +00:00
7413736a7e
Only correctly lower exception handing intrinsics if exception handling is
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turned on. Likewise for scanning of invokes to mark landing pads.
llvm-svn: 37570
2007-06-13 16:53:21 +00:00
26455c4ae0
Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
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VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.
This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.
llvm-svn: 37569
2007-06-13 15:12:02 +00:00
Dan Gohman