llvm-project

Commit Graph

Author	SHA1	Message	Date
Stanislav Mekhanoshin	3bffb1cd0e	[AMDGPU] Use single cache policy operand Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469	2021-03-15 13:00:59 -07:00
Stanislav Mekhanoshin	a8d9d50762	[AMDGPU] gfx90a support Differential Revision: https://reviews.llvm.org/D96906	2021-02-17 16:01:32 -08:00
Matt Arsenault	4a9a4885ae	AMDGPU: Convert test to MIR Currently the dbg_value ends up in the relaxed branch block. A future commit will push the dbg_value out of this block, and I'm not sure how to coax the IR into producing the same MIR at the relevant point.	2020-09-01 11:01:02 -04:00

Author

SHA1

Message

Date

Stanislav Mekhanoshin

3bffb1cd0e

[AMDGPU] Use single cache policy operand

Replace individual operands GLC, SLC, and DLC with a single cache_policy
bitmask operand. This will reduce the number of operands in MIR and I hope
the amount of code. These operands are mostly 0 anyway.

Additional advantage that parser will accept these flags in any order unlike
now.

Differential Revision: https://reviews.llvm.org/D96469

2021-03-15 13:00:59 -07:00

Stanislav Mekhanoshin

a8d9d50762

[AMDGPU] gfx90a support

Differential Revision: https://reviews.llvm.org/D96906

2021-02-17 16:01:32 -08:00

Matt Arsenault

4a9a4885ae

AMDGPU: Convert test to MIR

Currently the dbg_value ends up in the relaxed branch block. A future
commit will push the dbg_value out of this block, and I'm not sure how
to coax the IR into producing the same MIR at the relevant point.

2020-09-01 11:01:02 -04:00

3 Commits