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8 Commits

Author SHA1 Message Date
Craig Topper 12d0753aca [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32. 
The patterns that use this really want to know if the operand has at
least 32 sign/zero bits.

This increases opportunities to use W instructions when the original
source used i8/i16. Not sure how much this matters for performance,
but it makes i8/i16 code more consistent with i32.
 2021-01-24 13:58:14 -08:00
Craig Topper 60ebf6408e [RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16. 2021-01-24 13:48:29 -08:00
Michael Munday e28b6a60bc [RISCV][NFC] Regenerate RISCV CodeGen tests 
Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Differential Revision: https://reviews.llvm.org/D92841
 2020-12-09 19:42:49 +00:00
Luis Marques 3d0fbafd0b [RISCV] Switch to the Machine Scheduler 
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106
 2019-09-17 11:15:35 +00:00
Luis Marques 2d550d19b3 Revert Patch from Phabricator 
This reverts r372092 (git commit e38695a025)

llvm-svn: 372104
 2019-09-17 10:52:09 +00:00
Luis Marques e38695a025 Patch from Phabricator 
llvm-svn: 372092
 2019-09-17 09:43:08 +00:00
Alex Bradbury 7539fa2c2d [RISCV] Implement RV64D codegen 
This patch:
* Adds necessary RV64D codegen patterns
* Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI)

Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type.

Differential Revision: https://reviews.llvm.org/D53237

llvm-svn: 352833
 2019-02-01 03:53:30 +00:00
Alex Bradbury 60baa2e015 [RISCV] Codegen support for RV32D floating point conversion operations 
This also includes support and a test for truncating stores, which are now
possible thanks to the fpround pattern.

llvm-svn: 329876
 2018-04-12 05:47:15 +00:00