OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
384,207 Commits 32 Branches 0 Tags 2.2 GiB
Commit Graph

4 Commits

Author SHA1 Message Date
Kazushi (Jam) Marukawa 24faa87075 [VE] Update VELIntrinsic tests 
Update comment and style of regression tests for VELIntrinsic

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D94490
 2021-01-13 00:12:50 +09:00
Kazushi (Jam) Marukawa 44a4f93925 [VE] Optimize leaf functions 
Optimize leaf functions by not generating save/restore for callee saved
registers.  Update regression tests also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91539
 2020-11-17 00:38:01 +09:00
Simon Moll 1c00d096a6 [VE] LVLGen sets VL before vector insts 
The VE backend represents vector instructions with an explicit 'i32'
vector length operand.  In the VE ISA, the vector length is always read
from the VL hardware register.  The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D91416
 2020-11-16 09:19:14 +01:00
Kazushi (Jam) Marukawa 410626c9b5 [VE] Support vld intrinsics 
Add intrinsics for vector load instructions.  Add a regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91332
 2020-11-13 07:34:42 +09:00